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[/] [vivado/] [steel-core.sim/] [sim_1/] [behav/] [xsim/] [xvlog.log] - Blame information for rev 11

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Line No. Rev Author Line
1 11 rafaelcalc
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/alu.v" into library xil_defaultlib
2
INFO: [VRFC 10-311] analyzing module alu
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/branch_unit.v" into library xil_defaultlib
4
INFO: [VRFC 10-311] analyzing module branch_unit
5
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/csr_file.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module csr_file
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/decoder.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module decoder
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/imm_generator.v" into library xil_defaultlib
10
INFO: [VRFC 10-311] analyzing module imm_generator
11
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/integer_file.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module integer_file
13
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/load_unit.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module load_unit
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/machine_control.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module machine_control
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INFO: [VRFC 10-2458] undeclared symbol FUNCT7_wfi, assumed default net type wire [/home/rafa/ufrgs/steel-core/rtl/machine_control.v:136]
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INFO: [VRFC 10-2458] undeclared symbol RS2_ADDR_wfi, assumed default net type wire [/home/rafa/ufrgs/steel-core/rtl/machine_control.v:141]
19
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/steel_top.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module steel_top
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INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/store_unit.v" into library xil_defaultlib
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INFO: [VRFC 10-311] analyzing module store_unit
23
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/rafa/ufrgs/steel-core/rtl/bench/tb_compliance.v" into library xil_defaultlib
24
INFO: [VRFC 10-311] analyzing module tb_compliance

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