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Subversion Repositories steelcore

[/] [vivado/] [steel-core.srcs/] [constrs_1/] [new/] [contraints.xdc] - Blame information for rev 11

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Line No. Rev Author Line
1 11 rafaelcalc
set_property PACKAGE_PIN E3 [get_ports CLK]
2
set_property IOSTANDARD LVCMOS33 [get_ports CLK]
3
create_clock -period 10.000 -name CLK -waveform {0.000 5.000} [get_ports CLK]
4
 
5
set_property PACKAGE_PIN U9 [get_ports RESET]
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set_property IOSTANDARD LVCMOS33 [get_ports RESET]
7
 
8
set_property PACKAGE_PIN D4 [get_ports UART_TX]
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set_property IOSTANDARD LVCMOS33 [get_ports UART_TX]
10
 
11
set_property CFGBVS VCCO [current_design]
12
set_property CONFIG_VOLTAGE 3.3 [current_design]

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