OpenCores
URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

[/] [vivado/] [steel-core.srcs/] [sim_1/] [imports/] [steel-core/] [rtl/] [bench/] [tb_integer_file.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
2
// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
3
// 
4
// Create Date: 03.04.2020 18:35:35
5
// Module Name: tb_integer_file
6
// Project Name: Steel Core
7
// Description: 32-bit Integer Register File testbench
8
// 
9
// Dependencies: globals.vh
10
//               integer_file.v
11
// 
12
// Version 0.01
13
// 
14
//////////////////////////////////////////////////////////////////////////////////
15
 
16
/*********************************************************************************
17
 
18
MIT License
19
 
20
Copyright (c) 2020 Rafael de Oliveira Calçada
21
 
22
Permission is hereby granted, free of charge, to any person obtaining a copy
23
of this software and associated documentation files (the "Software"), to deal
24
in the Software without restriction, including without limitation the rights
25
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
26
copies of the Software, and to permit persons to whom the Software is
27
furnished to do so, subject to the following conditions:
28
 
29
The above copyright notice and this permission notice shall be included in all
30
copies or substantial portions of the Software.
31
 
32
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
33
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
34
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
35
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
36
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
37
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38
SOFTWARE.
39
 
40
********************************************************************************/
41
 
42
`timescale 1ns / 1ps
43
`include "../globals.vh"
44
 
45
module tb_integer_file();
46
 
47
    reg CLK;
48
 
49
    reg [4:0] RS_1_ADDR;
50
    reg [4:0] RS_2_ADDR;
51
    wire [31:0] RS_1;
52
    wire [31:0] RS_2;
53
 
54
    reg [4:0] RD_ADDR;
55
    reg WR_EN;
56
    reg [31:0] RD;
57
 
58
    integer_file dut(
59
 
60
        .CLK(               CLK),
61
 
62
        .RS_1_ADDR(         RS_1_ADDR),
63
        .RS_2_ADDR(         RS_2_ADDR),
64
        .RD_ADDR(           RD_ADDR),
65
        .RS_1(              RS_1),
66
        .RS_2(              RS_2),
67
 
68
        .WR_EN(             WR_EN),
69
        .RD(                RD)
70
 
71
    );
72
 
73
    integer i;
74
 
75
    always
76
    begin
77
        #10 CLK = !CLK;
78
    end
79
 
80
    initial
81
    begin
82
 
83
        $display("Testing Integer Register File...");
84
 
85
        CLK = 1'b0;
86
 
87
        RS_1_ADDR = 5'b00000;
88
        RS_2_ADDR = 5'b00000;
89
        RD_ADDR = 5'b00000;
90
        WR_EN = 1'b0;
91
        RD = 32'b0;
92
 
93
        $display("Testing values on power up...");
94
 
95
        for(i = 0; i < 32; i=i+1)
96
        begin
97
 
98
            RS_1_ADDR = i[4:0];
99
 
100
            #20;
101
 
102
            if(RS_1 != 32'h00000000)
103
            begin
104
                $display("FAIL. Check the results.");
105
                $finish;
106
            end
107
 
108
        end
109
 
110
        $display("Power up values OK.");
111
 
112
        $display("Testing write operation...");
113
 
114
        for(i = 0; i < 32; i=i+1)
115
        begin
116
 
117
            RD_ADDR = i[4:0];
118
            WR_EN = 1'b1;
119
            RD = $random;
120
 
121
            #20;
122
 
123
            WR_EN = 1'b0;
124
            RS_1_ADDR = RD_ADDR;
125
            RS_2_ADDR = RD_ADDR;
126
 
127
            #20;
128
 
129
            if(RD_ADDR == 5'b00000)
130
            begin
131
                if(RS_1 != 32'h00000000)
132
                begin
133
                    $display("FAIL. Check the results.");
134
                    $finish;
135
                end
136
                if(RS_2 != 32'h00000000)
137
                begin
138
                    $display("FAIL. Check the results.");
139
                    $finish;
140
                end
141
            end
142
            if(RD_ADDR != 5'b00000)
143
            begin
144
                if(RS_1 != RD)
145
                begin
146
                    $display("FAIL. Check the results.");
147
                    $finish;
148
                end
149
                if(RS_2 != RD)
150
                begin
151
                    $display("FAIL. Check the results.");
152
                    $finish;
153
                end
154
            end
155
 
156
        end
157
 
158
        $display("Write operation seems to work.");
159
 
160
        $display("Integer Register File successfully tested.");
161
 
162
    end
163
 
164
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.