Subversion Repositories sts1

--------------------------------------------------------------------------------

-- Entity name: spe                                                                             --

-- Description: The code calculates the path BIP-8 parity over the SPE.         --

-- It is the even parity, over all 783 bytes of SPE, which is put in            --

-- SPE(2,1). SPE(2,1) is the 2nd row and the first column of SPE, which has     --

-- 87 columns and 9 rows, representing 783 bytes. It is assumed here. that      --

-- (9 x 86) bytes of payload has already been generated, the program will       --

-- calculate the BIP now, and buffer that, till its location is arrived.        --

-- INPUT: Program recieves input from 7 VT Groups. The VT Groups are taken      --

-- as component.                                                                                        --

-- The program generates 9 x 87  SPE by taking 9 x 84 payload.                  --

-- NOTE: In this program the J1 and Path BIP-8 is given only                    --

--                                                                                                      --

--              ** Project Maintainers: Feeroz Akhter Khan **                           --

--                                              and Dr. Subrat Kar **                           --

--                              Dept. of Electrical Engineering, IIT Delhi              --

--------------------------------------------------------------------------------

library ieee;

library work;

use ieee.std_logic_1164.all;

use work.all;

---------------------------------

entity spe is

port (

  spe_data : out bit_vector(7 downto 0)

    );

 end spe;

------------------------------------

architecture behv of spe is

component vtg is

  port (

    vtg_data : out bit_vector(7 downto 0)

    );

end component;

component vtg_2 is

  port (

    vtg_2_data : out bit_vector(7 downto 0)

    );

end component;

component vtg_3 is

  port (

    vtg_3_data : out bit_vector(7 downto 0)

    );

end component;

component vtg_4 is

  port (

    vtg_4_data : out bit_vector(7 downto 0)

    );

end component;

component vtg_5 is

  port (

    vtg_5_data : out bit_vector(7 downto 0)

    );

end component;

component vtg_6 is

  port (

    vtg_6_data : out bit_vector(7 downto 0)

    );

end component;

component vtg_7 is

  port (

    vtg_7_data : out bit_vector(7 downto 0)

    );

end component;

----------------------------------------------------

--declaration of the signals

signal spe_data_temp : bit_vector(7 downto 0);

subtype path_data is bit_vector(7 downto 0);

type trace_byte is array(15 downto 0) of path_data;

signal J1 : trace_byte;

----------------------------------------------------

signal path_parity : bit_vector(7 downto 0) := "00000000";

signal B3 : bit_vector(7 downto 0) := "00000000";

signal C2 : bit_vector(7 downto 0) := "00000010";

signal FF : bit_vector(7 downto 0) := "01111110";        -- FF is the fixed stuff, which is put to non designed bytes

signal vtg_1_byte : bit_vector(7 downto 0);   --for port map of the indata

signal vtg_2_byte : bit_vector(7 downto 0);   --for port map of the indata

signal vtg_3_byte : bit_vector(7 downto 0);   --for port map of the indata

signal vtg_4_byte : bit_vector(7 downto 0);   --for port map of the indata

signal vtg_5_byte : bit_vector(7 downto 0);   --for port map of the indata

signal vtg_6_byte : bit_vector(7 downto 0);   --for port map of the indata

signal vtg_7_byte : bit_vector(7 downto 0);   --for port map of the indata

signal spe_clk : bit := '0';                --clk rate of prbsgen

signal payload_only_clk : bit := '0';

signal vtg_clk : bit := '0';

type col is range 1 to 87;

signal spe_col : col;

type row is range 1 to 9;

signal spe_row : row;

signal spe_data_temp1 : bit_vector(7 downto 0);

signal spe_data_temp2 : bit_vector(7 downto 0);

signal spe_data_temp3 : bit_vector(7 downto 0);

signal spe_data_temp4 : bit_vector(7 downto 0);

signal spe_data_temp5 : bit_vector(7 downto 0);

signal spe_data_temp6 : bit_vector(7 downto 0);

signal spe_data_temp7 : bit_vector(7 downto 0);

--------------------------------------

subtype data_word is bit_vector(7 downto 0);

type vtg_1_byte_buffer is array (755 downto 0) of data_word;

type vtg_2_byte_buffer is array (756 downto 0) of data_word;

type vtg_3_byte_buffer is array (757 downto 0) of data_word;

type vtg_4_byte_buffer is array (758 downto 0) of data_word;

type vtg_5_byte_buffer is array (759 downto 0) of data_word;

type vtg_6_byte_buffer is array (760 downto 0) of data_word;

type vtg_7_byte_buffer is array (761 downto 0) of data_word;

signal data_byte : data_word;

signal spe_1_buffer : vtg_1_byte_buffer;

signal spe_2_buffer : vtg_2_byte_buffer;

signal spe_3_buffer : vtg_3_byte_buffer;

signal spe_4_buffer : vtg_4_byte_buffer;

signal spe_5_buffer : vtg_5_byte_buffer;

signal spe_6_buffer : vtg_6_byte_buffer;

signal spe_7_buffer : vtg_7_byte_buffer;

----------------------------------------------------

begin

E1 : vtg port map(vtg_1_byte);

E2 : vtg_2 port map(vtg_2_byte);

E3 : vtg_3 port map(vtg_3_byte);

E4 : vtg_4 port map(vtg_4_byte);

E5 : vtg_5 port map(vtg_5_byte);

E6 : vtg_6 port map(vtg_6_byte);

E7 : vtg_7 port map(vtg_7_byte);

spe_clk <= not spe_clk after 79.821200510855683269476372924649 ns;

payload_only_clk <= not payload_only_clk after 82.671957671957671957671957671958 ns;

vtg_clk <= not vtg_clk after 0.5787037037037037037037037037037 us;

--vt15_clk <= not vt15_clk after 4.6296296296296296296296296296296 us;

--------------------------------------------------

spe_1_buffer(0) <= vtg_1_byte;

spe_2_buffer(0) <= vtg_2_byte;

spe_3_buffer(0) <= vtg_3_byte;

spe_4_buffer(0) <= vtg_4_byte;

spe_5_buffer(0) <= vtg_5_byte;

spe_6_buffer(0) <= vtg_6_byte;

spe_7_buffer(0) <= vtg_7_byte;

--------------------------------------------------------------

--Path Overheads

spe_data_temp <= B3 when (spe_row = 2 and spe_col = 1) else

    C2 when (spe_row = 3 and spe_col = 1) else

    FF when (spe_row = 4 and spe_col = 1) else

    FF when (spe_row = 5 and spe_col = 1) else

    FF when (spe_row = 6 and spe_col = 1) else

    FF when (spe_row = 7 and spe_col = 1) else

    FF when (spe_row = 8 and spe_col = 1) else

    FF when (spe_row = 9 and spe_col = 1) else

    FF when (spe_col = 30) else

    FF when (spe_col = 59);

spe_data <= spe_data_temp;

--------------------------------------------------------------

--Path Trace Byte

J1(0) <=  "00000001";

J1(1) <=  "00000010";

J1(2) <=  "00000011";

J1(3) <=  "00000100";

J1(4) <=  "00000101";

J1(5) <=  "00000110";

J1(6) <=  "00000111";

J1(7) <=  "00001000";

J1(8) <=  "00001001";

J1(9) <=  "00001010";

J1(10) <= "00001011";

J1(11) <= "00001100";

J1(12) <= "00001101";

J1(13) <= "00001110";

J1(14) <= "00001111";

J1(15) <= "00010000";

--------------------------------------------------------------

process(spe_col)

variable trace : integer := 0;

begin

    if(spe_row = 1 and spe_col = 1) then

      spe_data_temp <= J1(trace);

      trace := trace + 1;

      if(trace = 15) then

        trace := 0;

      end if;

    end if;

end process;

--------------------------------------------------------------

--Path Parity calculation

process(spe_clk)

begin

      if(spe_clk'event and spe_clk = '0') then

          path_parity(7 downto 0) <= path_parity(7 downto 0) xor spe_data_temp(7 downto 0);

          if(spe_col = 87 and spe_row = 9) then

              B3(7 downto 0) <= path_parity(7 downto 0) xor spe_data_temp(7 downto 0);

          end if;

        end if;

end process;

--------------------------------------------------------------

-- Byte Interleaving of VT groups

-- To be included later

--------------------------------------------------------------

process(spe_clk)

begin

    if(spe_clk'event and spe_clk = '0') then

      spe_col <= spe_col + 1;

      if(spe_col = 87) then

        if(spe_row = 9) then

          spe_col <= 1;

          spe_row <= 1;

          else

          spe_col <= 1;

          spe_row <= spe_row + 1;

        end if;

      end if;

    end if;

end process;

process(spe_clk)

begin

    if (spe_clk'event and spe_clk = '0') then

      spe_data_temp1 <= spe_1_buffer(754);

      spe_data_temp2 <= spe_2_buffer(755);

      spe_data_temp3 <= spe_3_buffer(756);

      spe_data_temp4 <= spe_4_buffer(757);

      spe_data_temp5 <= spe_5_buffer(758);

      spe_data_temp6 <= spe_6_buffer(759);

      spe_data_temp7 <= spe_7_buffer(760);

    end if;

end process;

process(spe_clk)

begin

    if (spe_clk'event and spe_clk = '0') then

      case spe_row is

      when spe_row =>

        case spe_col is

        when spe_col=>

          if(spe_col = 1 or spe_col = 8 or spe_col = 15 or spe_col = 22 or spe_col = 30 or spe_col = 37 or spe_col = 44 or spe_col = 51 or spe_col = 59 or spe_col = 66 or spe_col = 73 or spe_col = 80) then

            spe_data_temp <= spe_data_temp1;

            spe_data <= spe_data_temp1;

          elsif(spe_col = 2 or spe_col = 9 or spe_col = 16 or spe_col = 23 or spe_col = 31 or spe_col = 38 or spe_col = 45 or spe_col = 52 or spe_col = 60 or spe_col = 67 or spe_col = 74 or spe_col = 81) then

            spe_data_temp <= spe_data_temp2;

            spe_data <= spe_data_temp2;

          elsif(spe_col = 3 or spe_col = 10 or spe_col = 17 or spe_col = 24 or spe_col = 32 or spe_col = 39 or spe_col = 46 or spe_col = 53 or spe_col = 61 or spe_col = 68 or spe_col = 75 or spe_col = 82) then

            spe_data_temp <= spe_data_temp3;

            spe_data <= spe_data_temp3;

          elsif(spe_col = 4 or spe_col = 11 or spe_col = 18 or spe_col = 25 or spe_col = 33 or spe_col = 40 or spe_col = 47 or spe_col = 54 or spe_col = 62 or spe_col = 69 or spe_col = 76 or spe_col = 83) then

            spe_data_temp <= spe_data_temp4;

            spe_data <= spe_data_temp4;

          elsif(spe_col = 5 or spe_col = 12 or spe_col = 19 or spe_col = 26 or spe_col = 34 or spe_col = 41 or spe_col = 48 or spe_col = 55 or spe_col = 63 or spe_col = 70 or spe_col = 77 or spe_col = 84) then

            spe_data_temp <= spe_data_temp5;

            spe_data <= spe_data_temp5;

          elsif(spe_col = 6 or spe_col = 13 or spe_col = 20 or spe_col = 27 or spe_col = 35 or spe_col = 42 or spe_col = 49 or spe_col = 56 or spe_col = 64 or spe_col = 71 or spe_col = 78 or spe_col = 85) then

            spe_data_temp <= spe_data_temp6;

            spe_data <= spe_data_temp6;

          elsif(spe_col = 7 or spe_col = 14 or spe_col = 21 or spe_col = 28 or spe_col = 36 or spe_col = 43 or spe_col = 50 or spe_col = 57 or spe_col = 65 or spe_col = 72 or spe_col = 79 or spe_col = 86) then

            spe_data_temp <= spe_data_temp7;

            spe_data <= spe_data_temp7;

          end if;

        when others =>

          NULL;

        end case;

     end case;

  end if;

end process;

------------------------------------------------

end behv;