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[/] [suslik/] [trunk/] [rtl/] [sim_test.v] - Blame information for rev 2

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1 2 gorand2
`timescale 1 ns / 100 ps
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module testram(input clk,input we, input [31:0] addrA, output reg [511:0] dataA,input [511:0] dataW);
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  reg [31:0] ram0 [32767:0];
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  always @(posedge clk)
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    begin
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      dataA<=
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      {
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        ram0[{addrA[16:6],4'd15}],
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        ram0[{addrA[16:6],4'd14}],
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        ram0[{addrA[16:6],4'd13}],
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        ram0[{addrA[16:6],4'd12}],
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        ram0[{addrA[16:6],4'd11}],
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        ram0[{addrA[16:6],4'd10}],
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        ram0[{addrA[16:6],4'd9}],
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        ram0[{addrA[16:6],4'd8}],
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        ram0[{addrA[16:6],4'd7}],
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        ram0[{addrA[16:6],4'd6}],
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        ram0[{addrA[16:6],4'd5}],
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        ram0[{addrA[16:6],4'd4}],
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        ram0[{addrA[16:6],4'd3}],
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        ram0[{addrA[16:6],4'd2}],
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        ram0[{addrA[16:6],4'd1}],
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        ram0[{addrA[16:6],4'd0}]
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      };
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      if (we)
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        begin
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          ram0[{addrA[16:6],4'd0}]<=dataW[31:0];
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          ram0[{addrA[16:6],4'd1}]<=dataW[63:32];
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          ram0[{addrA[16:6],4'd2}]<=dataW[95:64];
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          ram0[{addrA[16:6],4'd3}]<=dataW[127:96];
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          ram0[{addrA[16:6],4'd4}]<=dataW[159:128];
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          ram0[{addrA[16:6],4'd5}]<=dataW[191:160];
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          ram0[{addrA[16:6],4'd6}]<=dataW[223:192];
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          ram0[{addrA[16:6],4'd7}]<=dataW[255:224];
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          ram0[{addrA[16:6],4'd8}]<=dataW[287:256];
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          ram0[{addrA[16:6],4'd9}]<=dataW[319:288];
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          ram0[{addrA[16:6],4'd10}]<=dataW[351:320];
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          ram0[{addrA[16:6],4'd11}]<=dataW[383:352];
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          ram0[{addrA[16:6],4'd12}]<=dataW[415:384];
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          ram0[{addrA[16:6],4'd13}]<=dataW[447:416];
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          ram0[{addrA[16:6],4'd14}]<=dataW[479:448];
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          ram0[{addrA[16:6],4'd15}]<=dataW[511:480];
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        end
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    end
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endmodule
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module cpu2r6test();
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  reg clk=0;
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  wire busEnRead=1;
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  wire busEnWrite=1;
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  wire busRead;
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  wire busWrite;
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  wire [31:0] busAddr;
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  wire [511:0] busInput;
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  wire [511:0] ramDataA;
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  wire [511:0] ramDataW;
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  reg [511:0] dataW_reg;
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  reg we_reg=0;
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  wire we;
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  reg [31:0] addr_reg;
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  reg busRdy=0;
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  wire [31:0] ioBusAddr;
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  wire [1:0] ioBusSize;
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  wire [31:0] ioBusOut;
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  wire [31:0] ioBusIn;
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  reg ioBusRdy=0;
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  wire ioBusWr;
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  wire ioBusRd;
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  wire [3:0] dummy;
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  cpu2r6 mycpu2(clk,busEnRead,busEnWrite,busRdy,busRead,busWrite,busAddr,busInput,ramDataW,
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                ioBusAddr,ioBusSize,ioBusOut,ioBusIn,ioBusRdy,ioBusWr,ioBusRd,dummy);
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  testram ram0(clk,we,busAddr,ramDataA,ramDataW);
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  assign busInput=(we_reg && (busAddr==addr_reg)) ? dataW_reg : ramDataA;
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  assign we=busWrite;
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  always @(posedge clk)
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    begin
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      ioBusRdy<=ioBusWr || ioBusRd;
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      we_reg<=we;
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      dataW_reg<=ramDataW;
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      addr_reg<=busAddr;
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      busRdy<=busRead;
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      if (ioBusWr) $display("out addr %h,data %h",ioBusAddr,ioBusOut);
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      if (ioBusRd) $display("in addr %h",ioBusAddr);
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    end
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  always
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    #100 clk<=!clk;
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  initial
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    begin
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      $readmemh("testmem6.hex",ram0.ram0);
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      $monitor("r2=0x%h",mycpu2.regf0.ram0.regs[2]);
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    end
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endmodule
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