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hiroshi |
/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_baud.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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import uart_package:: * ;
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module uart_baud
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(
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input wire clk_i,
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input wire nrst_i,
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input u_reg_t u_reg,
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input codec_state_t rec_next_state,
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input u_codec_t trans_codec,
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input wire rxd_clean,
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output wire rec_clk_en,
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output wire rec_sample_pulse,
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output wire leading_edge,
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output wire timeout_signal,
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output wire trans_clk_en
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) ;
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// -------------------
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// -- receiver baud --
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// -------------------
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// -- leading edge generate --
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logic [3:0] rec_count ;
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logic [7:0] rec_divisor ;
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logic rxd_l ;
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logic [5:0] timeout_c ;
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always_ff @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0)
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rxd_l <= #1 1'b1 ;
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else
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rxd_l <= #1 rxd_clean ;
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end
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wire rec_count_enable = rec_count == 4'hf ;
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wire rec_count_sample = rec_count == 4'h8 ;
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assign leading_edge = (rxd_l & ~rxd_clean) && (rec_next_state == IDLE ||
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rec_next_state == TIMEOUT ||
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rec_next_state == STOP) ;
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always_ff @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0)
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rec_count <= #1 4'h0 ;
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else if(rec_next_state == IDLE || rec_count_enable == 1'b1 || leading_edge == 1'b1)
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rec_count <= #1 4'h0 ;
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else
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rec_count <= #1 rec_count + 4'h1 ;
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end
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wire rec_count_end = rec_divisor == u_reg.baud_reg && rec_count_enable == 1'b1 ;
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// sample pulse position -> baud_reg/2
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assign rec_sample_pulse = rec_divisor == {1'b0, u_reg.baud_reg[7:1]} && rec_count_sample == 1'b1 ;
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assign rec_clk_en = rec_count_end ;
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always_ff @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0)
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rec_divisor <= #1 8'h00 ;
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else if(rec_count_end == 1'b1 || rec_next_state == IDLE || leading_edge == 1'b1)
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rec_divisor <= #1 8'h00 ;
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else if(rec_count_enable == 1'b1)
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rec_divisor <= #1 rec_divisor + 8'h01 ;
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else
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rec_divisor <= #1 rec_divisor ;
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end
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// -- timeout counter --
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// about 4 character :: read for manual -> 4.3 Interrupt Identification Register (IIR)
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always_ff @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0)
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timeout_c <= #1 6'h00 ;
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else if(timeout_signal == 1'b1 || rec_next_state == IDLE || leading_edge == 1'b1)
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timeout_c <= #1 6'h00 ;
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else if(rec_count_end == 1'b1)
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timeout_c <= #1 timeout_c + 6'h01 ;
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else
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timeout_c <= #1 timeout_c ;
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end
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assign timeout_signal = timeout_c == 6'h28 && rec_count_end == 1'b1 ;
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// ----------------------
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// -- transmitter baud --
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// ----------------------
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logic [3:0] trans_count ;
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logic [7:0] trans_divisor ;
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wire trans_count_enable = trans_count == 4'hf ;
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always_ff @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0)
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trans_count <= #1 4'h0 ;
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else if(trans_codec.state == IDLE || trans_count_enable == 1'b1)
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trans_count <= #1 4'h0 ;
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else
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trans_count <= trans_count + 4'h1 ;
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end
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wire trans_count_end = trans_divisor == u_reg.baud_reg && trans_count_enable == 1'b1 ;
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assign trans_clk_en = trans_count_end ;
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always_ff @(posedge clk_i, negedge nrst_i) begin
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if(nrst_i == 1'b0)
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trans_divisor <= #1 8'h00 ;
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else if(trans_count_end == 1'b1 || trans_codec.state == IDLE)
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trans_divisor <= #1 8'h00 ;
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else if(trans_count_enable == 1'b1)
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trans_divisor <= #1 trans_divisor + 8'h01 ;
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else
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trans_divisor <= #1 trans_divisor ;
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end
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endmodule
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