| 1 |
2 |
hiroshi |
/* *****************************************************************************
|
| 2 |
|
|
* title: uart_16550_rll module *
|
| 3 |
|
|
* description: RS232 Protocol 16550D uart (mostly supported) *
|
| 4 |
|
|
* languages: systemVerilog *
|
| 5 |
|
|
* *
|
| 6 |
|
|
* Copyright (C) 2010 miyagi.hiroshi *
|
| 7 |
|
|
* *
|
| 8 |
|
|
* This library is free software; you can redistribute it and/or *
|
| 9 |
|
|
* modify it under the terms of the GNU Lesser General Public *
|
| 10 |
|
|
* License as published by the Free Software Foundation; either *
|
| 11 |
|
|
* version 2.1 of the License, or (at your option) any later version. *
|
| 12 |
|
|
* *
|
| 13 |
|
|
* This library is distributed in the hope that it will be useful, *
|
| 14 |
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
| 15 |
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
|
| 16 |
|
|
* Lesser General Public License for more details. *
|
| 17 |
|
|
* *
|
| 18 |
|
|
* You should have received a copy of the GNU Lesser General Public *
|
| 19 |
|
|
* License along with this library; if not, write to the Free Software *
|
| 20 |
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
|
| 21 |
|
|
* *
|
| 22 |
|
|
* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
|
| 23 |
|
|
* from http://www.gnu.org/licenses/lgpl.txt *
|
| 24 |
|
|
*****************************************************************************
|
| 25 |
|
|
* redleaflogic,ltd *
|
| 26 |
|
|
* miyagi.hiroshi@redleaflogic.biz *
|
| 27 |
|
|
* $Id: uart_codec_state.sv 108 2010-03-30 02:56:26Z hiroshi $ *
|
| 28 |
|
|
***************************************************************************** */
|
| 29 |
|
|
|
| 30 |
|
|
`ifdef SYN
|
| 31 |
|
|
/* empty */
|
| 32 |
|
|
`else
|
| 33 |
|
|
timeunit 1ps ;
|
| 34 |
|
|
timeprecision 1ps ;
|
| 35 |
|
|
`endif
|
| 36 |
|
|
import uart_package:: * ;
|
| 37 |
|
|
module uart_codec_state(input u_reg_t u_reg,
|
| 38 |
|
|
input u_codec_t codec,
|
| 39 |
|
|
input wire receiver_mode,
|
| 40 |
|
|
input wire timeout_signal,
|
| 41 |
|
|
output codec_state_t next_state
|
| 42 |
|
|
) ;
|
| 43 |
|
|
|
| 44 |
|
|
// import uart_package:: * ;
|
| 45 |
|
|
|
| 46 |
|
|
// -- count state -------------------
|
| 47 |
|
|
// - IDLE --> START -> SEND0..SEND6->SEND7->PARITY->STOP
|
| 48 |
|
|
// - ^ ^ | | ^ ^ |
|
| 49 |
|
|
// - | | +------+---->+------+ |
|
| 50 |
|
|
// - +---------+-------------------------------------+
|
| 51 |
|
|
// - IDLE -> START :: transmit data : start bit
|
| 52 |
|
|
// - STOP -> START :: transmit data : start bit
|
| 53 |
|
|
// - START -> SEND0 :: alway
|
| 54 |
|
|
// - SEND1 -> SEND2 :: alway
|
| 55 |
|
|
// - .......
|
| 56 |
|
|
// - SEND6 -> PARITY :: 7bit && parity
|
| 57 |
|
|
// - SEND6 -> STOP :: 7bit
|
| 58 |
|
|
// - SEND6 -> SEND7 :: 8bit
|
| 59 |
|
|
// - SEND7 -> PARITY :: 8bit && parity
|
| 60 |
|
|
// - SEND7 -> STOP :: 8bit
|
| 61 |
|
|
// - STOP -> IDLE :: not start bit
|
| 62 |
|
|
// ----------------------------------
|
| 63 |
|
|
always_comb begin
|
| 64 |
|
|
case (codec.state)
|
| 65 |
|
|
IDLE : begin
|
| 66 |
|
|
if(codec.start == 1'b1)
|
| 67 |
|
|
next_state = START ;
|
| 68 |
|
|
else
|
| 69 |
|
|
next_state = IDLE ;
|
| 70 |
|
|
end
|
| 71 |
|
|
|
| 72 |
|
|
TIMEOUT : begin
|
| 73 |
|
|
if(codec.start == 1'b1)
|
| 74 |
|
|
next_state = START ;
|
| 75 |
|
|
else if(timeout_signal == 1'b1 || u_reg.line_status_reg.data_ready == 1'b0)
|
| 76 |
|
|
next_state = IDLE ;
|
| 77 |
|
|
else
|
| 78 |
|
|
next_state = TIMEOUT ;
|
| 79 |
|
|
end
|
| 80 |
|
|
|
| 81 |
|
|
START : next_state = SEL_0 ;
|
| 82 |
|
|
SEL_0 : next_state = SEL_1 ;
|
| 83 |
|
|
SEL_1 : next_state = SEL_2 ;
|
| 84 |
|
|
SEL_2 : next_state = SEL_3 ;
|
| 85 |
|
|
SEL_3 : next_state = SEL_4 ;
|
| 86 |
|
|
SEL_4 : next_state = SEL_5 ;
|
| 87 |
|
|
SEL_5 : begin
|
| 88 |
|
|
if(u_reg.line_control_reg.char_length == CHAR_7_BIT)
|
| 89 |
|
|
next_state = DATA_END ;
|
| 90 |
|
|
else
|
| 91 |
|
|
next_state = SEL_6 ;
|
| 92 |
|
|
end
|
| 93 |
|
|
|
| 94 |
|
|
SEL_6 : next_state = DATA_END ;
|
| 95 |
|
|
|
| 96 |
|
|
DATA_END : begin
|
| 97 |
|
|
if(u_reg.line_control_reg.parity_enable == 1'b1)
|
| 98 |
|
|
next_state = PARITY ;
|
| 99 |
|
|
else
|
| 100 |
|
|
next_state = STOP ;
|
| 101 |
|
|
end
|
| 102 |
|
|
|
| 103 |
|
|
PARITY : next_state = STOP ;
|
| 104 |
|
|
|
| 105 |
|
|
STOP : begin
|
| 106 |
|
|
if(codec.start == 1'b1)
|
| 107 |
|
|
next_state = START ;
|
| 108 |
|
|
else if(u_reg.line_status_reg.data_ready == 1'b1 && receiver_mode == 1'b1)
|
| 109 |
|
|
next_state = TIMEOUT ;
|
| 110 |
|
|
else
|
| 111 |
|
|
next_state = IDLE ;
|
| 112 |
|
|
end
|
| 113 |
|
|
default : next_state = IDLE ;
|
| 114 |
|
|
endcase
|
| 115 |
|
|
end
|
| 116 |
|
|
endmodule
|
