OpenCores
URL https://opencores.org/ocsvn/systemverilog-uart16550/systemverilog-uart16550/trunk

Subversion Repositories systemverilog-uart16550

[/] [systemverilog-uart16550/] [trunk/] [rtl/] [uart_fifo.sv] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 hiroshi 
/* *****************************************************************************
2 
   * title:         uart_16550_rll module                                      *
3 
   * description:   RS232 Protocol 16550D uart (mostly supported)              *
4 
   * languages:     systemVerilog                                              *
5 
   *                                                                           *
6 
   * Copyright (C) 2010 miyagi.hiroshi                                         *
7 
   *                                                                           *
8 
   * This library is free software; you can redistribute it and/or             *
9 
   * modify it under the terms of the GNU Lesser General Public                *
10 
   * License as published by the Free Software Foundation; either              *
11 
   * version 2.1 of the License, or (at your option) any later version.        *
12 
   *                                                                           *
13 
   * This library is distributed in the hope that it will be useful,           *
14 
   * but WITHOUT ANY WARRANTY; without even the implied warranty of            *
15 
   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU         *
16 
   * Lesser General Public License for more details.                           *
17 
   *                                                                           *
18 
   * You should have received a copy of the GNU Lesser General Public          *
19 
   * License along with this library; if not, write to the Free Software       *
20 
   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111*1307  USA *
21 
   *                                                                           *
22 
   *         ***  GNU LESSER GENERAL PUBLIC LICENSE  ***                       *
23 
   *           from http://www.gnu.org/licenses/lgpl.txt                       *
24 
   *****************************************************************************
25 
   *                            redleaflogic,ltd                               *
26 
   *                    miyagi.hiroshi@redleaflogic.biz                        *
27 
   *          $Id: uart_fifo.sv 108 2010-03-30 02:56:26Z hiroshi $         *
28 
   ***************************************************************************** */
29 
 
30 
`ifdef SYN
31 
/* empty */
32 
`else
33 
timeunit      1ps ;
34 
timeprecision 1ps ;
35 
`endif
36 
 
37 
  // module uart_fifo #(parameter DATA_WIDTH = 8, parameter ADDR_WIDTH = 2)
38 
  import fifo_package:: * ;
39 
  module uart_fifo
40 
    (input wire clk_i,
41 
     input wire nrst_i,
42 
     input wire clear,
43 
     input wire [1:0] almost_empty_level,
44 
     fifo_bus   fifo_pop,
45 
     fifo_bus   fifo_push,
46 
     output wire all_error
47 
     ) ;
48 
 
49 
   parameter ADDR_WIDTH = 2 ;
50 
   parameter DATA_WIDTH = 2 ;
51 
 
52 
   //   u_fifo_t  #(DATA_WIDTH(8), ADDR_WIDTH(4)) u_fifo ;
53 
   u_fifo_t    u_fifo ;
54 
   wire [ADDR_WIDTH-1:0] r_c1 ;
55 
   reg                   f_fr ;
56 
   wire                  pop    = fifo_pop.pop ;
57 
   wire                  push   = fifo_push.push ;
58 
   wire [DATA_WIDTH-1:0] push_dat = fifo_push.push_dat ;
59 
   logic  almost_full ;
60 
 
61 
   assign fifo_push.empty = (u_fifo.write_pointer == u_fifo.read_pointer) & ~f_fr ;
62 
   assign fifo_push.full  = (u_fifo.write_pointer == u_fifo.read_pointer) &  f_fr ;
63 
 
64 
   assign fifo_pop.empty = (u_fifo.write_pointer == u_fifo.read_pointer) & ~f_fr ;
65 
   assign fifo_pop.full  = (u_fifo.write_pointer == u_fifo.read_pointer) &  f_fr ;
66 
   assign fifo_push.almost_full = almost_full ;
67 
 
68 
   always_comb begin
69 
      case (almost_empty_level)
70 
        2'b00   : begin
71 
           almost_full = f_fr == 1'b1
72 
                                ? (u_fifo.write_pointer - u_fifo.read_pointer) == LEVEL_1
73 
                                : (u_fifo.write_pointer + u_fifo.read_pointer) == LEVEL_1 ;
74 
        end
75 
        2'b01   : begin
76 
           almost_full = f_fr == 1'b1
77 
                                ? (u_fifo.write_pointer - u_fifo.read_pointer) == LEVEL_2
78 
                                : (u_fifo.write_pointer + u_fifo.read_pointer) == LEVEL_2 ;
79 
        end
80 
        2'b10   : begin
81 
           almost_full = f_fr == 1'b1
82 
                                ? (u_fifo.write_pointer - u_fifo.read_pointer) == LEVEL_3
83 
                                : (u_fifo.write_pointer + u_fifo.read_pointer) == LEVEL_3 ;
84 
        end
85 
        2'b11   : begin
86 
           almost_full = f_fr == 1'b1
87 
                                ? (u_fifo.write_pointer - u_fifo.read_pointer) == LEVEL_4
88 
                                : (u_fifo.write_pointer + u_fifo.read_pointer) == LEVEL_4 ;
89 
        end
90 
      endcase // case (almost_empty_level)
91 
   end // always_comb begin
92 
 
93 
   assign #100 fifo_pop.pop_dat   =  u_fifo.mem[u_fifo.read_pointer] ;
94 
   assign  all_error = u_fifo.err[0] |
95 
                       u_fifo.err[1] |
96 
                       u_fifo.err[2] |
97 
                       u_fifo.err[3] |
98 
                       u_fifo.err[4] |
99 
                       u_fifo.err[5] |
100 
                       u_fifo.err[6] |
101 
                       u_fifo.err[7] |
102 
                       u_fifo.err[8] |
103 
                       u_fifo.err[9] |
104 
                       u_fifo.err[10] |
105 
                       u_fifo.err[11] |
106 
                       u_fifo.err[12] |
107 
                       u_fifo.err[13] |
108 
                       u_fifo.err[14] |
109 
                       u_fifo.err[15] ;
110 
 
111 
 
112 
 
113 
   always @(posedge clk_i, negedge nrst_i) begin
114 
      if(nrst_i == 1'b0) begin
115 
         u_fifo.err[0] <= #1 1'b0 ;
116 
         u_fifo.err[1] <= #1 1'b0 ;
117 
         u_fifo.err[2] <= #1 1'b0 ;
118 
         u_fifo.err[3] <= #1 1'b0 ;
119 
         u_fifo.err[4] <= #1 1'b0 ;
120 
         u_fifo.err[5] <= #1 1'b0 ;
121 
         u_fifo.err[6] <= #1 1'b0 ;
122 
         u_fifo.err[7] <= #1 1'b0 ;
123 
         u_fifo.err[8] <= #1 1'b0 ;
124 
         u_fifo.err[9] <= #1 1'b0 ;
125 
         u_fifo.err[10] <= #1 1'b0 ;
126 
         u_fifo.err[11] <= #1 1'b0 ;
127 
         u_fifo.err[12] <= #1 1'b0 ;
128 
         u_fifo.err[13] <= #1 1'b0 ;
129 
         u_fifo.err[14] <= #1 1'b0 ;
130 
         u_fifo.err[15] <= #1 1'b0 ;
131 
         u_fifo.mem[4'h0] <= #1 11'h000 ; // initial addr:'h0->data::'h0
132 
      end
133 
      else
134 
        case ({push, pop})
135 
          2'b01 : u_fifo.err[u_fifo.read_pointer] <= #1 1'b0 ;
136 
          2'b10 : begin
137 
             u_fifo.mem[u_fifo.write_pointer] <= #1 push_dat[10:0] ;
138 
             u_fifo.err[u_fifo.write_pointer] <= #1 |(push_dat[10:8]) ;
139 
          end
140 
          2'b11 : begin
141 
             u_fifo.mem[u_fifo.write_pointer] <= #1 push_dat[10:0] ;
142 
             u_fifo.err[u_fifo.write_pointer] <= #1 |(push_dat[10:8]) ;
143 
             u_fifo.err[u_fifo.read_pointer]  <= #1 1'b0 ;
144 
          end
145 
          default : u_fifo.err <= #1 u_fifo.err ;
146 
        endcase // case ({push, pop})
147 
   end // always @ (posedge clk_i, negedge nrst_i)
148 
 
149 
   assign r_c1 = u_fifo.read_pointer - 'h01 ;
150 
 
151 
   always @(posedge clk_i, negedge nrst_i) begin
152 
      if(nrst_i == 1'b0)
153 
        f_fr <= #1 1'b0 ;
154 
      else if(r_c1 == u_fifo.write_pointer)
155 
        f_fr <= #1 1'b1 ;
156 
      else if(pop == 1'b1 || clear == 1'b1)
157 
        f_fr <= #1 1'b0 ;
158 
      else
159 
        f_fr <= #1 f_fr ;
160 
   end
161 
 
162 
   always @(posedge clk_i, negedge nrst_i) begin
163 
      if(nrst_i == 1'b0)
164 
        u_fifo.write_pointer <= #1 'h00 ;
165 
      else if(clear == 1'b1)
166 
        u_fifo.write_pointer <= #1 'h00 ;
167 
      else if(push == 1'b1)
168 
        u_fifo.write_pointer <= #1 u_fifo.write_pointer + 'h01 ;
169 
      else
170 
        u_fifo.write_pointer <= #1 u_fifo.write_pointer ;
171 
   end
172 
 
173 
   // -- read pinter inc & clear to current error bit --
174 
   always @(posedge clk_i, negedge nrst_i) begin
175 
      if(nrst_i == 1'b0)
176 
        u_fifo.read_pointer <= #1 'h00 ;
177 
      else if(clear == 1'b1)
178 
        u_fifo.read_pointer <= #1 'h00 ;
179 
      else if(pop == 1'b1)
180 
        u_fifo.read_pointer <= #1 u_fifo.read_pointer + 'h01 ;
181 
      else
182 
        u_fifo.read_pointer <= #1 u_fifo.read_pointer ;
183 
   end
184 
 
185 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.