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hiroshi |
/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_interface.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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// --- uart16550 interface signale ---
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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interface uart_bus ;
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wire stx_o ;
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wire srx_i ;
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wire rts_o ;
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wire cts_i ;
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wire dtr_o ;
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wire dsr_i ;
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wire ri_i ;
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wire dcd_i ;
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endinterface : uart_bus
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interface wb_bus() ;
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wire clk_i ; // clock
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wire nrst_i ; // reset
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wire [31:0] adr_i ; // address
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wire [31:0] dat_i ; // data input
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wire [31:0] dat_o ; // data output
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wire we_i ; // write enable
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wire [3:0] sel_i ; // select
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wire stb_i ; // strobe signal
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wire ack_o ; // acknowledge
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wire cyc_i ; // cycle assrted
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wire intr_o ; // interrupt output
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modport master_mp(
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output clk_i, nrst_i, adr_i, dat_i, we_i, sel_i, cyc_i, stb_i,
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input dat_o, ack_o, intr_o
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) ;
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modport slave_mp(
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input clk_i, nrst_i, adr_i, dat_i, we_i, sel_i, stb_i, cyc_i,
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output dat_o, ack_o, intr_o) ;
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endinterface : wb_bus
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