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hiroshi |
/* *****************************************************************************
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* title: uart_16550_rll module *
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* description: RS232 Protocol 16550D uart (mostly supported) *
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* languages: systemVerilog *
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* *
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* Copyright (C) 2010 miyagi.hiroshi *
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* *
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* This library is free software; you can redistribute it and/or *
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* modify it under the terms of the GNU Lesser General Public *
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* License as published by the Free Software Foundation; either *
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* version 2.1 of the License, or (at your option) any later version. *
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* *
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* This library is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* Lesser General Public License for more details. *
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* *
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* You should have received a copy of the GNU Lesser General Public *
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* License along with this library; if not, write to the Free Software *
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111*1307 USA *
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* *
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* *** GNU LESSER GENERAL PUBLIC LICENSE *** *
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* from http://www.gnu.org/licenses/lgpl.txt *
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*****************************************************************************
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* redleaflogic,ltd *
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* miyagi.hiroshi@redleaflogic.biz *
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* $Id: uart_package.sv 108 2010-03-30 02:56:26Z hiroshi $ *
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***************************************************************************** */
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package uart_package ;
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`ifdef SYN
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/* empty */
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`else
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timeunit 1ps ;
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timeprecision 1ps ;
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`endif
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localparam UART_RXD = 'h0 ;
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localparam UART_TXD = 'h0 ;
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localparam UART_INTERRUPT_ENABLE = 'h1 ;
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localparam UART_INTERRUPT_IDENT = 'h2 ;
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localparam UART_FIFO_CONTROL = 'h2 ;
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localparam UART_LINE_CONTROL = 'h3 ;
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localparam UART_MODEM_CONTROL = 'h4 ;
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localparam UART_LINE_STATUS = 'h5 ;
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localparam UART_MODEM_STATUS = 'h6 ;
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localparam UART_SCRATCH = 'h7 ;
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localparam UART_BAUD = 'h0 ;
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typedef enum logic [3:0] {
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IDLE,
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TIMEOUT,
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STOP,
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START,
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SEL_0,
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SEL_1,
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SEL_2,
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SEL_3,
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SEL_4,
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SEL_5,
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SEL_6,
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DATA_END,
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PARITY
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} codec_state_t ;
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// -- read for manual - 4.5 Line Control Register (LCR) --
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typedef enum logic [1:0] {
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CHAR_8_BIT = 2'b11,
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CHAR_7_BIT = 2'b10,
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CHAR_6_BIT = 2'b01,
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CHAR_5_BIT = 2'b00
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} char_length_t ;
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// -- read for manual - 4.3 Interrupt Identification Register (IIR) --
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typedef enum logic [3:0] {
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REC_LINE_STATUS = 4'b0110,
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REC_DATA_AVAILABLE = 4'b0100,
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TIME_OUT = 4'b1100,
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TRANS_REG_EMPTY = 4'b0010,
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MODEM_STATUS = 4'b0000,
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NO_INTERRUPT = 4'b0001 // -- bit 0 -> "1" no interrupt pending
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} interrupt_identification_t ;
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typedef struct packed {
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logic [3:0] ignored_74_bit ;
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logic modem_status ;
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logic rec_line_status ;
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logic trans_holding_reg_empty ;
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logic rec_data_available ;
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} interrupt_enable_reg_t ;
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typedef struct packed {
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logic [3:0] ignored_74_value_hC ;
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interrupt_identification_t interrupt_identification ;
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} interrupt_identification_reg_t ;
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typedef struct packed {
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logic modem_status ;
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logic transmitter_holding_register_empty ;
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logic timeout_indication ;
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logic receiver_data_available ;
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logic receiver_line_status ;
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} interrupt_pending_reg_t ;
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// -- read for manual - 4.4 FIFO Control Register (FCR) --
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typedef enum logic [1:0] {
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BYTE_1 = 2'b00,
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BYTE_4 = 2'b01,
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BYTE_8 = 2'b10,
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BYTE_14 = 2'b11
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} define_fifo_trigger_level_t ;
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typedef struct packed {
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define_fifo_trigger_level_t define_fifo_trigger_level ;
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logic [2:0] ignored_53_bit ;
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logic transmitter_fifo_reset ;
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logic receiver_fifo_reset ;
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logic ignored_0_bit ;
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} fifo_control_reg_t ;
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typedef struct packed {
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logic divisor_access ;
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logic break_control_bit ;
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logic stick_parity ;
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logic even_parity ;
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logic parity_enable ;
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logic stop_bit_count ;
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char_length_t char_length ;
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} line_control_reg_t ;
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typedef struct packed {
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logic [2:0] ignored_75_bit ;
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logic loopback ;
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logic out2 ;
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logic out1 ;
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logic rts ;
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logic dtr ;
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} modem_control_reg_t ;
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typedef struct packed {
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logic all_error ;
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logic trans_empty ;
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logic trans_fifo_empty ;
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logic break_intr ;
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logic framing_err ;
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logic parity_err ;
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logic overrun_err ;
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logic data_ready ;
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} line_status_reg_t ;
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typedef struct packed {
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logic dcd ;
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logic ri ;
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logic dsr ;
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logic cts ;
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logic dcd_indicator ;
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logic ri_indicator ;
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logic dsr_indicator ;
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logic cts_indicator ;
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} modem_status_reg_t ;
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typedef struct packed{
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interrupt_enable_reg_t interrupt_enable_reg ;
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interrupt_identification_reg_t interrupt_ident_reg ;
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fifo_control_reg_t fifo_control_reg ;
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modem_control_reg_t modem_control_reg ;
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line_control_reg_t line_control_reg ;
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line_status_reg_t line_status_reg ;
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modem_status_reg_t modem_status_reg ;
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interrupt_pending_reg_t interrupt_pending_reg ;
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logic [7:0] scratch_reg ;
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logic [7:0] baud_reg ;
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} u_reg_t ;
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typedef struct packed{
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logic [7:0] data_r ;
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logic start ;
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logic line ;
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logic framing_err ;
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logic parity_err ;
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logic break_err ;
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codec_state_t state ;
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} u_codec_t ;
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endpackage : uart_package
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