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[/] [t400/] [trunk/] [bench/] [vhdl/] [tb_microbus.vhd] - Blame information for rev 179

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1 117 arniml
-------------------------------------------------------------------------------
2
--
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-- Testbench for MICROBUS evaluation.
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--
5 179 arniml
-- $Id: tb_microbus.vhd 179 2009-04-01 19:48:38Z arniml $
6 117 arniml
--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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--      http://www.opencores.org/cvsweb.shtml/t400/
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--
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-------------------------------------------------------------------------------
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entity tb_microbus is
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end tb_microbus;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.t400_system_comp_pack.t420;
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use work.tb_pack.all;
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use work.t400_opt_pack.all;
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architecture behav of tb_microbus is
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  -- 5 MHz clock
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  constant period_c : time := 200 ns;
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  signal   ck_s     : std_logic;
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  signal   en_ck_s  : std_logic := '0';
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  signal reset_n_s  : std_logic;
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  signal io_l_s     : std_logic_vector(7 downto 0);
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  signal io_d_s     : std_logic_vector(3 downto 0);
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  signal io_g_s     : std_logic_vector(3 downto 0);
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  signal io_in_s    : std_logic_vector(3 downto 0);
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  signal si_s,
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         so_s,
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         sk_s       : std_logic;
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  signal cs_n_s,
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         rd_n_s,
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         wr_n_s     : std_logic;
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  signal tb_io_l_s  : std_logic_vector(7 downto 0);
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begin
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  reset_n_s <= '1';
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  -----------------------------------------------------------------------------
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  -- DUT
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  -----------------------------------------------------------------------------
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  t420_b : t420
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    generic map (
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      opt_ck_div_g   => t400_opt_ck_div_4_c,
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      opt_microbus_g => t400_opt_microbus_c
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    )
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    port map (
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      ck_i      => ck_s,
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      ck_en_i   => en_ck_s,
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      reset_n_i => reset_n_s,
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      cko_i     => io_in_s(2),
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      si_i      => si_s,
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      so_o      => so_s,
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      sk_o      => sk_s,
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      io_l_b    => io_l_s,
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      io_d_o    => io_d_s,
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      io_g_b    => io_g_s,
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      io_in_i   => io_in_s
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    );
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  io_l_s  <= (others => 'H');
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  io_d_s  <= (others => 'H');
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  io_g_s  <= (others => 'H');
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  io_in_s <= (others => 'H');
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  -----------------------------------------------------------------------------
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  -- Testbench elements
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  -----------------------------------------------------------------------------
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  tb_elems_b : tb_elems
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    generic map (
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      period_g  => period_c,
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      d_width_g => 4,
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      g_width_g => 4
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    )
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    port map (
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      io_l_i  => tb_io_l_s,
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      io_d_i  => io_d_s,
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      io_g_i  => io_g_s,
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      io_in_o => open,
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      so_i    => so_s,
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      si_o    => si_s,
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      sk_i    => sk_s,
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      ck_o    => ck_s
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    );
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  -----------------------------------------------------------------------------
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  -- Process ck_div
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  --
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  -- Purpose:
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  --   Generates the en_ck_s signal from the high frequency clock.
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  --
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  ck_div: process (ck_s)
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    variable cnt_v : natural := 0;
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  begin
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    if ck_s'event and ck_s = '1' then
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      en_ck_s <= '0';
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      if cnt_v = 25 then
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        cnt_v := 0;
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        en_ck_s <= '1';
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      else
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        cnt_v := cnt_v + 1;
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      end if;
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    end if;
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  end process ck_div;
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  --
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  -----------------------------------------------------------------------------
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  -----------------------------------------------------------------------------
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  -- Process microbus
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  --
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  -- Purpose:
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  --   Implements the microbus testbench element.
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  --   a) sends twelve bytes of data to the DUT
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  --        HELLO WORLD!
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  --   b) reads twelve bytes from the DUT and compares them against
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  --      the original sequence
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  --
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  microbus: process
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    procedure tb_pass_fail(pass : in boolean) is
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    begin
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      tb_io_l_s <= "00000000";
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      wait for 1 us;
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      tb_io_l_s <= "10100000";
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      wait for 1 us;
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      tb_io_l_s <= "01010000";
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      wait for 1 us;
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      if pass then
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        tb_io_l_s <= "00000000";
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      else
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        tb_io_l_s <= "11110000";
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      end if;
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      wait for 1 us;
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    end;
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    constant msg_c : string := string'("HELLO WORLD!");
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  begin
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    -- default settings
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    cs_n_s    <= '1';
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    rd_n_s    <= '1';
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    wr_n_s    <= '1';
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    io_l_s    <= (others => 'H');
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    tb_io_l_s <= (others => '0');
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    --
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    -- send the message string
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    --
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    for idx in msg_c'range loop
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      wait until io_g_s(0)'event and io_g_s(0) = '1';
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      if idx mod 2 = 0 then
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        -- short wait for even positions
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        wait for 1 us;
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      else
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        -- long wait for odd positions
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        wait for 1 ms;
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      end if;
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      io_l_s <= std_logic_vector(to_unsigned(character'pos(msg_c(idx)), 8));
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      wait for 10 ns;
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      cs_n_s <= '0';
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      wr_n_s <= '0';
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      wait for 400 ns;
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      cs_n_s <= '1';
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      wr_n_s <= '1';
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      wait for 10 ns;
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      io_l_s <= (others => 'H');
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    end loop;
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    --
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    -- and receive it again
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    --
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    for idx in msg_c'range loop
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      wait until io_g_s(0)'event and io_g_s(0) = '1';
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      if idx mod 2 = 0 then
228
        -- short wait for even positions
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        wait for 1 us;
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      else
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        -- long wait for odd positions
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        wait for 1 ms;
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      end if;
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      cs_n_s <= '0';
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      rd_n_s <= '0';
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      wait for 400 ns;
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      if character'pos(msg_c(idx)) /= to_integer(unsigned(io_l_s)) then
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        tb_pass_fail(pass => false);
240
      end if;
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      cs_n_s <= '1';
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      rd_n_s <= '1';
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      -- ack with dummy write
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      wait for 1 us;
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      cs_n_s <= '0';
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      wr_n_s <= '0';
248
      wait for 400 ns;
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      cs_n_s <= '1';
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      wr_n_s <= '1';
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    end loop;
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    tb_pass_fail(pass => true);
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    wait;
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  end process microbus;
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  --
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  io_in_s(1) <= rd_n_s;
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  io_in_s(2) <= cs_n_s;
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  io_in_s(3) <= wr_n_s;
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  --
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  -----------------------------------------------------------------------------
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end behav;

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