OpenCores
URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [sw/] [verif/] [black_box/] [ldd/] [test.asm] - Blame information for rev 179

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 40 arniml
        ;; *******************************************************************
2 179 arniml
        ;; $Id: test.asm 179 2009-04-01 19:48:38Z arniml $
3 40 arniml
        ;;
4
        ;; Checks the LDD instruction.
5
        ;;
6
 
7
        ;; the cpu type is defined on asl's command line
8
 
9
        ;; macro for checking a digit
10
check_d MACRO   reg, digit
11
        lbi     (reg ! 3), ~digit & 0xf	; select inverse digit
12
        ldd     reg, digit
13
        lbi     reg, digit
14
        ske
15
        jmp     fail
16
        ENDM
17
 
18
 
19
        ;; macro for checking LDD on a complete register
20
check_r MACRO   reg
21
        check_d reg, 0
22
        check_d reg, 1
23
        check_d reg, 2
24
        check_d reg, 3
25
        check_d reg, 4
26
        check_d reg, 5
27
        check_d reg, 6
28
        check_d reg, 7
29
        check_d reg, 8
30
        check_d reg, 9
31
        check_d reg, 10
32
        check_d reg, 11
33
        check_d reg, 12
34
        check_d reg, 13
35
        check_d reg, 14
36
        check_d reg, 15
37
        ENDM
38
 
39
 
40
        org     0x00
41
        clra
42
 
43
 
44
        ;; prepare other registers
45
        ;; register 1
46
        lbi     1, 0
47
        jsr     clear_reg
48
        ;; register 2
49
        lbi     2, 0
50
        jsr     clear_reg
51
        ;; register 3
52
        lbi     3, 0
53
        jsr     clear_reg
54
 
55
 
56
        ;; *******************************************************************
57
        ;; Test LDD on register 0
58
        ;;
59
        lbi     0, 0
60
        jsr     init_reg
61
        ;;
62
        check_r 0
63
 
64
 
65
        ;; *******************************************************************
66
        ;; Test LDD on register 1
67
        ;;
68
        lbi     0, 0
69
        jsr     clear_reg
70
        lbi     1, 0
71
        jsr     init_reg
72
        ;;
73
        check_r 1
74
 
75
 
76
        ;; *******************************************************************
77
        ;; Test LDD on register 2
78
        ;;
79
        lbi     1, 0
80
        jsr     clear_reg
81
        lbi     2, 0
82
        jsr     init_reg
83
        ;;
84
        check_r 2
85
 
86
        ;; *******************************************************************
87
        ;; Test LDD on register 3
88
        ;;
89
        lbi     2, 0
90
        jsr     clear_reg
91
        lbi     3, 0
92
        jsr     init_reg
93
        ;;
94
        check_r 3
95
 
96
 
97
        jmp     pass
98
 
99
 
100
 
101
        ;; initialize current register with proper values
102
        ;;
103
init_reg:
104
        clra
105
        cab
106
        stii    0x0
107
        stii    0x1
108
        stii    0x2
109
        stii    0x3
110
        stii    0x4
111
        stii    0x5
112
        stii    0x6
113
        stii    0x7
114
        stii    0x8
115
        stii    0x9
116
        stii    0xa
117
        stii    0xb
118
        stii    0xc
119
        stii    0xd
120
        stii    0xe
121
        stii    0xf
122
        ret
123
 
124
        ;;
125
        ;; clear current register
126
        ;;
127
clear_reg:
128
        clra
129
        cab
130
        stii    0x0
131
        stii    0x0
132
        stii    0x0
133
        stii    0x0
134
        stii    0x0
135
        stii    0x0
136
        stii    0x0
137
        stii    0x0
138
        stii    0x0
139
        stii    0x0
140
        stii    0x0
141
        stii    0x0
142
        stii    0x0
143
        stii    0x0
144
        stii    0x0
145
        stii    0x0
146
        ret
147
 
148
        org     0x380
149
        include "pass_fail.asm"

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.