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Subversion Repositories tcp_ip_core_w_dhcp

[/] [tcp_ip_core_w_dhcp/] [trunk/] [TB_spi_mod.vhd] - Blame information for rev 2

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--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   21:47:27 12/04/2014
-- Design Name:   
-- Module Name:   /home/craig/Documents/CW/Git_Repos/hw_client/TB_spi_mod.vhd
-- Project Name:  hw_client
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: spi_mod
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY TB_spi_mod IS
END TB_spi_mod;
 
ARCHITECTURE behavior OF TB_spi_mod IS
 
    COMPONENT spi_mod
    PORT(
         CLK_IN                                                 : IN  std_logic;
         RST_IN                                                 : IN  std_logic;
         WR_CONTINUOUS_IN                       : IN  std_logic;
         WE_IN                                          : IN  std_logic;
         WR_ADDR_IN                                     : IN  std_logic_vector(7 downto 0);
         WR_DATA_IN                                     : IN  std_logic_vector(7 downto 0);
         WR_DATA_CMPLT_OUT              : OUT std_logic;
                        RD_CONTINUOUS_IN                        : IN  std_logic;
         RD_IN                                          : IN  std_logic;
         RD_WIDTH_IN                            : IN  std_logic;
         RD_ADDR_IN                                     : IN  std_logic_vector(7 downto 0);
         RD_DATA_OUT                            : OUT std_logic_vector(7 downto 0);
                        RD_DATA_CMPLT_OUT                       : out STD_LOGIC;
                        SLOW_CS_EN_IN                           : in STD_LOGIC;
                        OPER_CMPLT_POST_CS_OUT  : out STD_LOGIC;
         SDI_OUT                                                : OUT std_logic;
         SDO_IN                                                 : IN  std_logic;
         SCLK_OUT                                       : OUT std_logic;
         CS_OUT                                                 : OUT std_logic);
    END COMPONENT;
 
 
   --Inputs
   signal CLK_IN : std_logic := '0';
   signal RST_IN : std_logic := '0';
   signal WR_CONTINUOUS_IN : std_logic := '0';
   signal RD_CONTINUOUS_IN : std_logic := '0';
   signal WE_IN : std_logic := '0';
   signal WR_ADDR_IN : std_logic_vector(7 downto 0) := (others => '0');
   signal WR_DATA_IN : std_logic_vector(7 downto 0) := (others => '0');
   signal RD_IN, OPER_CMPLT_POST_CS_OUT : std_logic := '0';
   signal RD_WIDTH_IN : std_logic := '0';
   signal RD_ADDR_IN : std_logic_vector(7 downto 0) := (others => '0');
   signal SDO : std_logic := '0';
 
        --Outputs
   signal WR_DATA_CMPLT_OUT, SLOW_CS_EN_IN : std_logic;
   signal RD_DATA_OUT : std_logic_vector(7 downto 0);
   signal SDI, RD_DATA_CMPLT_OUT : std_logic;
   signal SCLK : std_logic;
   signal CS : std_logic;
 
   -- Clock period definitions
   constant CLK_IN_period : time := 9 ns;
 
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
   uut: spi_mod PORT MAP (
          CLK_IN => CLK_IN,
          RST_IN => RST_IN,
          WR_CONTINUOUS_IN => WR_CONTINUOUS_IN,
          WE_IN => WE_IN,
          WR_ADDR_IN => WR_ADDR_IN,
          WR_DATA_IN => WR_DATA_IN,
          WR_DATA_CMPLT_OUT => WR_DATA_CMPLT_OUT,
                         RD_CONTINUOUS_IN => RD_CONTINUOUS_IN,
          RD_IN => RD_IN,
          RD_WIDTH_IN => RD_WIDTH_IN,
          RD_ADDR_IN => RD_ADDR_IN,
          RD_DATA_OUT => RD_DATA_OUT,
                         RD_DATA_CMPLT_OUT => RD_DATA_CMPLT_OUT,
                         SLOW_CS_EN_IN => SLOW_CS_EN_IN,
                         OPER_CMPLT_POST_CS_OUT => OPER_CMPLT_POST_CS_OUT,
          SDI_OUT => SDI,
          SDO_IN => SDO,
          SCLK_OUT => SCLK,
          CS_OUT => CS
        );
 
   -- Clock process definitions
   CLK_IN_process :process
   begin
                CLK_IN <= '0';
                wait for CLK_IN_period/2;
                CLK_IN <= '1';
                wait for CLK_IN_period/2;
   end process;
 
   -- Stimulus process
   stim_proc: process
   begin
      wait for CLK_IN_period*10;
 
                SLOW_CS_EN_IN <= '1';
 
                WE_IN <= '0';
                wait for CLK_IN_period;
                WR_DATA_IN <= X"AE";
                WR_ADDR_IN <= X"45";
                WE_IN <= '1';
                wait for CLK_IN_period;
                WE_IN <= '0';
 
                wait for 30 us;
 
                WE_IN <= '0';
                wait for CLK_IN_period;
                WR_DATA_IN <= X"F2";
                WR_ADDR_IN <= X"9B";
                WE_IN <= '1';
                WR_CONTINUOUS_IN <= '1';
                wait for CLK_IN_period;
                WE_IN <= '0';
 
                wait for 1310 ns;
                WR_DATA_IN <= X"2B";
 
                wait for 640 ns;
                WR_DATA_IN <= X"E7";
 
                wait for 640 ns;
                WR_DATA_IN <= X"A1";
 
                wait for 640 ns;
                WR_DATA_IN <= X"43";
 
                wait for 50 us;
                WR_CONTINUOUS_IN <= '0';
 
                wait for 30 us;
                SLOW_CS_EN_IN <= '0';
 
                RD_IN <= '0';
                wait for CLK_IN_period;
                RD_ADDR_IN <= X"26";
                RD_IN <= '1';
                wait for CLK_IN_period;
                RD_IN <= '0';
 
                wait for 670 ns;
 
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
 
                wait for 30 us;
 
                RD_IN <= '0';
                wait for CLK_IN_period;
                RD_ADDR_IN <= X"62";
                RD_IN <= '1';
                RD_WIDTH_IN <= '0';
                wait for CLK_IN_period;
                RD_IN <= '0';
                RD_WIDTH_IN <= '1';
 
                wait for 670 ns;
 
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
 
                wait for 30 us;
 
                RD_IN <= '0';
                wait for CLK_IN_period;
                RD_CONTINUOUS_IN <= '1';
                RD_ADDR_IN <= X"62";
                RD_IN <= '1';
                RD_WIDTH_IN <= '0';
                wait for CLK_IN_period;
                RD_IN <= '0';
 
                wait for 820 ns;
 
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
 
                wait for 820 ns;
 
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
 
                wait for 820 ns;
 
                SDO <= '1';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '0';
                wait for 80 ns;
                SDO <= '1';
                wait for 80 ns;
 
                wait for 20 us;
                RD_CONTINUOUS_IN <= '0';
 
                wait for 30 us;
                SLOW_CS_EN_IN <= '0';
 
                RD_IN <= '0';
                wait for CLK_IN_period;
                RD_ADDR_IN <= X"26";
                RD_IN <= '1';
                wait for CLK_IN_period;
                RD_IN <= '0';
 
      wait;
   end process;
 
END;

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Subversion Repositories tcp_ip_core_w_dhcp

[/] [tcp_ip_core_w_dhcp/] [trunk/] [TB_spi_mod.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	craighaywo	`--------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 21:47:27 12/04/2014`
6			`-- Design Name:`
7			`-- Module Name: /home/craig/Documents/CW/Git_Repos/hw_client/TB_spi_mod.vhd`
8			`-- Project Name: hw_client`
9			`-- Target Device:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- VHDL Test Bench Created by ISE for module: spi_mod`
14			`--`
15			`-- Dependencies:`
16			`--`
17			`-- Revision:`
18			`-- Revision 0.01 - File Created`
19			`-- Additional Comments:`
20			`--`
21			`-- Notes:`
22			`-- This testbench has been automatically generated using types std_logic and`
23			`-- std_logic_vector for the ports of the unit under test. Xilinx recommends`
24			`-- that these types always be used for the top-level I/O of a design in order`
25			`-- to guarantee that the testbench will bind correctly to the post-implementation`
26			`-- simulation model.`
27			`--------------------------------------------------------------------------------`
28			`LIBRARY ieee;`
29			`USE ieee.std_logic_1164.ALL;`
30
31			`-- Uncomment the following library declaration if using`
32			`-- arithmetic functions with Signed or Unsigned values`
33			`--USE ieee.numeric_std.ALL;`
34
35			`ENTITY TB_spi_mod IS`
36			`END TB_spi_mod;`
37
38			`ARCHITECTURE behavior OF TB_spi_mod IS`
39
40			`COMPONENT spi_mod`
41			`PORT(`
42			`CLK_IN : IN std_logic;`
43			`RST_IN : IN std_logic;`
44			`WR_CONTINUOUS_IN : IN std_logic;`
45			`WE_IN : IN std_logic;`
46			`WR_ADDR_IN : IN std_logic_vector(7 downto 0);`
47			`WR_DATA_IN : IN std_logic_vector(7 downto 0);`
48			`WR_DATA_CMPLT_OUT : OUT std_logic;`
49			`RD_CONTINUOUS_IN : IN std_logic;`
50			`RD_IN : IN std_logic;`
51			`RD_WIDTH_IN : IN std_logic;`
52			`RD_ADDR_IN : IN std_logic_vector(7 downto 0);`
53			`RD_DATA_OUT : OUT std_logic_vector(7 downto 0);`
54			`RD_DATA_CMPLT_OUT : out STD_LOGIC;`
55			`SLOW_CS_EN_IN : in STD_LOGIC;`
56			`OPER_CMPLT_POST_CS_OUT : out STD_LOGIC;`
57			`SDI_OUT : OUT std_logic;`
58			`SDO_IN : IN std_logic;`
59			`SCLK_OUT : OUT std_logic;`
60			`CS_OUT : OUT std_logic);`
61			`END COMPONENT;`
62
63
64			`--Inputs`
65			`signal CLK_IN : std_logic := '0';`
66			`signal RST_IN : std_logic := '0';`
67			`signal WR_CONTINUOUS_IN : std_logic := '0';`
68			`signal RD_CONTINUOUS_IN : std_logic := '0';`
69			`signal WE_IN : std_logic := '0';`
70			`signal WR_ADDR_IN : std_logic_vector(7 downto 0) := (others => '0');`
71			`signal WR_DATA_IN : std_logic_vector(7 downto 0) := (others => '0');`
72			`signal RD_IN, OPER_CMPLT_POST_CS_OUT : std_logic := '0';`
73			`signal RD_WIDTH_IN : std_logic := '0';`
74			`signal RD_ADDR_IN : std_logic_vector(7 downto 0) := (others => '0');`
75			`signal SDO : std_logic := '0';`
76
77			`--Outputs`
78			`signal WR_DATA_CMPLT_OUT, SLOW_CS_EN_IN : std_logic;`
79			`signal RD_DATA_OUT : std_logic_vector(7 downto 0);`
80			`signal SDI, RD_DATA_CMPLT_OUT : std_logic;`
81			`signal SCLK : std_logic;`
82			`signal CS : std_logic;`
83
84			`-- Clock period definitions`
85			`constant CLK_IN_period : time := 9 ns;`
86
87			`BEGIN`
88
89			`-- Instantiate the Unit Under Test (UUT)`
90			`uut: spi_mod PORT MAP (`
91			`CLK_IN => CLK_IN,`
92			`RST_IN => RST_IN,`
93			`WR_CONTINUOUS_IN => WR_CONTINUOUS_IN,`
94			`WE_IN => WE_IN,`
95			`WR_ADDR_IN => WR_ADDR_IN,`
96			`WR_DATA_IN => WR_DATA_IN,`
97			`WR_DATA_CMPLT_OUT => WR_DATA_CMPLT_OUT,`
98			`RD_CONTINUOUS_IN => RD_CONTINUOUS_IN,`
99			`RD_IN => RD_IN,`
100			`RD_WIDTH_IN => RD_WIDTH_IN,`
101			`RD_ADDR_IN => RD_ADDR_IN,`
102			`RD_DATA_OUT => RD_DATA_OUT,`
103			`RD_DATA_CMPLT_OUT => RD_DATA_CMPLT_OUT,`
104			`SLOW_CS_EN_IN => SLOW_CS_EN_IN,`
105			`OPER_CMPLT_POST_CS_OUT => OPER_CMPLT_POST_CS_OUT,`
106			`SDI_OUT => SDI,`
107			`SDO_IN => SDO,`
108			`SCLK_OUT => SCLK,`
109			`CS_OUT => CS`
110			`);`
111
112			`-- Clock process definitions`
113			`CLK_IN_process :process`
114			`begin`
115			`CLK_IN <= '0';`
116			`wait for CLK_IN_period/2;`
117			`CLK_IN <= '1';`
118			`wait for CLK_IN_period/2;`
119			`end process;`
120
121			`-- Stimulus process`
122			`stim_proc: process`
123			`begin`
124			`wait for CLK_IN_period*10;`
125
126			`SLOW_CS_EN_IN <= '1';`
127
128			`WE_IN <= '0';`
129			`wait for CLK_IN_period;`
130			`WR_DATA_IN <= X"AE";`
131			`WR_ADDR_IN <= X"45";`
132			`WE_IN <= '1';`
133			`wait for CLK_IN_period;`
134			`WE_IN <= '0';`
135
136			`wait for 30 us;`
137
138			`WE_IN <= '0';`
139			`wait for CLK_IN_period;`
140			`WR_DATA_IN <= X"F2";`
141			`WR_ADDR_IN <= X"9B";`
142			`WE_IN <= '1';`
143			`WR_CONTINUOUS_IN <= '1';`
144			`wait for CLK_IN_period;`
145			`WE_IN <= '0';`
146
147			`wait for 1310 ns;`
148			`WR_DATA_IN <= X"2B";`
149
150			`wait for 640 ns;`
151			`WR_DATA_IN <= X"E7";`
152
153			`wait for 640 ns;`
154			`WR_DATA_IN <= X"A1";`
155
156			`wait for 640 ns;`
157			`WR_DATA_IN <= X"43";`
158
159			`wait for 50 us;`
160			`WR_CONTINUOUS_IN <= '0';`
161
162			`wait for 30 us;`
163			`SLOW_CS_EN_IN <= '0';`
164
165			`RD_IN <= '0';`
166			`wait for CLK_IN_period;`
167			`RD_ADDR_IN <= X"26";`
168			`RD_IN <= '1';`
169			`wait for CLK_IN_period;`
170			`RD_IN <= '0';`
171
172			`wait for 670 ns;`
173
174			`SDO <= '0';`
175			`wait for 80 ns;`
176			`SDO <= '0';`
177			`wait for 80 ns;`
178			`SDO <= '0';`
179			`wait for 80 ns;`
180			`SDO <= '0';`
181			`wait for 80 ns;`
182			`SDO <= '0';`
183			`wait for 80 ns;`
184			`SDO <= '1';`
185			`wait for 80 ns;`
186			`SDO <= '1';`
187			`wait for 80 ns;`
188			`SDO <= '0';`
189			`wait for 80 ns;`
190
191			`wait for 30 us;`
192
193			`RD_IN <= '0';`
194			`wait for CLK_IN_period;`
195			`RD_ADDR_IN <= X"62";`
196			`RD_IN <= '1';`
197			`RD_WIDTH_IN <= '0';`
198			`wait for CLK_IN_period;`
199			`RD_IN <= '0';`
200			`RD_WIDTH_IN <= '1';`
201
202			`wait for 670 ns;`
203
204			`SDO <= '0';`
205			`wait for 80 ns;`
206			`SDO <= '0';`
207			`wait for 80 ns;`
208			`SDO <= '0';`
209			`wait for 80 ns;`
210			`SDO <= '0';`
211			`wait for 80 ns;`
212			`SDO <= '1';`
213			`wait for 80 ns;`
214			`SDO <= '0';`
215			`wait for 80 ns;`
216			`SDO <= '0';`
217			`wait for 80 ns;`
218			`SDO <= '0';`
219			`wait for 80 ns;`
220			`SDO <= '1';`
221			`wait for 80 ns;`
222			`SDO <= '0';`
223			`wait for 80 ns;`
224			`SDO <= '1';`
225			`wait for 80 ns;`
226			`SDO <= '1';`
227			`wait for 80 ns;`
228			`SDO <= '0';`
229			`wait for 80 ns;`
230			`SDO <= '0';`
231			`wait for 80 ns;`
232			`SDO <= '0';`
233			`wait for 80 ns;`
234			`SDO <= '1';`
235			`wait for 80 ns;`
236			`SDO <= '0';`
237			`wait for 80 ns;`
238			`SDO <= '0';`
239			`wait for 80 ns;`
240			`SDO <= '0';`
241			`wait for 80 ns;`
242			`SDO <= '1';`
243			`wait for 80 ns;`
244			`SDO <= '0';`
245			`wait for 80 ns;`
246			`SDO <= '1';`
247			`wait for 80 ns;`
248			`SDO <= '1';`
249			`wait for 80 ns;`
250
251			`wait for 30 us;`
252
253			`RD_IN <= '0';`
254			`wait for CLK_IN_period;`
255			`RD_CONTINUOUS_IN <= '1';`
256			`RD_ADDR_IN <= X"62";`
257			`RD_IN <= '1';`
258			`RD_WIDTH_IN <= '0';`
259			`wait for CLK_IN_period;`
260			`RD_IN <= '0';`
261
262			`wait for 820 ns;`
263
264			`SDO <= '0';`
265			`wait for 80 ns;`
266			`SDO <= '0';`
267			`wait for 80 ns;`
268			`SDO <= '0';`
269			`wait for 80 ns;`
270			`SDO <= '0';`
271			`wait for 80 ns;`
272			`SDO <= '0';`
273			`wait for 80 ns;`
274			`SDO <= '1';`
275			`wait for 80 ns;`
276			`SDO <= '1';`
277			`wait for 80 ns;`
278			`SDO <= '0';`
279			`wait for 80 ns;`
280
281			`wait for 820 ns;`
282
283			`SDO <= '0';`
284			`wait for 80 ns;`
285			`SDO <= '0';`
286			`wait for 80 ns;`
287			`SDO <= '1';`
288			`wait for 80 ns;`
289			`SDO <= '1';`
290			`wait for 80 ns;`
291			`SDO <= '0';`
292			`wait for 80 ns;`
293			`SDO <= '0';`
294			`wait for 80 ns;`
295			`SDO <= '1';`
296			`wait for 80 ns;`
297			`SDO <= '0';`
298			`wait for 80 ns;`
299
300			`wait for 820 ns;`
301
302			`SDO <= '1';`
303			`wait for 80 ns;`
304			`SDO <= '1';`
305			`wait for 80 ns;`
306			`SDO <= '1';`
307			`wait for 80 ns;`
308			`SDO <= '0';`
309			`wait for 80 ns;`
310			`SDO <= '0';`
311			`wait for 80 ns;`
312			`SDO <= '0';`
313			`wait for 80 ns;`
314			`SDO <= '0';`
315			`wait for 80 ns;`
316			`SDO <= '1';`
317			`wait for 80 ns;`
318
319			`wait for 20 us;`
320			`RD_CONTINUOUS_IN <= '0';`
321
322			`wait for 30 us;`
323			`SLOW_CS_EN_IN <= '0';`
324
325			`RD_IN <= '0';`
326			`wait for CLK_IN_period;`
327			`RD_ADDR_IN <= X"26";`
328			`RD_IN <= '1';`
329			`wait for CLK_IN_period;`
330			`RD_IN <= '0';`
331
332			`wait;`
333			`end process;`
334
335			`END;`