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[/] [tcp_ip_core_w_dhcp/] [trunk/] [checksum_calc.vhd] - Blame information for rev 2

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1 2 craighaywo 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    12:51:09 12/30/2014
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-- Design Name:
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-- Module Name:    checksum_calc - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity checksum_calc is
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    Port ( CLK_IN                                               : in  STD_LOGIC;
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           RST_IN                                               : in  STD_LOGIC;
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           CHECKSUM_CALC_IN                     : in  STD_LOGIC;
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           START_ADDR_IN                                : in  STD_LOGIC_VECTOR (10 downto 0);
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           COUNT_IN                                             : in  STD_LOGIC_VECTOR (10 downto 0);
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           VALUE_IN                                             : in  STD_LOGIC_VECTOR (7 downto 0);
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           VALUE_ADDR_OUT                               : out STD_LOGIC_VECTOR (10 downto 0);
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                          CHECKSUM_INIT_IN                      : in  STD_LOGIC_VECTOR (15 downto 0);
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                          CHECKSUM_SET_INIT_IN          : in  STD_LOGIC;
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                          CHECKSUM_ODD_LENGTH_IN        : in  STD_LOGIC;
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           CHECKSUM_OUT                                 : out STD_LOGIC_VECTOR (15 downto 0);
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           CHECKSUM_DONE_OUT                    : out STD_LOGIC);
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end checksum_calc;
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architecture Behavioral of checksum_calc is
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type CC_ST is ( IDLE,
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                                                SET_INITIAL_VALUE0,
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                                                SET_INITIAL_VALUE1,
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                                                LOAD_START_ADDR,
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                                                INC_ADDR0,
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                                                INC_ADDR1,
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                                                LOAD_VALUE_LSB,
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                                                ADD_VALUE,
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                                                CHECK_COUNT,
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                                                CHECK_REMAINDER,
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                                                ADD_REMAINDER,
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                                                ONES_COMPLEMENT,
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                                                COMPLETE
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                                                );
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signal cc_state, cc_next_state : CC_ST := IDLE;
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signal rd_addr                                                          : unsigned(10 downto 0);
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signal value, checksum_reg_inv                  : unsigned(15 downto 0);
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signal checksum_reg                                                     : unsigned(31 downto 0);
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signal count                                                                    : unsigned(10 downto 0);
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signal checksum_odd                                                     : std_logic;
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begin
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        VALUE_ADDR_OUT <= std_logic_vector(rd_addr);
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        CHECKSUM_OUT <= std_logic_vector(checksum_reg_inv);
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        CHECKSUM_DONE_OUT <= '1' when cc_state = COMPLETE else '0';
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        SYNC_PROC: process(CLK_IN)
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   begin
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      if rising_edge(CLK_IN) then
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                        cc_state <= cc_next_state;
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      end if;
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   end process;
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        NEXT_STATE_DECODE: process (cc_state, CHECKSUM_CALC_IN, count, CHECKSUM_SET_INIT_IN)
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   begin
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      cc_next_state <= cc_state;  --default is to stay in current state
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      case (cc_state) is
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         when IDLE =>
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                                if CHECKSUM_CALC_IN = '1' then
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                                        cc_next_state <= LOAD_START_ADDR;
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                                elsif CHECKSUM_SET_INIT_IN = '1' then
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                                        cc_next_state <= SET_INITIAL_VALUE0;
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                                end if;
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                        when SET_INITIAL_VALUE0 =>
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                                cc_next_state <= SET_INITIAL_VALUE1;
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                        when SET_INITIAL_VALUE1 =>
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                                if CHECKSUM_CALC_IN = '1' then
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                                        cc_next_state <= LOAD_START_ADDR;
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                                end if;
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                        when LOAD_START_ADDR =>
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                                cc_next_state <= INC_ADDR0;
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                        when INC_ADDR0 =>
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                                cc_next_state <= INC_ADDR1;
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                        when INC_ADDR1 =>
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                                cc_next_state <= LOAD_VALUE_LSB;
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                        when LOAD_VALUE_LSB =>
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                                cc_next_state <= ADD_VALUE;
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                        when ADD_VALUE =>
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                                cc_next_state <= CHECK_COUNT;
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                        when CHECK_COUNT =>
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                                if count = "00000000000" then
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                                        cc_next_state <= CHECK_REMAINDER;
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                                else
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                                        cc_next_state <= INC_ADDR0;
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                                end if;
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                        when CHECK_REMAINDER =>
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                                if checksum_reg(31 downto 16) = X"0000" then
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                                        cc_next_state <= ONES_COMPLEMENT;
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                                else
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                                        cc_next_state <= ADD_REMAINDER;
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                                end if;
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                        when ADD_REMAINDER =>
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                                cc_next_state <= CHECK_REMAINDER;
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                        when ONES_COMPLEMENT =>
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                                cc_next_state <= COMPLETE;
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                        when COMPLETE =>
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                                cc_next_state <= IDLE;
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                end case;
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        end process;
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        RD_ADDR_PROC: process(CLK_IN)
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   begin
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      if rising_edge(CLK_IN) then
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                        if cc_state = LOAD_START_ADDR then
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                                rd_addr <= unsigned(START_ADDR_IN);
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                        elsif cc_state = INC_ADDR0 then
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                                rd_addr <= rd_addr + 1;
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                        elsif cc_state = INC_ADDR1 then
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                                rd_addr <= rd_addr + 1;
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                        end if;
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                        if CHECKSUM_CALC_IN = '1' then
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                                checksum_odd <= CHECKSUM_ODD_LENGTH_IN;
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                        end if;
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      end if;
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   end process;
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        LOAD_VALUE_PROC: process(CLK_IN)
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   begin
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      if rising_edge(CLK_IN) then
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                        if cc_state = INC_ADDR1 then
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                                value(15 downto 8) <= unsigned(VALUE_IN);
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                        end if;
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                        if cc_state = LOAD_VALUE_LSB then
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                                if checksum_odd = '1' and count = "00000000001" then
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                                        value(7 downto 0) <= X"00";
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                                else
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                                        value(7 downto 0) <= unsigned(VALUE_IN);
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                                end if;
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                        end if;
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      end if;
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   end process;
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        ADD_VALUE_TO_CHECKSUM: process(CLK_IN)
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        begin
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      if rising_edge(CLK_IN) then
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                        if cc_state = IDLE then
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                                checksum_reg <= (others => '0');
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                        elsif cc_state = SET_INITIAL_VALUE0 then
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                                checksum_reg(15 downto 0) <= unsigned(CHECKSUM_INIT_IN);
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                                checksum_reg(31 downto 16) <= (others => '0');
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                        elsif cc_state = ADD_VALUE then
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                                checksum_reg <= checksum_reg + unsigned(X"0000" & value);
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                        elsif cc_state = ADD_REMAINDER then
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                                checksum_reg <= unsigned(X"0000" & checksum_reg(15 downto 0)) + unsigned(X"0000" & checksum_reg(31 downto 16));
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                        end if;
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                        if cc_state = ONES_COMPLEMENT then
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                                checksum_reg_inv <= not(checksum_reg(15 downto 0));
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                        end if;
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                end if;
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        end process;
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        COUNT_PROC: process(CLK_IN)
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        begin
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      if rising_edge(CLK_IN) then
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                        if (cc_state = IDLE or cc_state = SET_INITIAL_VALUE1) and CHECKSUM_CALC_IN = '1' then
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                                count <= unsigned(COUNT_IN);
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                        elsif cc_state = ADD_VALUE then
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                                count <= count - 1;
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                        end if;
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                end if;
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        end process;
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end Behavioral;
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