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craighaywo |
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-- Creation Date: 21:12:48 05/06/2010
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-- Module Name: RS232/UART Interface - Behavioral
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-- Used TAB of 4 Spaces
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity uart is
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generic (
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CLK_FREQ : integer := 50; -- Main frequency (MHz)
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SER_FREQ : integer := 9600 -- Baud rate (bps)
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);
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port (
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-- Control
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clk : in std_logic; -- Main clock
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rst : in std_logic; -- Main reset
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-- External Interface
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rx : in std_logic; -- RS232 received serial data
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tx : out std_logic; -- RS232 transmitted serial data
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-- RS232/UART Configuration
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par_en : in std_logic; -- Parity bit enable
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-- uPC Interface
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tx_req : in std_logic; -- Request SEND of data
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tx_end : out std_logic; -- Data SENDED
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tx_data : in std_logic_vector(7 downto 0); -- Data to transmit
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rx_ready : out std_logic; -- Received data ready to uPC read
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rx_data : out std_logic_vector(7 downto 0) -- Received data
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);
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end uart;
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architecture Behavioral of uart is
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-- Constants
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constant UART_IDLE : std_logic := '1';
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constant UART_START : std_logic := '0';
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constant PARITY_EN : std_logic := '1';
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constant RST_LVL : std_logic := '1';
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-- Types
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type state is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap signals
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-- RX Signals
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signal rx_fsm : state; -- Control of reception
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signal rx_clk_en : std_logic; -- Received clock enable
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signal rx_rcv_init : std_logic; -- Start of reception
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signal rx_par_bit : std_logic; -- Calculated Parity bit
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signal rx_data_deb : std_logic; -- Debounce RX data
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signal rx_data_tmp : std_logic_vector(7 downto 0); -- Serial to parallel converter
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signal rx_data_cnt : std_logic_vector(2 downto 0); -- Count received bits
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-- TX Signals
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signal tx_fsm : state; -- Control of transmission
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signal tx_clk_en : std_logic; -- Transmited clock enable
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signal tx_par_bit : std_logic; -- Calculated Parity bit
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signal tx_data_tmp : std_logic_vector(7 downto 0); -- Parallel to serial converter
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signal tx_data_cnt : std_logic_vector(2 downto 0); -- Count transmited bits
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begin
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tx_clk_gen:process(clk)
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variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
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begin
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if clk'event and clk = '1' then
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-- Normal Operation
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if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 then
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tx_clk_en <= '1';
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counter := 0;
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else
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tx_clk_en <= '0';
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counter := counter + 1;
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end if;
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-- Reset condition
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if rst = RST_LVL then
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tx_clk_en <= '0';
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counter := 0;
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end if;
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end if;
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end process;
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tx_proc:process(clk)
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variable data_cnt : std_logic_vector(2 downto 0);
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begin
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if clk'event and clk = '1' then
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if tx_clk_en = '1' then
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-- Default values
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tx_end <= '0';
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tx <= UART_IDLE;
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-- FSM description
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case tx_fsm is
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-- Wait to transfer data
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when idle =>
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-- Send Init Bit
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if tx_req = '1' then
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tx <= UART_START;
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tx_data_tmp <= tx_data;
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tx_fsm <= data;
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tx_data_cnt <= (others=>'1');
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tx_par_bit <= '0';
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end if;
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-- Data receive
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when data =>
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tx <= tx_data_tmp(0);
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tx_par_bit <= tx_par_bit xor tx_data_tmp(0);
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if tx_data_cnt = 0 then
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if par_en = PARITY_EN then
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tx_fsm <= parity;
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else
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tx_fsm <= stop1;
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end if;
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tx_data_cnt <= (others=>'1');
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else
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tx_data_tmp <= '0' & tx_data_tmp(7 downto 1);
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tx_data_cnt <= tx_data_cnt - 1;
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end if;
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when parity =>
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tx <= tx_par_bit;
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tx_fsm <= stop1;
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-- End of communication
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when stop1 =>
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-- Send Stop Bit
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tx <= UART_IDLE;
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tx_fsm <= stop2;
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when stop2 =>
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-- Send Stop Bit
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tx_end <= '1';
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tx <= UART_IDLE;
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tx_fsm <= idle;
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-- Invalid States
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when others => null;
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end case;
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-- Reset condition
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if rst = RST_LVL then
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tx_fsm <= idle;
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tx_par_bit <= '0';
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tx_data_tmp <= (others=>'0');
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tx_data_cnt <= (others=>'0');
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end if;
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end if;
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end if;
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end process;
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rx_debounceer:process(clk)
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variable deb_buf : std_logic_vector(3 downto 0);
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begin
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if clk'event and clk = '1' then
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-- Debounce logic
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if deb_buf = "0000" then
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rx_data_deb <= '0';
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elsif deb_buf = "1111" then
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rx_data_deb <= '1';
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end if;
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-- Data storage to debounce
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deb_buf := deb_buf(2 downto 0) & rx;
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end if;
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end process;
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rx_start_detect:process(clk)
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variable rx_data_old : std_logic;
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begin
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if clk'event and clk = '1' then
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-- Falling edge detection
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if rx_data_old = '1' and rx_data_deb = '0' and rx_fsm = idle then
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rx_rcv_init <= '1';
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else
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rx_rcv_init <= '0';
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end if;
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-- Default assignments
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rx_data_old := rx_data_deb;
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-- Reset condition
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if rst = RST_LVL then
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rx_data_old := '0';
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rx_rcv_init <= '0';
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end if;
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end if;
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end process;
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rx_clk_gen:process(clk)
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variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
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begin
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if clk'event and clk = '1' then
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-- Normal Operation
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if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 or rx_rcv_init = '1' then
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rx_clk_en <= '1';
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counter := 0;
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else
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rx_clk_en <= '0';
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counter := counter + 1;
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end if;
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-- Reset condition
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if rst = RST_LVL then
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rx_clk_en <= '0';
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counter := 0;
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end if;
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end if;
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end process;
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rx_proc:process(clk)
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begin
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if clk'event and clk = '1' then
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-- Default values
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rx_ready <= '0';
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-- Enable on UART rate
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if rx_clk_en = '1' then
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-- FSM description
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case rx_fsm is
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-- Wait to transfer data
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when idle =>
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if rx_data_deb = UART_START then
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rx_fsm <= data;
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end if;
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rx_par_bit <= '0';
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rx_data_cnt <= (others=>'0');
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-- Data receive
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when data =>
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-- Check data to generate parity
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if par_en = PARITY_EN then
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rx_par_bit <= rx_par_bit xor rx;
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end if;
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if rx_data_cnt = 7 then
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-- Data path
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rx_data(7) <= rx;
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for i in 0 to 6 loop
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rx_data(i) <= rx_data_tmp(6-i);
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end loop;
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-- With parity verification
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if par_en = PARITY_EN then
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rx_fsm <= parity;
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-- Without parity verification
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else
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rx_ready <= '1';
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rx_fsm <= idle;
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end if;
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else
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rx_data_tmp <= rx_data_tmp(6 downto 0) & rx;
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rx_data_cnt <= rx_data_cnt + 1;
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end if;
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when parity =>
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-- Check received parity
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rx_fsm <= idle;
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if rx_par_bit = rx then
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rx_ready <= '1';
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end if;
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when others => null;
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end case;
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-- Reset condition
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if rst = RST_LVL then
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rx_fsm <= idle;
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rx_ready <= '0';
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rx_data <= (others=>'0');
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rx_data_tmp <= (others=>'0');
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rx_data_cnt <= (others=>'0');
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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