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Chips-2.0 Demo for Atlys Development Card
=========================================
 
:Author: Jonathan P Dawson
:Date: 2013-10-17
:email: chips@jondawson.org.uk
 
This project implements a TCP/IP stack. The TCP/IP stack acts as a server, and
can accept a single connection to a TCP port. The connection is provided as a
bidirectional stream of data to the application. The following protocols are supported:
 
        + ARP request/response (with 16 level cache)
        + ICMP echo request/response (ping)
        + TCP/IP socket
 
Synthesis Estimate
==================
 
The TCP/IP server consumes around 800 LUTs and 300 Flip-Flops in a Xilinx Spartan 6 device.
 
 
Dependencies
============
 
The stack is implemented in C, and needs Chips-2.0 to compile it into a Verilog
module.
 
Source Files
============
 
The TCP/IP stack is provided by two source files:
 
        + source/server.h
        + source/server.c
 
Configuration
=============
 
The following parameters can be configured at compile time within source/server.h:
 
        + Local Ethernet MAC address (default: 0x000102030405)
        + Local IP Address (default: 192.168.1.1)
        + Local TCP Port number (default: 80 HTTP)
 
Compile
=======
 
Compile into a Verilog module (server.v) using the following command::
 
        $ chip2/c2verilog source/server.v
 
Interface
=========
 
::
 
                             +-----------+
                             |  SERVER   |
                             +-----------+
      ethernet_rx [15:0] >===>           >===> output_socket [15:0]
                             |           |
                             |           |
      ethernet_tx [15:0] <===<           <===< input_socket [15:0]
                             +-----------+
 
 
Ethernet Interface
------------------
 
The Ethernet interface consists of two streams of data:
 
        + An input, input_eth_rx.
        + An output, output_eth_tx.
 
Both streams are 16 bits wide, and use the following protocol:
 
 
+------+-----------------+
| word |   designation   |
+------+-----------------+
|  0   | length in bytes |
+------+-----------------+
|  n   |       data      |
+------+-----------------+
 
 
Socket Interface
----------------
 
The socket interface consists of two streams of data:
 
        + An input, input_socket.
        + An output, output_socket.
 
Both streams are 16 bits wide, and use the following protocol:
 
 
+------+-----------------+
| word |   designation   |
+------+-----------------+
|  0   | length in bytes |
+------+-----------------+
|  n   |       data      |
+------+-----------------+
 
 
Stream Interconnect Conventions
===============================
 
The interfaces are based on the Chips Physical Interface Convetions which are
described in the Chips-2.0 `reference manual
`_.
 

Line No.	Rev	Author	Line
1	4	jondawson	`Chips-2.0 Demo for Atlys Development Card`
2	2	jondawson	`=========================================`
3
4			`:Author: Jonathan P Dawson`
5			`:Date: 2013-10-17`
6			`:email: chips@jondawson.org.uk`
7
8			`This project implements a TCP/IP stack. The TCP/IP stack acts as a server, and`
9			`can accept a single connection to a TCP port. The connection is provided as a`
10			`bidirectional stream of data to the application. The following protocols are supported:`
11
12			`+ ARP request/response (with 16 level cache)`
13			`+ ICMP echo request/response (ping)`
14			`+ TCP/IP socket`
15
16			`Synthesis Estimate`
17			`==================`
18
19			`The TCP/IP server consumes around 800 LUTs and 300 Flip-Flops in a Xilinx Spartan 6 device.`
20
21
22			`Dependencies`
23			`============`
24
25			`The stack is implemented in C, and needs Chips-2.0 to compile it into a Verilog`
26			`module.`
27
28			`Source Files`
29			`============`
30
31			`The TCP/IP stack is provided by two source files:`
32
33			`+ source/server.h`
34			`+ source/server.c`
35
36			`Configuration`
37			`=============`
38
39			`The following parameters can be configured at compile time within source/server.h:`
40
41	3	jondawson	`+ Local Ethernet MAC address (default: 0x000102030405)`
42			`+ Local IP Address (default: 192.168.1.1)`
43			`+ Local TCP Port number (default: 80 HTTP)`
44	2	jondawson
45			`Compile`
46			`=======`
47
48			`Compile into a Verilog module (server.v) using the following command::`
49
50			`$ chip2/c2verilog source/server.v`
51
52			`Interface`
53			`=========`
54
55	3	jondawson	`::`
56
57			`+-----------+`
58			`\| SERVER \|`
59			`+-----------+`
60			`ethernet_rx [15:0] >===> >===> output_socket [15:0]`
61			`\| \|`
62			`\| \|`
63			`ethernet_tx [15:0] <===< <===< input_socket [15:0]`
64			`+-----------+`
65
66
67	2	jondawson	`Ethernet Interface`
68			`------------------`
69
70			`The Ethernet interface consists of two streams of data:`
71
72			`+ An input, input_eth_rx.`
73			`+ An output, output_eth_tx.`
74
75			`Both streams are 16 bits wide, and use the following protocol:`
76
77
78			`+------+-----------------+`
79			`\| word \| designation \|`
80			`+------+-----------------+`
81			`\| 0 \| length in bytes \|`
82			`+------+-----------------+`
83			`\| n \| data \|`
84			`+------+-----------------+`
85
86
87			`Socket Interface`
88			`----------------`
89
90			`The socket interface consists of two streams of data:`
91
92			`+ An input, input_socket.`
93			`+ An output, output_socket.`
94
95			`Both streams are 16 bits wide, and use the following protocol:`
96
97
98			`+------+-----------------+`
99			`\| word \| designation \|`
100			`+------+-----------------+`
101			`\| 0 \| length in bytes \|`
102			`+------+-----------------+`
103			`\| n \| data \|`
104			`+------+-----------------+`
105
106
107			`Stream Interconnect Conventions`
108			`===============================`
109
110	4	jondawson	`The interfaces are based on the Chips Physical Interface Convetions which are`
111			described in the Chips-2.0 `reference manual
112			`_.
113	2	jondawson

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[/] [tcp_socket/] [trunk/] [TCPIP.rst] - Blame information for rev 4