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jondawson |
from chips.compiler.exceptions import C2CHIPError
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import chips.compiler.compiler
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import os
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import sys
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class Chip:
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"""A Chip represents a collection of components connected together by
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wires. As you create wires and component instances, you will need to tell
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them which chip they belong to. Once you have a completed chip you can:
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+ Implement it in verilog - using the generate_verilog method
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+ Automatically generate documentation - using the generate_document method
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You can create a new chip like this::
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my_chip = Chip(name = "My Chip")"""
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def __init__(self, name):
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"""Takes a single argument *name*, the name of the chip"""
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self.name = name
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self.instances = []
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self.wires = []
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self.inputs = []
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self.outputs = []
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self.components = []
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def generate_verilog(self):
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"""Generate verilog for the chip"""
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for i in self.wires:
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if i.source is None:
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raise C2CHIPError("wire %s has no source"%i.name)
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if i.sink is None:
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raise C2CHIPError("wire %s has no sink"%i.name)
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for i in self.inputs:
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if i.sink is None:
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raise C2CHIPError("input %s has no sink"%i.name)
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for i in self.outputs:
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if i.source is None:
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raise C2CHIPError("output %s has no source"%i.name)
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ports = ["clk", "rst"]
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ports += ["%s"%i.name for i in self.inputs]
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ports += ["%s_stb"%i.name for i in self.inputs]
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ports += ["%s_ack"%i.name for i in self.inputs]
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ports += ["%s"%i.name for i in self.outputs]
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ports += ["%s_stb"%i.name for i in self.outputs]
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ports += ["%s_ack"%i.name for i in self.outputs]
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ports = ", ".join(ports)
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output_file = open(self.name + ".v", "w")
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output_file.write("module %s(%s);\n"%(self.name, ports))
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output_file.write(" input clk;\n")
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output_file.write(" input rst;\n")
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for i in self.inputs:
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output_file.write(" input [15:0] %s;\n"%i.name)
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output_file.write(" input %s_stb;\n"%i.name)
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output_file.write(" output %s_ack;\n"%i.name)
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for i in self.outputs:
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output_file.write(" output [15:0] %s;\n"%i.name)
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output_file.write(" output %s_stb;\n"%i.name)
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output_file.write(" input %s_ack;\n"%i.name)
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for i in self.wires:
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output_file.write(" wire [15:0] %s;\n"%i.name)
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output_file.write(" wire %s_stb;\n"%i.name)
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output_file.write(" wire %s_ack;\n"%i.name)
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for instance in self.instances:
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component = instance.component.name
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output_file.write(" %s %s_%s(\n "%(component, component, id(instance)))
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ports = []
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ports.append(".clk(clk)")
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ports.append(".rst(rst)")
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for name, i in instance.inputs.iteritems():
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ports.append(".input_%s(%s)"%(name, i.name))
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ports.append(".input_%s_stb(%s_stb)"%(name, i.name))
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ports.append(".input_%s_ack(%s_ack)"%(name, i.name))
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for name, i in instance.outputs.iteritems():
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ports.append(".output_%s(%s)"%(name, i.name))
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ports.append(".output_%s_stb(%s_stb)"%(name, i.name))
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ports.append(".output_%s_ack(%s_ack)"%(name, i.name))
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output_file.write(",\n ".join(ports))
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output_file.write(");\n")
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output_file.write("endmodule\n")
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output_file.close()
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def generate_testbench(self, stop_clocks=None):
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"""Generate verilog for the test bench"""
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output_file = open(self.name + "_tb.v", "w")
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output_file.write("module %s_tb;\n"%self.name)
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output_file.write(" reg clk;\n")
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output_file.write(" reg rst;\n")
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for i in self.inputs:
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output_file.write(" wire [15:0] %s;\n"%i.name)
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output_file.write(" wire [15:0] %s_stb;\n"%i.name)
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output_file.write(" wire [15:0] %s_ack;\n"%i.name)
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for i in self.outputs:
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output_file.write(" wire [15:0] %s;\n"%i.name)
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output_file.write(" wire [15:0] %s_stb;\n"%i.name)
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output_file.write(" wire [15:0] %s_ack;\n"%i.name)
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output_file.write(" \n initial\n")
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output_file.write(" begin\n")
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output_file.write(" rst <= 1'b1;\n")
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output_file.write(" #50 rst <= 1'b0;\n")
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output_file.write(" end\n\n")
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if stop_clocks:
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output_file.write(" \n initial\n")
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output_file.write(" begin\n")
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output_file.write(" #%s $finish;\n"%(10*stop_clocks))
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output_file.write(" end\n\n")
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output_file.write(" \n initial\n")
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output_file.write(" begin\n")
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output_file.write(" clk <= 1'b0;\n")
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output_file.write(" while (1) begin\n")
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output_file.write(" #5 clk <= ~clk;\n")
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output_file.write(" end\n")
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output_file.write(" end\n\n")
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output_file.write(" %s uut(\n "%(self.name))
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ports = []
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ports.append(".clk(clk)")
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ports.append(".rst(rst)")
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for i in self.inputs:
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ports.append(".%s(%s)"%(i.name, i.name))
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ports.append(".%s_stb(%s_stb)"%(i.name, i.name))
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ports.append(".%s_ack(%s_ack)"%(i.name, i.name))
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for i in self.outputs:
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ports.append(".%s(%s)"%(i.name, i.name))
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ports.append(".%s_stb(%s_stb)"%(i.name, i.name))
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ports.append(".%s_ack(%s_ack)"%(i.name, i.name))
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output_file.write(",\n ".join(ports))
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output_file.write(");\n")
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output_file.write("endmodule\n")
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output_file.close()
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def compile_iverilog(self, run=False):
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"""Compile using the Iverilog simulator"""
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files = ["%s.v"%i.name for i in self.components]
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files.append(self.name + ".v")
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files.append(self.name + "_tb.v")
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files = " ".join(files)
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os.system("iverilog -o %s %s"%(self.name + "_tb", files))
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if run:
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return os.system("vvp %s"%(self.name + "_tb"))
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class Component:
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"""You can use the component class to add new components to your chip.
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Components are written in C, and you need to supply the C code for the
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component when you create it. The Chips API will automatically compile the
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C code, and extract the name, inputs, outputs and the documentation from the
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code.
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If you want to keep the C file seperate you can read it in from a file like
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this::
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my_component = Adder(C_file="adder.c")
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Once you have defined a component you can use the __call__ method to create
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an instance of the component.
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"""
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def __init__(self, C_file):
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"""Takes a single string argument, the C code to compile"""
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self.name, self.inputs, self.outputs, self.doc = chips.compiler.compiler.comp(C_file)
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def __call__(self, chip, inputs, outputs):
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"""Takes three arguments:
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+ chip, the chip that the component instance belongs to.
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+ inputs, a list of *Wires* (or *Inputs*) to connect to the component inputs
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+ outputs, a list of *Wires* (or *Outputs*) to connect to the component outputs"""
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return _Instance(self, chip, inputs, outputs)
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class _Instance:
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"""This class represents a component instance. You don't normaly need to
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create them directly, use the Component.__call__ method."""
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def __init__(self, component, chip, inputs, outputs):
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self.chip = chip
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self.inputs = inputs
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self.outputs = outputs
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self.component = component
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self.chip.instances.append(self)
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if component not in chip.components:
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chip.components.append(component)
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if len(self.component.inputs) != len(self.inputs):
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raise C2CHIPError("Instance %s does not have the right number or inputs"%self.name)
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if len(self.component.outputs) != len(self.outputs):
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raise C2CHIPError("Instance %s does not have the right number or outputs"%self.name)
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for i in inputs.values():
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if i.sink is not None:
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raise C2CHIPError("%s allready has a sink"%i.name)
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i.sink = self
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for i in outputs.values():
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if i.source is not None:
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raise C2CHIPError("%s has allready has a source"%i.name)
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i.source = self
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for i in inputs.keys():
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if i not in self.component.inputs:
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raise C2CHIPError("%s is not an input of component %s"%(i, component.name))
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for i in outputs.keys():
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if i not in self.component.outputs:
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raise C2CHIPError("%s has allready has a source %s"%(i, component.name))
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class Wire:
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"""Create a connection between two components. A wire is a point to point
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connection with one input and one output"""
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def __init__(self, chip):
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self.chip = chip
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chip.wires.append(self)
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self.source = None
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self.sink = None
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self.name = "wire_" + str(id(self))
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class Input:
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"""Create an input to the chip."""
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def __init__(self, chip, name):
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"""Takes a single argument, the chip to which the input belongs, and a
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string representing the name"""
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self.chip = chip
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chip.inputs.append(self)
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self.sink = None
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self.name = name
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class Output:
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"""Create an output from the chip."""
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def __init__(self, chip, name):
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"""Takes two argument, the chip to which the output belongs, and a
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string representing the name"""
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self.chip = chip
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chip.outputs.append(self)
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self.source = None
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self.name = name
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