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jondawson |
#!/usr/bin/env python
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"""A C to Verilog compiler"""
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__author__ = "Jon Dawson"
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__copyright__ = "Copyright (C) 2013, Jonathan P Dawson"
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__version__ = "0.1"
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def unique(l):
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"""In the absence of set in older python implementations, make list values unique"""
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return dict(zip(l, l)).keys()
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def log2(frames):
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"""Integer only algorithm to calculate the number of bits needed to store a number"""
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bits = 1
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power = 2
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while power < frames:
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bits += 1
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power *= 2
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return bits
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def to_gray(i):
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"""Convert integer to gray code"""
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return (i >> 1) ^ i
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def generate_CHIP(input_file,
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name,
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frames,
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output_file,
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registers,
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memory_size_2,
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memory_size_4,
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initialize_memory,
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memory_content_2,
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memory_content_4,
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no_tb_mode=False):
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"""A big ugly function to crunch through all the instructions and generate the CHIP equivilent"""
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#calculate the values of jump locations
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location = 0
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labels = {}
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new_frames = []
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for frame in frames:
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if frame[0]["op"] == "label":
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labels[frame[0]["label"]] = location
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else:
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new_frames.append(frame)
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location += 1
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frames = new_frames
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#substitue real values for labeled jump locations
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for frame in frames:
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for instruction in frame:
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if "label" in instruction:
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instruction["label"]=labels[instruction["label"]]
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#list all inputs and outputs used in the program
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inputs = unique([i["input"] for frame in frames for i in frame if "input" in i])
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outputs = unique([i["output"] for frame in frames for i in frame if "output" in i])
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input_files = unique([i["file_name"] for frame in frames for i in frame if "file_read" == i["op"]])
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output_files = unique([i["file_name"] for frame in frames for i in frame if "file_write" == i["op"]])
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testbench = not inputs and not outputs and not no_tb_mode
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#Do not generate a port in testbench mode
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inports = [
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("input_" + i, 16) for i in inputs
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] + [
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("input_" + i + "_stb", 1) for i in inputs
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] + [
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("output_" + i + "_ack", 1) for i in outputs
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]
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outports = [
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("output_" + i, 16) for i in outputs
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] + [
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("output_" + i + "_stb", 1) for i in outputs
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] + [
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("input_" + i + "_ack", 1) for i in inputs
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]
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#create list of signals
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signals = [
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("timer", 16),
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("program_counter", log2(len(frames))),
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("address_2", 16),
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("data_out_2", 16),
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("data_in_2", 16),
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("write_enable_2", 1),
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("address_4", 16),
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("data_out_4", 32),
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("data_in_4", 32),
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("write_enable_4", 1),
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] + [
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("register_%s"%(register), definition[1]*8) for register, definition in registers.iteritems()
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] + [
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("s_output_" + i + "_stb", 16) for i in outputs
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] + [
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("s_output_" + i, 16) for i in outputs
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] + [
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("s_input_" + i + "_ack", 16) for i in inputs
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]
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if testbench:
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signals.append(("clk", 1))
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signals.append(("rst", 1))
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else:
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inports.append(("clk", 1))
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inports.append(("rst", 1))
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#output the code in verilog
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output_file.write("//name : %s\n"%name)
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output_file.write("//tag : c components\n")
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for i in inputs:
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output_file.write("//input : input_%s:16\n"%i)
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for i in outputs:
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output_file.write("//output : output_%s:16\n"%i)
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output_file.write("//source_file : %s\n"%input_file)
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output_file.write("///%s\n"%"".join(["=" for i in name]))
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output_file.write("///\n")
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output_file.write("///*Created by C2CHIP*\n\n")
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output_file.write("// Register Allocation\n")
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output_file.write("// ===================\n")
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output_file.write("// %s %s %s \n"%("Register".center(20), "Name".center(20), "Size".center(20)))
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for register, definition in registers.iteritems():
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register_name, size = definition
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output_file.write("// %s %s %s \n"%(str(register).center(20), register_name.center(20), str(size).center(20)))
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output_file.write(" \n`timescale 1ns/1ps\n")
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output_file.write("module %s"%name)
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all_ports = [name for name, size in inports + outports]
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if all_ports:
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output_file.write("(")
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output_file.write(",".join(all_ports))
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output_file.write(");\n")
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else:
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output_file.write(";\n")
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output_file.write(" integer file_count;\n")
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input_files = dict(zip(input_files, ["input_file_%s"%i for i, j in enumerate(input_files)]))
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for i in input_files.values():
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output_file.write(" integer %s;\n"%i)
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output_files = dict(zip(output_files, ["output_file_%s"%i for i, j in enumerate(output_files)]))
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for i in output_files.values():
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output_file.write(" integer %s;\n"%i)
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def write_declaration(object_type, name, size, value=None):
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if size == 1:
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output_file.write(object_type)
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output_file.write(name)
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if value is not None:
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output_file.write("= %s'd%s"%(size,value))
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output_file.write(";\n")
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else:
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output_file.write(object_type)
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output_file.write("[%i:0]"%(size-1))
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output_file.write(" ")
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output_file.write(name)
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if value is not None:
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output_file.write("= %s'd%s"%(size,value))
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output_file.write(";\n")
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for name, size in inports:
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write_declaration(" input ", name, size)
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for name, size in outports:
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write_declaration(" output ", name, size)
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for name, size in signals:
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write_declaration(" reg ", name, size)
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memory_size_2 = int(memory_size_2)
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memory_size_4 = int(memory_size_4)
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if memory_size_2:
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output_file.write(" reg [15:0] memory_2 [%i:0];\n"%(memory_size_2-1))
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if memory_size_4:
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output_file.write(" reg [31:0] memory_4 [%i:0];\n"%(memory_size_4-1))
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#generate clock and reset in testbench mode
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if testbench:
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output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
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output_file.write(" // CLOCK AND RESET GENERATION \n")
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output_file.write(" // \n")
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output_file.write(" // This file was generated in test bench mode. In this mode, the verilog \n")
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output_file.write(" // output file can be executed directly within a verilog simulator. \n")
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output_file.write(" // In test bench mode, a simulated clock and reset signal are generated within\n")
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output_file.write(" // the output file. \n")
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output_file.write(" // Verilog files generated in testbecnch mode are not suitable for synthesis, \n")
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output_file.write(" // or for instantiation within a larger design.\n")
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output_file.write(" \n initial\n")
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output_file.write(" begin\n")
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output_file.write(" rst <= 1'b1;\n")
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output_file.write(" #50 rst <= 1'b0;\n")
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output_file.write(" end\n\n")
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output_file.write(" \n initial\n")
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output_file.write(" begin\n")
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output_file.write(" clk <= 1'b0;\n")
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output_file.write(" while (1) begin\n")
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output_file.write(" #5 clk <= ~clk;\n")
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output_file.write(" end\n")
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output_file.write(" end\n\n")
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#Generate a state machine to execute the instructions
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binary_operators = ["+", "-", "*", "/", "|", "&", "^", "<<", ">>", "<",">", ">=",
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"<=", "==", "!="]
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if initialize_memory and (memory_content_2 or memory_content_4):
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output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
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output_file.write(" // MEMORY INITIALIZATION \n")
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output_file.write(" // \n")
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output_file.write(" // In order to reduce program size, array contents have been stored into \n")
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output_file.write(" // memory at initialization. In an FPGA, this will result in the memory being \n")
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output_file.write(" // initialized when the FPGA configures. \n")
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output_file.write(" // Memory will not be re-initialized at reset. \n")
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output_file.write(" // Dissable this behaviour using the no_initialize_memory switch \n")
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output_file.write(" \n initial\n")
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output_file.write(" begin\n")
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for location, content in memory_content_2.iteritems():
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output_file.write(" memory_2[%s] = %s;\n"%(location, content))
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for location, content in memory_content_4.iteritems():
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output_file.write(" memory_4[%s] = %s;\n"%(location, content))
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output_file.write(" end\n\n")
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if input_files or output_files:
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output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
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output_file.write(" // OPEN FILES \n")
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output_file.write(" // \n")
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output_file.write(" // Open all files used at the start of the process \n")
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output_file.write(" \n initial\n")
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output_file.write(" begin\n")
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for file_name, file_ in input_files.iteritems():
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output_file.write(" %s = $fopenr(\"%s\");\n"%(file_, file_name))
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for file_name, file_ in output_files.iteritems():
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output_file.write(" %s = $fopen(\"%s\");\n"%(file_, file_name))
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output_file.write(" end\n\n")
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output_file.write("\n //////////////////////////////////////////////////////////////////////////////\n")
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output_file.write(" // FSM IMPLEMENTAION OF C PROCESS \n")
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output_file.write(" // \n")
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output_file.write(" // This section of the file contains a Finite State Machine (FSM) implementing\n")
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output_file.write(" // the C process. In general execution is sequential, but the compiler will \n")
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output_file.write(" // attempt to execute instructions in parallel if the instruction dependencies\n")
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output_file.write(" // allow. Further concurrency can be achieved by executing multiple C \n")
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output_file.write(" // processes concurrently within the device. \n")
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output_file.write(" \n always @(posedge clk)\n")
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output_file.write(" begin\n\n")
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if memory_size_2:
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output_file.write(" //implement memory for 2 byte x n arrays\n")
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output_file.write(" if (write_enable_2 == 1'b1) begin\n")
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output_file.write(" memory_2[address_2] <= data_in_2;\n")
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output_file.write(" end\n")
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output_file.write(" data_out_2 <= memory_2[address_2];\n")
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output_file.write(" write_enable_2 <= 1'b0;\n\n")
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if memory_size_4:
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output_file.write(" //implement memory for 4 byte x n arrays\n")
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output_file.write(" if (write_enable_4 == 1'b1) begin\n")
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output_file.write(" memory_4[address_4] <= data_in_4;\n")
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output_file.write(" end\n")
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output_file.write(" data_out_4 <= memory_4[address_4];\n")
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output_file.write(" write_enable_4 <= 1'b0;\n\n")
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output_file.write(" //implement timer\n")
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output_file.write(" timer <= 16'h0000;\n\n")
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output_file.write(" case(program_counter)\n\n")
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#A frame is executed in each state
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for location, frame in enumerate(frames):
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output_file.write(" 16'd%s:\n"%to_gray(location))
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output_file.write(" begin\n")
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output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
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for instruction in frame:
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if instruction["op"] == "literal":
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output_file.write(
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" register_%s <= %s;\n"%(
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instruction["dest"],
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instruction["literal"]))
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elif instruction["op"] == "move":
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output_file.write(
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" register_%s <= register_%s;\n"%(
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instruction["dest"],
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instruction["src"]))
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elif instruction["op"] in ["~"]:
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output_file.write(
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" register_%s <= ~register_%s;\n"%(
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instruction["dest"],
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instruction["src"]))
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elif instruction["op"] in binary_operators and "left" in instruction:
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if not instruction["signed"]:
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output_file.write(
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" register_%s <= %s %s $unsigned(register_%s);\n"%(
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instruction["dest"],
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instruction["left"],
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instruction["op"],
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instruction["src"]))
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else:
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#Verilog uses >>> as an arithmetic right shift
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if instruction["op"] == ">>":
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instruction["op"] = ">>>"
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output_file.write(
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" register_%s <= %s %s $signed(register_%s);\n"%(
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instruction["dest"],
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instruction["left"],
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instruction["op"],
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instruction["src"]))
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|
|
elif instruction["op"] in binary_operators and "right" in instruction:
|
333 |
|
|
if not instruction["signed"]:
|
334 |
|
|
output_file.write(
|
335 |
|
|
" register_%s <= $unsigned(register_%s) %s %s;\n"%(
|
336 |
|
|
instruction["dest"],
|
337 |
|
|
instruction["src"],
|
338 |
|
|
instruction["op"],
|
339 |
|
|
instruction["right"]))
|
340 |
|
|
else:
|
341 |
|
|
#Verilog uses >>> as an arithmetic right shift
|
342 |
|
|
if instruction["op"] == ">>":
|
343 |
|
|
instruction["op"] = ">>>"
|
344 |
|
|
output_file.write(
|
345 |
|
|
" register_%s <= $signed(register_%s) %s %s;\n"%(
|
346 |
|
|
instruction["dest"],
|
347 |
|
|
instruction["src"],
|
348 |
|
|
instruction["op"],
|
349 |
|
|
instruction["right"]))
|
350 |
|
|
|
351 |
|
|
elif instruction["op"] in binary_operators:
|
352 |
|
|
if not instruction["signed"]:
|
353 |
|
|
output_file.write(
|
354 |
|
|
" register_%s <= $unsigned(register_%s) %s $unsigned(register_%s);\n"%(
|
355 |
|
|
instruction["dest"],
|
356 |
|
|
instruction["src"],
|
357 |
|
|
instruction["op"],
|
358 |
|
|
instruction["srcb"]))
|
359 |
|
|
else:
|
360 |
|
|
#Verilog uses >>> as an arithmetic right shift
|
361 |
|
|
if instruction["op"] == ">>":
|
362 |
|
|
instruction["op"] = ">>>"
|
363 |
|
|
output_file.write(
|
364 |
|
|
" register_%s <= $signed(register_%s) %s $signed(register_%s);\n"%(
|
365 |
|
|
instruction["dest"],
|
366 |
|
|
instruction["src"],
|
367 |
|
|
instruction["op"],
|
368 |
|
|
instruction["srcb"]))
|
369 |
|
|
|
370 |
|
|
elif instruction["op"] == "jmp_if_false":
|
371 |
|
|
output_file.write(" if (register_%s == 0)\n"%(instruction["src"]));
|
372 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(instruction["label"]&0xffff))
|
373 |
|
|
|
374 |
|
|
elif instruction["op"] == "jmp_if_true":
|
375 |
|
|
output_file.write(" if (register_%s != 0)\n"%(instruction["src"]));
|
376 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(instruction["label"]&0xffff))
|
377 |
|
|
|
378 |
|
|
elif instruction["op"] == "jmp_and_link":
|
379 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(instruction["label"]&0xffff))
|
380 |
|
|
output_file.write(" register_%s <= 16'd%s;\n"%(
|
381 |
|
|
instruction["dest"], to_gray((location+1)&0xffff)))
|
382 |
|
|
|
383 |
|
|
elif instruction["op"] == "jmp_to_reg":
|
384 |
|
|
output_file.write(
|
385 |
|
|
" program_counter <= register_%s;\n"%instruction["src"])
|
386 |
|
|
|
387 |
|
|
elif instruction["op"] == "goto":
|
388 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%(to_gray(instruction["label"]&0xffff)))
|
389 |
|
|
|
390 |
|
|
elif instruction["op"] == "file_read":
|
391 |
|
|
output_file.write(" file_count = $fscanf(%s, \"%%d\\n\", register_%s);\n"%(
|
392 |
|
|
input_files[instruction["file_name"]], instruction["dest"]))
|
393 |
|
|
|
394 |
|
|
elif instruction["op"] == "file_write":
|
395 |
|
|
output_file.write(" $fdisplay(%s, \"%%d\", register_%s);\n"%(
|
396 |
|
|
output_files[instruction["file_name"]], instruction["src"]))
|
397 |
|
|
|
398 |
|
|
elif instruction["op"] == "read":
|
399 |
|
|
output_file.write(" register_%s <= input_%s;\n"%(
|
400 |
|
|
instruction["dest"], instruction["input"]))
|
401 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
402 |
|
|
output_file.write(" s_input_%s_ack <= 1'b1;\n"%instruction["input"])
|
403 |
|
|
output_file.write( " if (s_input_%s_ack == 1'b1 && input_%s_stb == 1'b1) begin\n"%(
|
404 |
|
|
instruction["input"],
|
405 |
|
|
instruction["input"]
|
406 |
|
|
))
|
407 |
|
|
output_file.write(" s_input_%s_ack <= 1'b0;\n"%instruction["input"])
|
408 |
|
|
output_file.write(" program_counter <= 16'd%s;\n"%to_gray(location+1))
|
409 |
|
|
output_file.write(" end\n")
|
410 |
|
|
|
411 |
|
|
elif instruction["op"] == "ready":
|
412 |
|
|
output_file.write(" register_%s <= 0;\n"%instruction["dest"])
|
413 |
|
|
output_file.write(" register_%s[0] <= input_%s_stb;\n"%(
|
414 |
|
|
instruction["dest"], instruction["input"]))
|
415 |
|
|
|
416 |
|
|
elif instruction["op"] == "write":
|
417 |
|
|
output_file.write(" s_output_%s <= register_%s;\n"%(
|
418 |
|
|
instruction["output"], instruction["src"]))
|
419 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location))
|
420 |
|
|
output_file.write(" s_output_%s_stb <= 1'b1;\n"%instruction["output"])
|
421 |
|
|
output_file.write(
|
422 |
|
|
" if (s_output_%s_stb == 1'b1 && output_%s_ack == 1'b1) begin\n"%(
|
423 |
|
|
instruction["output"],
|
424 |
|
|
instruction["output"]
|
425 |
|
|
))
|
426 |
|
|
output_file.write(" s_output_%s_stb <= 1'b0;\n"%instruction["output"])
|
427 |
|
|
output_file.write(" program_counter <= %s;\n"%to_gray(location+1))
|
428 |
|
|
output_file.write(" end\n")
|
429 |
|
|
|
430 |
|
|
elif instruction["op"] == "memory_read_request":
|
431 |
|
|
output_file.write(
|
432 |
|
|
" address_%s <= register_%s;\n"%(
|
433 |
|
|
instruction["element_size"],
|
434 |
|
|
instruction["src"])
|
435 |
|
|
)
|
436 |
|
|
|
437 |
|
|
elif instruction["op"] == "memory_read_wait":
|
438 |
|
|
pass
|
439 |
|
|
|
440 |
|
|
elif instruction["op"] == "memory_read":
|
441 |
|
|
output_file.write(
|
442 |
|
|
" register_%s <= data_out_%s;\n"%(
|
443 |
|
|
instruction["dest"],
|
444 |
|
|
instruction["element_size"])
|
445 |
|
|
)
|
446 |
|
|
|
447 |
|
|
elif instruction["op"] == "memory_write":
|
448 |
|
|
output_file.write(" address_%s <= register_%s;\n"%(
|
449 |
|
|
instruction["element_size"],
|
450 |
|
|
instruction["src"])
|
451 |
|
|
)
|
452 |
|
|
output_file.write(" data_in_%s <= register_%s;\n"%(
|
453 |
|
|
instruction["element_size"],
|
454 |
|
|
instruction["srcb"])
|
455 |
|
|
)
|
456 |
|
|
output_file.write(" write_enable_%s <= 1'b1;\n"%(
|
457 |
|
|
instruction["element_size"])
|
458 |
|
|
)
|
459 |
|
|
|
460 |
|
|
elif instruction["op"] == "memory_write_literal":
|
461 |
|
|
output_file.write(" address_%s <= 16'd%s;\n"%(
|
462 |
|
|
instruction["element_size"],
|
463 |
|
|
instruction["address"])
|
464 |
|
|
)
|
465 |
|
|
output_file.write(" data_in_%s <= %s;\n"%(
|
466 |
|
|
instruction["element_size"],
|
467 |
|
|
instruction["value"])
|
468 |
|
|
)
|
469 |
|
|
output_file.write(" write_enable_%s <= 1'b1;\n"%(
|
470 |
|
|
instruction["element_size"])
|
471 |
|
|
)
|
472 |
|
|
|
473 |
|
|
elif instruction["op"] == "assert":
|
474 |
|
|
output_file.write( " if (register_%s == 0) begin\n"%instruction["src"])
|
475 |
|
|
output_file.write( " $display(\"Assertion failed at line: %s in file: %s\");\n"%(
|
476 |
|
|
instruction["line"],
|
477 |
|
|
instruction["file"]
|
478 |
|
|
))
|
479 |
|
|
output_file.write( " $finish_and_return(1);\n")
|
480 |
|
|
output_file.write( " end\n")
|
481 |
|
|
|
482 |
|
|
elif instruction["op"] == "wait_clocks":
|
483 |
|
|
output_file.write(" if (timer < register_%s) begin\n"%instruction["src"])
|
484 |
|
|
output_file.write(" program_counter <= program_counter;\n")
|
485 |
|
|
output_file.write(" timer <= timer+1;\n")
|
486 |
|
|
output_file.write(" end\n")
|
487 |
|
|
|
488 |
|
|
elif instruction["op"] == "report":
|
489 |
|
|
if not instruction["signed"]:
|
490 |
|
|
output_file.write(
|
491 |
|
|
' $display ("%%d (report at line: %s in file: %s)", $unsigned(register_%s));\n'%(
|
492 |
|
|
instruction["line"],
|
493 |
|
|
instruction["file"],
|
494 |
|
|
instruction["src"],
|
495 |
|
|
))
|
496 |
|
|
else:
|
497 |
|
|
output_file.write(
|
498 |
|
|
' $display ("%%d (report at line: %s in file: %s)", $signed(register_%s));\n'%(
|
499 |
|
|
instruction["line"],
|
500 |
|
|
instruction["file"],
|
501 |
|
|
instruction["src"],
|
502 |
|
|
))
|
503 |
|
|
|
504 |
|
|
elif instruction["op"] == "stop":
|
505 |
|
|
#If we are in testbench mode stop the simulation
|
506 |
|
|
#If we are part of a larger design, other C programs may still be running
|
507 |
|
|
for file_ in input_files.values():
|
508 |
|
|
output_file.write(" $fclose(%s);\n"%file_)
|
509 |
|
|
for file_ in output_files.values():
|
510 |
|
|
output_file.write(" $fclose(%s);\n"%file_)
|
511 |
|
|
if testbench:
|
512 |
|
|
output_file.write(' $finish;\n')
|
513 |
|
|
output_file.write(" program_counter <= program_counter;\n")
|
514 |
|
|
output_file.write(" end\n\n")
|
515 |
|
|
|
516 |
|
|
output_file.write(" endcase\n")
|
517 |
|
|
|
518 |
|
|
#Reset program counter and control signals
|
519 |
|
|
output_file.write(" if (rst == 1'b1) begin\n")
|
520 |
|
|
output_file.write(" program_counter <= 0;\n")
|
521 |
|
|
for i in inputs:
|
522 |
|
|
output_file.write(" s_input_%s_ack <= 0;\n"%(i))
|
523 |
|
|
for i in outputs:
|
524 |
|
|
output_file.write(" s_output_%s_stb <= 0;\n"%(i))
|
525 |
|
|
output_file.write(" end\n")
|
526 |
|
|
output_file.write(" end\n")
|
527 |
|
|
for i in inputs:
|
528 |
|
|
output_file.write(" assign input_%s_ack = s_input_%s_ack;\n"%(i, i))
|
529 |
|
|
for i in outputs:
|
530 |
|
|
output_file.write(" assign output_%s_stb = s_output_%s_stb;\n"%(i, i))
|
531 |
|
|
output_file.write(" assign output_%s = s_output_%s;\n"%(i, i))
|
532 |
|
|
output_file.write("\nendmodule\n")
|
533 |
|
|
|
534 |
|
|
return inputs, outputs
|