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Subversion Repositories tcp_socket

[/] [tcp_socket/] [trunk/] [chips2/] [interconnect.py] - Blame information for rev 2

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#!/usr/bin/env python
 
from chips.api.api import *
import sys
 
 
my_chip = Chip("interconnect")
wire = Wire(my_chip)
Component("test_suite/producer.c")(my_chip, inputs={}, outputs={"z":wire})
Component("test_suite/consumer.c")(my_chip, inputs={"a":wire}, outputs={})
my_chip.generate_verilog()
my_chip.generate_testbench(100000)
my_chip.compile_iverilog(True)
 
my_chip = Chip("interconnect")
wire = Wire(my_chip)
Component("test_suite/slow_producer.c")(my_chip, inputs={}, outputs={"z":wire})
Component("test_suite/consumer.c")(my_chip, inputs={"a":wire}, outputs={})
my_chip.generate_verilog()
my_chip.generate_testbench(100000)
my_chip.compile_iverilog(True)
 
my_chip = Chip("interconnect")
wire = Wire(my_chip)
Component("test_suite/producer.c")(my_chip, inputs={}, outputs={"z":wire})
Component("test_suite/slow_consumer.c")(my_chip, inputs={"a":wire}, outputs={})
my_chip.generate_verilog()
my_chip.generate_testbench(100000)
my_chip.compile_iverilog(True)
 
my_chip = Chip("interconnect")
wire = Wire(my_chip)
Component("test_suite/slow_producer.c")(my_chip, inputs={}, outputs={"z":wire})
Component("test_suite/slow_consumer.c")(my_chip, inputs={"a":wire}, outputs={})
my_chip.generate_verilog()
my_chip.generate_testbench(100000)
my_chip.compile_iverilog(True)
 
os.remove("producer.v")
os.remove("consumer.v")
os.remove("interconnect_tb")
os.remove("interconnect.v")
os.remove("interconnect_tb.v")

Line No.	Rev	Author	Line
1	2	jondawson	`#!/usr/bin/env python`
2
3			`from chips.api.api import *`
4			`import sys`
5
6
7			`my_chip = Chip("interconnect")`
8			`wire = Wire(my_chip)`
9			`Component("test_suite/producer.c")(my_chip, inputs={}, outputs={"z":wire})`
10			`Component("test_suite/consumer.c")(my_chip, inputs={"a":wire}, outputs={})`
11			`my_chip.generate_verilog()`
12			`my_chip.generate_testbench(100000)`
13			`my_chip.compile_iverilog(True)`
14
15			`my_chip = Chip("interconnect")`
16			`wire = Wire(my_chip)`
17			`Component("test_suite/slow_producer.c")(my_chip, inputs={}, outputs={"z":wire})`
18			`Component("test_suite/consumer.c")(my_chip, inputs={"a":wire}, outputs={})`
19			`my_chip.generate_verilog()`
20			`my_chip.generate_testbench(100000)`
21			`my_chip.compile_iverilog(True)`
22
23			`my_chip = Chip("interconnect")`
24			`wire = Wire(my_chip)`
25			`Component("test_suite/producer.c")(my_chip, inputs={}, outputs={"z":wire})`
26			`Component("test_suite/slow_consumer.c")(my_chip, inputs={"a":wire}, outputs={})`
27			`my_chip.generate_verilog()`
28			`my_chip.generate_testbench(100000)`
29			`my_chip.compile_iverilog(True)`
30
31			`my_chip = Chip("interconnect")`
32			`wire = Wire(my_chip)`
33			`Component("test_suite/slow_producer.c")(my_chip, inputs={}, outputs={"z":wire})`
34			`Component("test_suite/slow_consumer.c")(my_chip, inputs={"a":wire}, outputs={})`
35			`my_chip.generate_verilog()`
36			`my_chip.generate_testbench(100000)`
37			`my_chip.compile_iverilog(True)`
38
39			`os.remove("producer.v")`
40			`os.remove("consumer.v")`
41			`os.remove("interconnect_tb")`
42			`os.remove("interconnect.v")`
43			`os.remove("interconnect_tb.v")`

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[/] [tcp_socket/] [trunk/] [chips2/] [interconnect.py] - Blame information for rev 2