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--------------------------------------------------------------------------------
---
---  CHIPS - 2.0 Simple Web App Demo
---
---  :Author: Jonathan P Dawson
---  :Date: 17/10/2013
---  :email: chips@jondawson.org.uk
---  :license: MIT
---  :Copyright: Copyright (C) Jonathan P Dawson 2013
---
---  A Serial Input Component
---
--------------------------------------------------------------------------------
---
---           +--------------+
---           | CLOCK TREE   |
---           +--------------+
---           |              >-- CLK1   (50MHz) ---> CLK
--- CLK_IN >-->              |
---           |              >-- CLK2   (100MHz)
---           |              |                     +-------+
---           |              +-- CLK3   (125MHz) ->+ ODDR2 +-->[GTXCLK]
---           |              |                     |       |
---           |              +-- CLK3_N (125MHZ) ->+       |
---           |              |                     +-------+
--- RST >----->              >-- CLK4   (200MHz)
---           |              |
---           |              |
---           |              |  CLK >--+--------+
---           |              |         |        |
---           |              |      +--v-+   +--v-+
---           |              |      |    |   |    |
---           |       LOCKED >------>    >--->    >-------> INTERNAL_RESET
---           |              |      |    |   |    |
---           +--------------+      +----+   +----+
---
---              +-------------+     +--------------+               
---              | SERVER      |     | USER DESIGN  |
---              +-------------+     +--------------+
---              |             |     |              |
---              |             >----->              <-------< SWITCHES
---              |             |     |              |
---              |             <-----<              >-------> LEDS
---              |             |     |              |               
---              |             |     |              <-------< BUTTONS
---              |             |     |              |
---              |             |     +----^----v----+
---              |             |          |    |
---              |             |     +----^----v----+
---              |             |     | UART         |
---              |             |     +--------------+
---              |             |     |              >-------> RS232-TX
---              |             |     |              |
---              +---v-----^---+     |              <-------< RS232-RX 
---                  |     |         +--------------+
---              +---v-----^---+           
---              | ETHERNET    |           
---              | MAC         |           
---              +-------------+           
---              |             +------> [PHY_RESET]           
---              |             |           
---[RXCLK] ----->+             +------> [TXCLK]           
---              |             |           
--- 125MHZ ----->+             +------> open           
---              |             |           
---  [RXD] ----->+             +------> [TXD]
---              |             |           
--- [RXDV] ----->+             +------> [TXEN]           
---              |             |           
--- [RXER] ----->+             +------> [TXER]           
---              |             |           
---              |             |
---              +-------------+
---
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library unisim;
use unisim.vcomponents.all;
 
entity ATLYS is
  port(
   CLK_IN        : in    std_logic;
   RST           : in    std_logic;
 
   --PHY INTERFACE
   TX            : out   std_logic;
   RX            : in    std_logic;
   PHY_RESET     : out   std_logic;
   RXDV          : in    std_logic;
   RXER          : in    std_logic;
   RXCLK         : in    std_logic;
   RXD           : in    std_logic_vector(7 downto 0);
   TXCLK         : in    std_logic;
   GTXCLK        : out   std_logic;
   TXD           : out   std_logic_vector(7 downto 0);
   TXEN          : out   std_logic;
   TXER          : out   std_logic;
 
   --LEDS
   GPIO_LEDS     : out std_logic_vector(7 downto 0);
   GPIO_SWITCHES : in  std_logic_vector(7 downto 0);
   GPIO_BUTTONS  : in  std_logic_vector(3 downto 0);
 
   --RS232 INTERFACE
   RS232_RX      : in    std_logic;
   RS232_TX      : out   std_logic
  );
end entity ATLYS;
 
architecture RTL of ATLYS is
 
  component gigabit_ethernet is
    port(
      CLK         : in  std_logic;
      RST         : in  std_logic;
 
      --Ethernet Clock
      CLK_125_MHZ : in  std_logic;
 
      --GMII IF
      GTXCLK      : out std_logic;
      TXCLK       : in  std_logic;
      TXER        : out std_logic;
      TXEN        : out std_logic;
      TXD         : out std_logic_vector(7 downto 0);
      PHY_RESET   : out std_logic;
      RXCLK       : in  std_logic;
      RXER        : in  std_logic;
      RXDV        : in  std_logic;
      RXD         : in  std_logic_vector(7 downto 0);
 
      --RX STREAM
      TX          : in  std_logic_vector(15 downto 0);
      TX_STB      : in  std_logic;
      TX_ACK      : out std_logic;
 
      --RX STREAM
      RX          : out std_logic_vector(15 downto 0);
      RX_STB      : out std_logic;
      RX_ACK      : in  std_logic
    );
  end component gigabit_ethernet;
 
  component SERVER is
    port(
      CLK : in std_logic;
      RST : in std_logic;
 
      --ETH RX STREAM
      INPUT_ETH_RX : in std_logic_vector(15 downto 0);
      INPUT_ETH_RX_STB : in std_logic;
      INPUT_ETH_RX_ACK : out std_logic;
 
      --ETH TX STREAM
      output_eth_tx : out std_logic_vector(15 downto 0);
      OUTPUT_ETH_TX_STB : out std_logic;
      OUTPUT_ETH_TX_ACK : in std_logic;
 
      --SOCKET RX STREAM
      INPUT_SOCKET : in std_logic_vector(15 downto 0);
      INPUT_SOCKET_STB : in std_logic;
      INPUT_SOCKET_ACK : out std_logic;
 
      --SOCKET TX STREAM
      OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
      OUTPUT_SOCKET_STB : out std_logic;
      OUTPUT_SOCKET_ACK : in std_logic
 
    );
  end component;
 
  component USER_DESIGN is
    port(
      CLK : in std_logic;
      RST : in std_logic;
 
      OUTPUT_LEDS : out std_logic_vector(15 downto 0);
      OUTPUT_LEDS_STB : out std_logic;
      OUTPUT_LEDS_ACK : in std_logic;
 
      INPUT_SWITCHES : in std_logic_vector(15 downto 0);
      INPUT_SWITCHES_STB : in std_logic;
      INPUT_SWITCHES_ACK : out std_logic;
 
      INPUT_BUTTONS : in std_logic_vector(15 downto 0);
      INPUT_BUTTONS_STB : in std_logic;
      INPUT_BUTTONS_ACK : out std_logic;
 
      --SOCKET RX STREAM
      INPUT_SOCKET : in std_logic_vector(15 downto 0);
      INPUT_SOCKET_STB : in std_logic;
      INPUT_SOCKET_ACK : out std_logic;
 
      --SOCKET TX STREAM
      OUTPUT_SOCKET : out std_logic_vector(15 downto 0);
      OUTPUT_SOCKET_STB : out std_logic;
      OUTPUT_SOCKET_ACK : in std_logic;
 
      --RS232 RX STREAM
      INPUT_RS232_RX : in std_logic_vector(15 downto 0);
      INPUT_RS232_RX_STB : in std_logic;
      INPUT_RS232_RX_ACK : out std_logic;
 
      --RS232 TX STREAM
      OUTPUT_RS232_TX : out std_logic_vector(15 downto 0);
      OUTPUT_RS232_TX_STB : out std_logic;
      OUTPUT_RS232_TX_ACK : in std_logic
 
 
    );
  end component;
 
  component SERIAL_INPUT is
    generic(
      CLOCK_FREQUENCY : integer;
      BAUD_RATE       : integer
    );
    port(
      CLK      : in std_logic;
      RST      : in std_logic;
      RX       : in std_logic;
 
      OUT1     : out std_logic_vector(7 downto 0);
      OUT1_STB : out std_logic;
      OUT1_ACK : in  std_logic
    );
  end component SERIAL_INPUT;
 
  component serial_output is
    generic(
      CLOCK_FREQUENCY : integer;
      BAUD_RATE       : integer
    );
    port(
      CLK     : in std_logic;
      RST     : in  std_logic;
      TX      : out std_logic;
 
      IN1     : in std_logic_vector(7 downto 0);
      IN1_STB : in std_logic;
      IN1_ACK : out std_logic
    );
  end component serial_output;
 
  --chips signals
  signal CLK : std_logic;
  signal RST_INV : std_logic;
 
  --clock tree signals
  signal clkin1            : std_logic;
  -- Output clock buffering
  signal clkfb             : std_logic;
  signal clk0              : std_logic;
  signal clk2x             : std_logic;
  signal clkfx             : std_logic;
  signal clkfx180          : std_logic;
  signal clkdv             : std_logic;
  signal clkfbout          : std_logic;
  signal locked_internal   : std_logic;
  signal status_internal   : std_logic_vector(7 downto 0);
  signal CLK_OUT1          : std_logic;
  signal CLK_OUT2          : std_logic;
  signal CLK_OUT3          : std_logic;
  signal CLK_OUT3_N        : std_logic;
  signal CLK_OUT4          : std_logic;
  signal NOT_LOCKED        : std_logic;
  signal INTERNAL_RST      : std_logic;
  signal RXD1              : std_logic;
  signal TX_LOCKED         : std_logic;
  signal INTERNAL_RXCLK    : std_logic;
  signal INTERNAL_RXCLK_BUF: std_logic;
  signal RXCLK_BUF         : std_logic;
 
  signal INTERNAL_TXD      : std_logic_vector(7 downto 0);
  signal INTERNAL_TXEN     : std_logic;
  signal INTERNAL_TXER     : std_logic;
 
  signal OUTPUT_LEDS : std_logic_vector(15 downto 0);
  signal OUTPUT_LEDS_STB : std_logic;
  signal OUTPUT_LEDS_ACK : std_logic;
 
  signal INPUT_SWITCHES : std_logic_vector(15 downto 0);
  signal INPUT_SWITCHES_STB : std_logic;
  signal INPUT_SWITCHES_ACK : std_logic;
  signal GPIO_SWITCHES_D : std_logic_vector(7 downto 0);
 
  signal INPUT_BUTTONS : std_logic_vector(15 downto 0);
  signal INPUT_BUTTONS_STB : std_logic;
  signal INPUT_BUTTONS_ACK : std_logic;
  signal GPIO_BUTTONS_D : std_logic_vector(3 downto 0);
 
  --ETH RX STREAM
  signal ETH_RX          : std_logic_vector(15 downto 0);
  signal ETH_RX_STB      : std_logic;
  signal ETH_RX_ACK      : std_logic;
 
  --ETH TX STREAM
  signal ETH_TX          : std_logic_vector(15 downto 0);
  signal ETH_TX_STB      : std_logic;
  signal ETH_TX_ACK      : std_logic;
 
  --RS232 RX STREAM
  signal INPUT_RS232_RX     : std_logic_vector(15 downto 0);
  signal INPUT_RS232_RX_STB : std_logic;
  signal INPUT_RS232_RX_ACK : std_logic;
 
  --RS232 TX STREAM
  signal OUTPUT_RS232_TX     : std_logic_vector(15 downto 0);
  signal OUTPUT_RS232_TX_STB      : std_logic;
  signal OUTPUT_RS232_TX_ACK      : std_logic;
 
  --SOCKET RX STREAM
  signal INPUT_SOCKET          : std_logic_vector(15 downto 0);
  signal INPUT_SOCKET_STB      : std_logic;
  signal INPUT_SOCKET_ACK      : std_logic;
 
  --SOCKET TX STREAM
  signal OUTPUT_SOCKET          : std_logic_vector(15 downto 0);
  signal OUTPUT_SOCKET_STB      : std_logic;
  signal OUTPUT_SOCKET_ACK      : std_logic;
 
begin
 
  gigabit_ethernet_inst_1 : gigabit_ethernet port map(
      CLK         => CLK,
      RST         => INTERNAL_RST,
 
      --Ethernet Clock
      CLK_125_MHZ => CLK_OUT3,
 
      --GMII IF
      GTXCLK      => open,
      TXCLK       => TXCLK,
      TXER        => INTERNAL_TXER,
      TXEN        => INTERNAL_TXEN,
      TXD         => INTERNAL_TXD,
      PHY_RESET   => PHY_RESET,
      RXCLK       => INTERNAL_RXCLK,
      RXER        => RXER,
      RXDV        => RXDV,
      RXD         => RXD,
 
      --RX STREAM
      TX          => ETH_TX,
      TX_STB      => ETH_TX_STB,
      TX_ACK      => ETH_TX_ACK,
 
      --RX STREAM
      RX          => ETH_RX,
      RX_STB      => ETH_RX_STB,
      RX_ACK      => ETH_RX_ACK
    );
 
  SERVER_INST_1 : SERVER port map(
      CLK => CLK,
      RST => INTERNAL_RST,
 
      --ETH RX STREAM
      INPUT_ETH_RX => ETH_RX,
      INPUT_ETH_RX_STB => ETH_RX_STB,
      INPUT_ETH_RX_ACK => ETH_RX_ACK,
 
      --ETH TX STREAM
      OUTPUT_ETH_TX => ETH_TX,
      OUTPUT_ETH_TX_STB => ETH_TX_STB,
      OUTPUT_ETH_TX_ACK => ETH_TX_ACK,
 
      --SOCKET STREAM
      INPUT_SOCKET => INPUT_SOCKET,
      INPUT_SOCKET_STB => INPUT_SOCKET_STB,
      INPUT_SOCKET_ACK => INPUT_SOCKET_ACK,
 
      --SOCKET STREAM
      OUTPUT_SOCKET => OUTPUT_SOCKET,
      OUTPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
      OUTPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK
 
    );
 
  USER_DESIGN_INST_1 : USER_DESIGN port map(
      CLK => CLK,
      RST => INTERNAL_RST,
 
      OUTPUT_LEDS => OUTPUT_LEDS,
      OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
      OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
 
      INPUT_SWITCHES => INPUT_SWITCHES,
      INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
      INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
 
      INPUT_BUTTONS => INPUT_BUTTONS,
      INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
      INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
 
      --RS232 RX STREAM
      INPUT_RS232_RX => INPUT_RS232_RX,
      INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
      INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
 
      --RS232 TX STREAM
      OUTPUT_RS232_TX => OUTPUT_RS232_TX,
      OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
      OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
 
      --SOCKET STREAM
      INPUT_SOCKET => OUTPUT_SOCKET,
      INPUT_SOCKET_STB => OUTPUT_SOCKET_STB,
      INPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK,
 
      --SOCKET STREAM
      OUTPUT_SOCKET => INPUT_SOCKET,
      OUTPUT_SOCKET_STB => INPUT_SOCKET_STB,
      OUTPUT_SOCKET_ACK => INPUT_SOCKET_ACK
 
  );
 
  SERIAL_OUTPUT_INST_1 : serial_output generic map(
      CLOCK_FREQUENCY => 50000000,
      BAUD_RATE       => 115200
  )port map(
      CLK     => CLK,
      RST     => INTERNAL_RST,
      TX      => RS232_TX,
 
      IN1     => OUTPUT_RS232_TX(7 downto 0),
      IN1_STB => OUTPUT_RS232_TX_STB,
      IN1_ACK => OUTPUT_RS232_TX_ACK
  );
 
  SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
      CLOCK_FREQUENCY => 50000000,
      BAUD_RATE       => 115200
  ) port map (
      CLK      => CLK,
      RST      => INTERNAL_RST,
      RX       => RS232_RX,
 
      OUT1     => INPUT_RS232_RX(7 downto 0),
      OUT1_STB => INPUT_RS232_RX_STB,
      OUT1_ACK => INPUT_RS232_RX_ACK
  );
 
  INPUT_RS232_RX(15 downto 8) <= (others => '0');
 
  process
  begin
    wait until rising_edge(CLK);
    NOT_LOCKED <= not LOCKED_INTERNAL;
    INTERNAL_RST <= NOT_LOCKED;
 
    if OUTPUT_LEDS_STB = '1' then
       GPIO_LEDS <= OUTPUT_LEDS(7 downto 0);
    end if;
    OUTPUT_LEDS_ACK <= '1';
 
    INPUT_SWITCHES_STB <= '1';
    GPIO_SWITCHES_D <= GPIO_SWITCHES;
    INPUT_SWITCHES(7 downto 0) <= GPIO_SWITCHES_D;
    INPUT_SWITCHES(15 downto 8) <= (others => '0');
 
    INPUT_BUTTONS_STB <= '1';
    GPIO_BUTTONS_D <= GPIO_BUTTONS;
    INPUT_BUTTONS(3 downto 0) <= GPIO_BUTTONS_D;
    INPUT_BUTTONS(15 downto 4) <= (others => '0');
 
  end process;
 
 
  -------------------------
  -- Output     Output     
  -- Clock     Freq (MHz)  
  -------------------------
  -- CLK_OUT1    50.000    
  -- CLK_OUT2   100.000    
  -- CLK_OUT3   125.000    
  -- CLK_OUT4   200.000    
 
  ----------------------------------
  -- Input Clock   Input Freq (MHz) 
  ----------------------------------
  -- primary         200.000        
 
 
  -- Input buffering
  --------------------------------------
  clkin1_buf : IBUFG
  port map
   (O  => clkin1,
    I  => CLK_IN);
 
 
  -- Clocking primitive
  --------------------------------------
  -- Instantiation of the DCM primitive
  --    * Unused inputs are tied off
  --    * Unused outputs are labeled unused
  dcm_sp_inst: DCM_SP
  generic map
   (CLKDV_DIVIDE          => 2.000,
    CLKFX_DIVIDE          => 4,
    CLKFX_MULTIPLY        => 5,
    CLKIN_DIVIDE_BY_2     => FALSE,
    CLKIN_PERIOD          => 10.0,
    CLKOUT_PHASE_SHIFT    => "NONE",
    CLK_FEEDBACK          => "1X",
    DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
    PHASE_SHIFT           => 0,
    STARTUP_WAIT          => FALSE)
  port map
   -- Input clock
   (CLKIN                 => clkin1,
    CLKFB                 => clkfb,
    -- Output clocks
    CLK0                  => clk0,
    CLK90                 => open,
    CLK180                => open,
    CLK270                => open,
    CLK2X                 => clk2x,
    CLK2X180              => open,
    CLKFX                 => clkfx,
    CLKFX180              => clkfx180,
    CLKDV                 => clkdv,
   -- Ports for dynamic phase shift
    PSCLK                 => '0',
    PSEN                  => '0',
    PSINCDEC              => '0',
    PSDONE                => open,
   -- Other control and status signals
    LOCKED                => TX_LOCKED,
    STATUS                => status_internal,
    RST                   => RST_INV,
   -- Unused pin, tie low
    DSSEN                 => '0');
 
  RST_INV <= not RST;
 
 
 
  -- Output buffering
  -------------------------------------
  clkfb <= CLK_OUT2;
 
  BUFG_INST1 : BUFG
  port map
   (O   => CLK_OUT1,
    I   => clkdv);
 
  BUFG_INST2 : BUFG
  port map
   (O   => CLK_OUT2,
    I   => clk0);
 
  BUFG_INST3 : BUFG
  port map
   (O   => CLK_OUT3,
    I   => clkfx);
 
  BUFG_INST4 : BUFG
  port map
   (O   => CLK_OUT3_N,
    I   => clkfx180);
 
  BUFG_INST5 : BUFG
  port map
   (O   => CLK_OUT4,
    I   => clk2x);
 
  ODDR2_INST1 : ODDR2
  generic map(
    DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
    INIT => '0',      -- Sets initial state of the Q output to '0' or '1'
    SRTYPE => "SYNC"
  ) port map (
    Q  => GTXCLK,     -- 1-bit output data
    C0 => CLK_OUT3,   -- 1-bit clock input
    C1 => CLK_OUT3_N, -- 1-bit clock input
    CE => '1',        -- 1-bit clock enable input
    D0 => '1',        -- 1-bit data input (associated with C0)
    D1 => '0',        -- 1-bit data input (associated with C1)
    R  => '0',        -- 1-bit reset input
    S  => '0'         -- 1-bit set input
  );
 
  -- Input buffering
  --------------------------------------
  BUFG_INST6 : IBUFG
  port map
   (O  => RXCLK_BUF,
    I  => RXCLK);
 
  -- DCM
  --------------------------------------
  dcm_sp_inst2: DCM_SP
  generic map
   (CLKDV_DIVIDE          => 2.000,
    CLKFX_DIVIDE          => 4,
    CLKFX_MULTIPLY        => 5,
    CLKIN_DIVIDE_BY_2     => FALSE,
    CLKIN_PERIOD          => 8.0,
    CLKOUT_PHASE_SHIFT    => "FIXED",
    CLK_FEEDBACK          => "1X",
    DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
    PHASE_SHIFT           => 14,
    STARTUP_WAIT          => FALSE)
  port map
   -- Input clock
   (CLKIN                 => RXCLK_BUF,
    CLKFB                 => INTERNAL_RXCLK,
    -- Output clocks
    CLK0                  => INTERNAL_RXCLK_BUF,
    CLK90                 => open,
    CLK180                => open,
    CLK270                => open,
    CLK2X                 => open,
    CLK2X180              => open,
    CLKFX                 => open,
    CLKFX180              => open,
    CLKDV                 => open,
   -- Ports for dynamic phase shift
    PSCLK                 => '0',
    PSEN                  => '0',
    PSINCDEC              => '0',
    PSDONE                => open,
   -- Other control and status signals
    LOCKED                => open,
    STATUS                => open,
    RST                   => RST_INV,
   -- Unused pin, tie low
    DSSEN                 => '0');
 
  -- Output buffering
  --------------------------------------
  BUFG_INST7 : BUFG
  port map
   (O  => INTERNAL_RXCLK,
    I  => INTERNAL_RXCLK_BUF);
 
  LOCKED_INTERNAL <= TX_LOCKED;
 
  -- Use ODDRs for clock/data forwarding
  --------------------------------------
  ODDR2_INST2_GENERATE : for I in 0 to 7 generate
    ODDR2_INST2 : ODDR2
       generic map(
         DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
         INIT => '0',      -- Sets initial state of the Q output to '0' or '1'
         SRTYPE => "SYNC"
       ) port map (
         Q  => TXD(I),          -- 1-bit output data
         C0 => CLK_OUT3,        -- 1-bit clock input
         C1 => CLK_OUT3_N,      -- 1-bit clock input
         CE => '1',             -- 1-bit clock enable input
         D0 => INTERNAL_TXD(I), -- 1-bit data input (associated with C0)
         D1 => INTERNAL_TXD(I), -- 1-bit data input (associated with C1)
         R  => '0',             -- 1-bit reset input
         S  => '0'              -- 1-bit set input
       );
  end generate;
 
  ODDR2_INST3 : ODDR2
  generic map(
    DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
    INIT => '0',      -- Sets initial state of the Q output to '0' or '1'
    SRTYPE => "SYNC"
  ) port map (
    Q  => TXEN,     -- 1-bit output data
    C0 => CLK_OUT3,   -- 1-bit clock input
    C1 => CLK_OUT3_N, -- 1-bit clock input
    CE => '1',        -- 1-bit clock enable input
    D0 => INTERNAL_TXEN,        -- 1-bit data input (associated with C0)
    D1 => INTERNAL_TXEN,        -- 1-bit data input (associated with C1)
    R  => '0',        -- 1-bit reset input
    S  => '0'         -- 1-bit set input
  );
 
  ODDR2_INST4 : ODDR2
  generic map(
    DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
    INIT => '0',      -- Sets initial state of the Q output to '0' or '1'
    SRTYPE => "SYNC"
  ) port map (
    Q  => TXER,     -- 1-bit output data
    C0 => CLK_OUT3,   -- 1-bit clock input
    C1 => CLK_OUT3_N, -- 1-bit clock input
    CE => '1',        -- 1-bit clock enable input
    D0 => INTERNAL_TXER,        -- 1-bit data input (associated with C0)
    D1 => INTERNAL_TXER,        -- 1-bit data input (associated with C1)
    R  => '0',        -- 1-bit reset input
    S  => '0'         -- 1-bit set input
  );
 
 
 
  -- Chips CLK frequency selection
  -------------------------------------
 
  CLK <= CLK_OUT1; --50 MHz
  --CLK <= CLK_OUT2; --100 MHz
  --CLK <= CLK_OUT3; --125 MHz
  --CLK <= CLK_OUT4; --200 MHz
 
end architecture RTL;

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[/] [tcp_socket/] [trunk/] [source/] [atlys.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	jondawson	`--------------------------------------------------------------------------------`
2			`---`
3			`--- CHIPS - 2.0 Simple Web App Demo`
4			`---`
5			`--- :Author: Jonathan P Dawson`
6			`--- :Date: 17/10/2013`
7			`--- :email: chips@jondawson.org.uk`
8			`--- :license: MIT`
9			`--- :Copyright: Copyright (C) Jonathan P Dawson 2013`
10			`---`
11			`--- A Serial Input Component`
12			`---`
13			`--------------------------------------------------------------------------------`
14			`---`
15			`--- +--------------+`
16			`--- \| CLOCK TREE \|`
17			`--- +--------------+`
18			`--- \| >-- CLK1 (50MHz) ---> CLK`
19			`--- CLK_IN >--> \|`
20			`--- \| >-- CLK2 (100MHz)`
21			`--- \| \| +-------+`
22			`--- \| +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]`
23			`--- \| \| \| \|`
24			`--- \| +-- CLK3_N (125MHZ) ->+ \|`
25			`--- \| \| +-------+`
26			`--- RST >-----> >-- CLK4 (200MHz)`
27			`--- \| \|`
28			`--- \| \|`
29			`--- \| \| CLK >--+--------+`
30			`--- \| \| \| \|`
31			`--- \| \| +--v-+ +--v-+`
32			`--- \| \| \| \| \| \|`
33			`--- \| LOCKED >------> >---> >-------> INTERNAL_RESET`
34			`--- \| \| \| \| \| \|`
35			`--- +--------------+ +----+ +----+`
36			`---`
37			`--- +-------------+ +--------------+`
38			`--- \| SERVER \| \| USER DESIGN \|`
39			`--- +-------------+ +--------------+`
40			`--- \| \| \| \|`
41			`--- \| >-----> <-------< SWITCHES`
42			`--- \| \| \| \|`
43			`--- \| <-----< >-------> LEDS`
44			`--- \| \| \| \|`
45			`--- \| \| \| <-------< BUTTONS`
46			`--- \| \| \| \|`
47			`--- \| \| +----^----v----+`
48			`--- \| \| \| \|`
49			`--- \| \| +----^----v----+`
50			`--- \| \| \| UART \|`
51			`--- \| \| +--------------+`
52			`--- \| \| \| >-------> RS232-TX`
53			`--- \| \| \| \|`
54			`--- +---v-----^---+ \| <-------< RS232-RX`
55			`--- \| \| +--------------+`
56			`--- +---v-----^---+`
57			`--- \| ETHERNET \|`
58			`--- \| MAC \|`
59			`--- +-------------+`
60			`--- \| +------> [PHY_RESET]`
61			`--- \| \|`
62			`---[RXCLK] ----->+ +------> [TXCLK]`
63			`--- \| \|`
64			`--- 125MHZ ----->+ +------> open`
65			`--- \| \|`
66			`--- [RXD] ----->+ +------> [TXD]`
67			`--- \| \|`
68			`--- [RXDV] ----->+ +------> [TXEN]`
69			`--- \| \|`
70			`--- [RXER] ----->+ +------> [TXER]`
71			`--- \| \|`
72			`--- \| \|`
73			`--- +-------------+`
74			`---`
75
76			`library ieee;`
77			`use ieee.std_logic_1164.all;`
78			`use ieee.numeric_std.all;`
79
80			`library unisim;`
81			`use unisim.vcomponents.all;`
82
83			`entity ATLYS is`
84			`port(`
85	4	jondawson	`CLK_IN : in std_logic;`
86			`RST : in std_logic;`
87	2	jondawson
88			`--PHY INTERFACE`
89	4	jondawson	`TX : out std_logic;`
90			`RX : in std_logic;`
91			`PHY_RESET : out std_logic;`
92			`RXDV : in std_logic;`
93			`RXER : in std_logic;`
94			`RXCLK : in std_logic;`
95			`RXD : in std_logic_vector(7 downto 0);`
96	2	jondawson	`TXCLK : in std_logic;`
97			`GTXCLK : out std_logic;`
98			`TXD : out std_logic_vector(7 downto 0);`
99			`TXEN : out std_logic;`
100			`TXER : out std_logic;`
101
102			`--LEDS`
103			`GPIO_LEDS : out std_logic_vector(7 downto 0);`
104			`GPIO_SWITCHES : in std_logic_vector(7 downto 0);`
105			`GPIO_BUTTONS : in std_logic_vector(3 downto 0);`
106
107			`--RS232 INTERFACE`
108			`RS232_RX : in std_logic;`
109			`RS232_TX : out std_logic`
110			`);`
111			`end entity ATLYS;`
112
113			`architecture RTL of ATLYS is`
114
115			`component gigabit_ethernet is`
116			`port(`
117			`CLK : in std_logic;`
118			`RST : in std_logic;`
119
120			`--Ethernet Clock`
121			`CLK_125_MHZ : in std_logic;`
122
123			`--GMII IF`
124			`GTXCLK : out std_logic;`
125			`TXCLK : in std_logic;`
126			`TXER : out std_logic;`
127			`TXEN : out std_logic;`
128			`TXD : out std_logic_vector(7 downto 0);`
129			`PHY_RESET : out std_logic;`
130			`RXCLK : in std_logic;`
131			`RXER : in std_logic;`
132			`RXDV : in std_logic;`
133			`RXD : in std_logic_vector(7 downto 0);`
134
135			`--RX STREAM`
136			`TX : in std_logic_vector(15 downto 0);`
137			`TX_STB : in std_logic;`
138			`TX_ACK : out std_logic;`
139
140			`--RX STREAM`
141			`RX : out std_logic_vector(15 downto 0);`
142			`RX_STB : out std_logic;`
143			`RX_ACK : in std_logic`
144			`);`
145			`end component gigabit_ethernet;`
146
147			`component SERVER is`
148			`port(`
149			`CLK : in std_logic;`
150			`RST : in std_logic;`
151	4	jondawson
152	2	jondawson	`--ETH RX STREAM`
153			`INPUT_ETH_RX : in std_logic_vector(15 downto 0);`
154			`INPUT_ETH_RX_STB : in std_logic;`
155			`INPUT_ETH_RX_ACK : out std_logic;`
156
157			`--ETH TX STREAM`
158			`output_eth_tx : out std_logic_vector(15 downto 0);`
159			`OUTPUT_ETH_TX_STB : out std_logic;`
160			`OUTPUT_ETH_TX_ACK : in std_logic;`
161
162			`--SOCKET RX STREAM`
163			`INPUT_SOCKET : in std_logic_vector(15 downto 0);`
164			`INPUT_SOCKET_STB : in std_logic;`
165			`INPUT_SOCKET_ACK : out std_logic;`
166
167			`--SOCKET TX STREAM`
168			`OUTPUT_SOCKET : out std_logic_vector(15 downto 0);`
169			`OUTPUT_SOCKET_STB : out std_logic;`
170			`OUTPUT_SOCKET_ACK : in std_logic`
171
172			`);`
173			`end component;`
174
175			`component USER_DESIGN is`
176			`port(`
177			`CLK : in std_logic;`
178			`RST : in std_logic;`
179	4	jondawson
180	2	jondawson	`OUTPUT_LEDS : out std_logic_vector(15 downto 0);`
181			`OUTPUT_LEDS_STB : out std_logic;`
182			`OUTPUT_LEDS_ACK : in std_logic;`
183
184			`INPUT_SWITCHES : in std_logic_vector(15 downto 0);`
185			`INPUT_SWITCHES_STB : in std_logic;`
186			`INPUT_SWITCHES_ACK : out std_logic;`
187
188			`INPUT_BUTTONS : in std_logic_vector(15 downto 0);`
189			`INPUT_BUTTONS_STB : in std_logic;`
190			`INPUT_BUTTONS_ACK : out std_logic;`
191
192			`--SOCKET RX STREAM`
193			`INPUT_SOCKET : in std_logic_vector(15 downto 0);`
194			`INPUT_SOCKET_STB : in std_logic;`
195			`INPUT_SOCKET_ACK : out std_logic;`
196
197			`--SOCKET TX STREAM`
198			`OUTPUT_SOCKET : out std_logic_vector(15 downto 0);`
199			`OUTPUT_SOCKET_STB : out std_logic;`
200			`OUTPUT_SOCKET_ACK : in std_logic;`
201
202			`--RS232 RX STREAM`
203			`INPUT_RS232_RX : in std_logic_vector(15 downto 0);`
204			`INPUT_RS232_RX_STB : in std_logic;`
205			`INPUT_RS232_RX_ACK : out std_logic;`
206
207			`--RS232 TX STREAM`
208			`OUTPUT_RS232_TX : out std_logic_vector(15 downto 0);`
209			`OUTPUT_RS232_TX_STB : out std_logic;`
210			`OUTPUT_RS232_TX_ACK : in std_logic`
211
212
213			`);`
214			`end component;`
215
216			`component SERIAL_INPUT is`
217			`generic(`
218			`CLOCK_FREQUENCY : integer;`
219			`BAUD_RATE : integer`
220			`);`
221			`port(`
222			`CLK : in std_logic;`
223			`RST : in std_logic;`
224			`RX : in std_logic;`
225
226			`OUT1 : out std_logic_vector(7 downto 0);`
227			`OUT1_STB : out std_logic;`
228			`OUT1_ACK : in std_logic`
229			`);`
230			`end component SERIAL_INPUT;`
231
232			`component serial_output is`
233			`generic(`
234			`CLOCK_FREQUENCY : integer;`
235			`BAUD_RATE : integer`
236			`);`
237			`port(`
238			`CLK : in std_logic;`
239			`RST : in std_logic;`
240			`TX : out std_logic;`
241
242			`IN1 : in std_logic_vector(7 downto 0);`
243			`IN1_STB : in std_logic;`
244			`IN1_ACK : out std_logic`
245			`);`
246			`end component serial_output;`
247
248			`--chips signals`
249			`signal CLK : std_logic;`
250			`signal RST_INV : std_logic;`
251
252			`--clock tree signals`
253			`signal clkin1 : std_logic;`
254			`-- Output clock buffering`
255			`signal clkfb : std_logic;`
256			`signal clk0 : std_logic;`
257			`signal clk2x : std_logic;`
258			`signal clkfx : std_logic;`
259			`signal clkfx180 : std_logic;`
260			`signal clkdv : std_logic;`
261			`signal clkfbout : std_logic;`
262			`signal locked_internal : std_logic;`
263			`signal status_internal : std_logic_vector(7 downto 0);`
264			`signal CLK_OUT1 : std_logic;`
265			`signal CLK_OUT2 : std_logic;`
266			`signal CLK_OUT3 : std_logic;`
267			`signal CLK_OUT3_N : std_logic;`
268			`signal CLK_OUT4 : std_logic;`
269			`signal NOT_LOCKED : std_logic;`
270			`signal INTERNAL_RST : std_logic;`
271			`signal RXD1 : std_logic;`
272			`signal TX_LOCKED : std_logic;`
273			`signal INTERNAL_RXCLK : std_logic;`
274			`signal INTERNAL_RXCLK_BUF: std_logic;`
275			`signal RXCLK_BUF : std_logic;`
276
277			`signal INTERNAL_TXD : std_logic_vector(7 downto 0);`
278			`signal INTERNAL_TXEN : std_logic;`
279			`signal INTERNAL_TXER : std_logic;`
280
281			`signal OUTPUT_LEDS : std_logic_vector(15 downto 0);`
282			`signal OUTPUT_LEDS_STB : std_logic;`
283			`signal OUTPUT_LEDS_ACK : std_logic;`
284
285			`signal INPUT_SWITCHES : std_logic_vector(15 downto 0);`
286			`signal INPUT_SWITCHES_STB : std_logic;`
287			`signal INPUT_SWITCHES_ACK : std_logic;`
288			`signal GPIO_SWITCHES_D : std_logic_vector(7 downto 0);`
289
290			`signal INPUT_BUTTONS : std_logic_vector(15 downto 0);`
291			`signal INPUT_BUTTONS_STB : std_logic;`
292			`signal INPUT_BUTTONS_ACK : std_logic;`
293			`signal GPIO_BUTTONS_D : std_logic_vector(3 downto 0);`
294
295			`--ETH RX STREAM`
296			`signal ETH_RX : std_logic_vector(15 downto 0);`
297			`signal ETH_RX_STB : std_logic;`
298			`signal ETH_RX_ACK : std_logic;`
299
300			`--ETH TX STREAM`
301			`signal ETH_TX : std_logic_vector(15 downto 0);`
302			`signal ETH_TX_STB : std_logic;`
303			`signal ETH_TX_ACK : std_logic;`
304
305			`--RS232 RX STREAM`
306			`signal INPUT_RS232_RX : std_logic_vector(15 downto 0);`
307			`signal INPUT_RS232_RX_STB : std_logic;`
308			`signal INPUT_RS232_RX_ACK : std_logic;`
309
310			`--RS232 TX STREAM`
311			`signal OUTPUT_RS232_TX : std_logic_vector(15 downto 0);`
312			`signal OUTPUT_RS232_TX_STB : std_logic;`
313			`signal OUTPUT_RS232_TX_ACK : std_logic;`
314
315			`--SOCKET RX STREAM`
316			`signal INPUT_SOCKET : std_logic_vector(15 downto 0);`
317			`signal INPUT_SOCKET_STB : std_logic;`
318			`signal INPUT_SOCKET_ACK : std_logic;`
319
320			`--SOCKET TX STREAM`
321			`signal OUTPUT_SOCKET : std_logic_vector(15 downto 0);`
322			`signal OUTPUT_SOCKET_STB : std_logic;`
323			`signal OUTPUT_SOCKET_ACK : std_logic;`
324
325			`begin`
326
327			`gigabit_ethernet_inst_1 : gigabit_ethernet port map(`
328			`CLK => CLK,`
329			`RST => INTERNAL_RST,`
330
331			`--Ethernet Clock`
332			`CLK_125_MHZ => CLK_OUT3,`
333
334			`--GMII IF`
335			`GTXCLK => open,`
336			`TXCLK => TXCLK,`
337			`TXER => INTERNAL_TXER,`
338			`TXEN => INTERNAL_TXEN,`
339			`TXD => INTERNAL_TXD,`
340			`PHY_RESET => PHY_RESET,`
341			`RXCLK => INTERNAL_RXCLK,`
342			`RXER => RXER,`
343			`RXDV => RXDV,`
344			`RXD => RXD,`
345
346			`--RX STREAM`
347			`TX => ETH_TX,`
348			`TX_STB => ETH_TX_STB,`
349			`TX_ACK => ETH_TX_ACK,`
350
351			`--RX STREAM`
352			`RX => ETH_RX,`
353			`RX_STB => ETH_RX_STB,`
354			`RX_ACK => ETH_RX_ACK`
355			`);`
356
357			`SERVER_INST_1 : SERVER port map(`
358			`CLK => CLK,`
359			`RST => INTERNAL_RST,`
360	4	jondawson
361	2	jondawson	`--ETH RX STREAM`
362			`INPUT_ETH_RX => ETH_RX,`
363			`INPUT_ETH_RX_STB => ETH_RX_STB,`
364			`INPUT_ETH_RX_ACK => ETH_RX_ACK,`
365
366			`--ETH TX STREAM`
367			`OUTPUT_ETH_TX => ETH_TX,`
368			`OUTPUT_ETH_TX_STB => ETH_TX_STB,`
369			`OUTPUT_ETH_TX_ACK => ETH_TX_ACK,`
370
371			`--SOCKET STREAM`
372			`INPUT_SOCKET => INPUT_SOCKET,`
373			`INPUT_SOCKET_STB => INPUT_SOCKET_STB,`
374			`INPUT_SOCKET_ACK => INPUT_SOCKET_ACK,`
375
376			`--SOCKET STREAM`
377			`OUTPUT_SOCKET => OUTPUT_SOCKET,`
378			`OUTPUT_SOCKET_STB => OUTPUT_SOCKET_STB,`
379			`OUTPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK`
380
381			`);`
382
383			`USER_DESIGN_INST_1 : USER_DESIGN port map(`
384			`CLK => CLK,`
385			`RST => INTERNAL_RST,`
386	4	jondawson
387	2	jondawson	`OUTPUT_LEDS => OUTPUT_LEDS,`
388			`OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,`
389			`OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,`
390
391			`INPUT_SWITCHES => INPUT_SWITCHES,`
392			`INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,`
393			`INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,`
394
395			`INPUT_BUTTONS => INPUT_BUTTONS,`
396			`INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,`
397			`INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,`
398
399			`--RS232 RX STREAM`
400			`INPUT_RS232_RX => INPUT_RS232_RX,`
401			`INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,`
402			`INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,`
403
404			`--RS232 TX STREAM`
405			`OUTPUT_RS232_TX => OUTPUT_RS232_TX,`
406			`OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,`
407			`OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,`
408
409			`--SOCKET STREAM`
410			`INPUT_SOCKET => OUTPUT_SOCKET,`
411			`INPUT_SOCKET_STB => OUTPUT_SOCKET_STB,`
412			`INPUT_SOCKET_ACK => OUTPUT_SOCKET_ACK,`
413
414			`--SOCKET STREAM`
415			`OUTPUT_SOCKET => INPUT_SOCKET,`
416			`OUTPUT_SOCKET_STB => INPUT_SOCKET_STB,`
417			`OUTPUT_SOCKET_ACK => INPUT_SOCKET_ACK`
418
419			`);`
420
421			`SERIAL_OUTPUT_INST_1 : serial_output generic map(`
422			`CLOCK_FREQUENCY => 50000000,`
423			`BAUD_RATE => 115200`
424			`)port map(`
425			`CLK => CLK,`
426			`RST => INTERNAL_RST,`
427			`TX => RS232_TX,`
428
429			`IN1 => OUTPUT_RS232_TX(7 downto 0),`
430			`IN1_STB => OUTPUT_RS232_TX_STB,`
431			`IN1_ACK => OUTPUT_RS232_TX_ACK`
432			`);`
433
434			`SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(`
435			`CLOCK_FREQUENCY => 50000000,`
436			`BAUD_RATE => 115200`
437			`) port map (`
438			`CLK => CLK,`
439			`RST => INTERNAL_RST,`
440			`RX => RS232_RX,`
441
442			`OUT1 => INPUT_RS232_RX(7 downto 0),`
443			`OUT1_STB => INPUT_RS232_RX_STB,`
444			`OUT1_ACK => INPUT_RS232_RX_ACK`
445			`);`
446
447			`INPUT_RS232_RX(15 downto 8) <= (others => '0');`
448
449			`process`
450			`begin`
451			`wait until rising_edge(CLK);`
452			`NOT_LOCKED <= not LOCKED_INTERNAL;`
453			`INTERNAL_RST <= NOT_LOCKED;`
454	4	jondawson
455	2	jondawson	`if OUTPUT_LEDS_STB = '1' then`
456	4	jondawson	`GPIO_LEDS <= OUTPUT_LEDS(7 downto 0);`
457	2	jondawson	`end if;`
458	4	jondawson	`OUTPUT_LEDS_ACK <= '1';`
459	2	jondawson
460			`INPUT_SWITCHES_STB <= '1';`
461			`GPIO_SWITCHES_D <= GPIO_SWITCHES;`
462			`INPUT_SWITCHES(7 downto 0) <= GPIO_SWITCHES_D;`
463			`INPUT_SWITCHES(15 downto 8) <= (others => '0');`
464
465			`INPUT_BUTTONS_STB <= '1';`
466			`GPIO_BUTTONS_D <= GPIO_BUTTONS;`
467			`INPUT_BUTTONS(3 downto 0) <= GPIO_BUTTONS_D;`
468			`INPUT_BUTTONS(15 downto 4) <= (others => '0');`
469
470			`end process;`
471
472
473			`-------------------------`
474			`-- Output Output`
475			`-- Clock Freq (MHz)`
476			`-------------------------`
477			`-- CLK_OUT1 50.000`
478			`-- CLK_OUT2 100.000`
479			`-- CLK_OUT3 125.000`
480			`-- CLK_OUT4 200.000`
481
482			`----------------------------------`
483			`-- Input Clock Input Freq (MHz)`
484			`----------------------------------`
485			`-- primary 200.000`
486
487
488			`-- Input buffering`
489			`--------------------------------------`
490			`clkin1_buf : IBUFG`
491			`port map`
492			`(O => clkin1,`
493			`I => CLK_IN);`
494
495
496			`-- Clocking primitive`
497			`--------------------------------------`
498			`-- Instantiation of the DCM primitive`
499			`-- * Unused inputs are tied off`
500			`-- * Unused outputs are labeled unused`
501			`dcm_sp_inst: DCM_SP`
502			`generic map`
503			`(CLKDV_DIVIDE => 2.000,`
504			`CLKFX_DIVIDE => 4,`
505			`CLKFX_MULTIPLY => 5,`
506			`CLKIN_DIVIDE_BY_2 => FALSE,`
507			`CLKIN_PERIOD => 10.0,`
508			`CLKOUT_PHASE_SHIFT => "NONE",`
509			`CLK_FEEDBACK => "1X",`
510			`DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",`
511			`PHASE_SHIFT => 0,`
512			`STARTUP_WAIT => FALSE)`
513			`port map`
514			`-- Input clock`
515			`(CLKIN => clkin1,`
516			`CLKFB => clkfb,`
517			`-- Output clocks`
518			`CLK0 => clk0,`
519			`CLK90 => open,`
520			`CLK180 => open,`
521			`CLK270 => open,`
522			`CLK2X => clk2x,`
523			`CLK2X180 => open,`
524			`CLKFX => clkfx,`
525			`CLKFX180 => clkfx180,`
526			`CLKDV => clkdv,`
527			`-- Ports for dynamic phase shift`
528			`PSCLK => '0',`
529			`PSEN => '0',`
530			`PSINCDEC => '0',`
531			`PSDONE => open,`
532			`-- Other control and status signals`
533			`LOCKED => TX_LOCKED,`
534			`STATUS => status_internal,`
535			`RST => RST_INV,`
536			`-- Unused pin, tie low`
537			`DSSEN => '0');`
538
539			`RST_INV <= not RST;`
540
541
542
543			`-- Output buffering`
544			`-------------------------------------`
545			`clkfb <= CLK_OUT2;`
546
547			`BUFG_INST1 : BUFG`
548			`port map`
549			`(O => CLK_OUT1,`
550			`I => clkdv);`
551
552			`BUFG_INST2 : BUFG`
553			`port map`
554			`(O => CLK_OUT2,`
555			`I => clk0);`
556
557			`BUFG_INST3 : BUFG`
558			`port map`
559			`(O => CLK_OUT3,`
560			`I => clkfx);`
561
562			`BUFG_INST4 : BUFG`
563			`port map`
564			`(O => CLK_OUT3_N,`
565			`I => clkfx180);`
566
567			`BUFG_INST5 : BUFG`
568			`port map`
569			`(O => CLK_OUT4,`
570			`I => clk2x);`
571
572			`ODDR2_INST1 : ODDR2`
573			`generic map(`
574			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
575			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
576			`SRTYPE => "SYNC"`
577			`) port map (`
578			`Q => GTXCLK, -- 1-bit output data`
579			`C0 => CLK_OUT3, -- 1-bit clock input`
580			`C1 => CLK_OUT3_N, -- 1-bit clock input`
581			`CE => '1', -- 1-bit clock enable input`
582			`D0 => '1', -- 1-bit data input (associated with C0)`
583			`D1 => '0', -- 1-bit data input (associated with C1)`
584			`R => '0', -- 1-bit reset input`
585			`S => '0' -- 1-bit set input`
586			`);`
587
588			`-- Input buffering`
589			`--------------------------------------`
590			`BUFG_INST6 : IBUFG`
591			`port map`
592			`(O => RXCLK_BUF,`
593			`I => RXCLK);`
594
595			`-- DCM`
596			`--------------------------------------`
597			`dcm_sp_inst2: DCM_SP`
598			`generic map`
599			`(CLKDV_DIVIDE => 2.000,`
600			`CLKFX_DIVIDE => 4,`
601			`CLKFX_MULTIPLY => 5,`
602			`CLKIN_DIVIDE_BY_2 => FALSE,`
603			`CLKIN_PERIOD => 8.0,`
604			`CLKOUT_PHASE_SHIFT => "FIXED",`
605			`CLK_FEEDBACK => "1X",`
606			`DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",`
607			`PHASE_SHIFT => 14,`
608			`STARTUP_WAIT => FALSE)`
609			`port map`
610			`-- Input clock`
611			`(CLKIN => RXCLK_BUF,`
612			`CLKFB => INTERNAL_RXCLK,`
613			`-- Output clocks`
614			`CLK0 => INTERNAL_RXCLK_BUF,`
615			`CLK90 => open,`
616			`CLK180 => open,`
617			`CLK270 => open,`
618			`CLK2X => open,`
619			`CLK2X180 => open,`
620			`CLKFX => open,`
621			`CLKFX180 => open,`
622			`CLKDV => open,`
623			`-- Ports for dynamic phase shift`
624			`PSCLK => '0',`
625			`PSEN => '0',`
626			`PSINCDEC => '0',`
627			`PSDONE => open,`
628			`-- Other control and status signals`
629			`LOCKED => open,`
630			`STATUS => open,`
631			`RST => RST_INV,`
632			`-- Unused pin, tie low`
633			`DSSEN => '0');`
634
635			`-- Output buffering`
636			`--------------------------------------`
637			`BUFG_INST7 : BUFG`
638			`port map`
639			`(O => INTERNAL_RXCLK,`
640			`I => INTERNAL_RXCLK_BUF);`
641
642			`LOCKED_INTERNAL <= TX_LOCKED;`
643
644			`-- Use ODDRs for clock/data forwarding`
645			`--------------------------------------`
646			`ODDR2_INST2_GENERATE : for I in 0 to 7 generate`
647			`ODDR2_INST2 : ODDR2`
648			`generic map(`
649			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
650			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
651			`SRTYPE => "SYNC"`
652			`) port map (`
653			`Q => TXD(I), -- 1-bit output data`
654			`C0 => CLK_OUT3, -- 1-bit clock input`
655			`C1 => CLK_OUT3_N, -- 1-bit clock input`
656			`CE => '1', -- 1-bit clock enable input`
657			`D0 => INTERNAL_TXD(I), -- 1-bit data input (associated with C0)`
658			`D1 => INTERNAL_TXD(I), -- 1-bit data input (associated with C1)`
659			`R => '0', -- 1-bit reset input`
660			`S => '0' -- 1-bit set input`
661			`);`
662			`end generate;`
663
664			`ODDR2_INST3 : ODDR2`
665			`generic map(`
666			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
667			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
668			`SRTYPE => "SYNC"`
669			`) port map (`
670			`Q => TXEN, -- 1-bit output data`
671			`C0 => CLK_OUT3, -- 1-bit clock input`
672			`C1 => CLK_OUT3_N, -- 1-bit clock input`
673			`CE => '1', -- 1-bit clock enable input`
674			`D0 => INTERNAL_TXEN, -- 1-bit data input (associated with C0)`
675			`D1 => INTERNAL_TXEN, -- 1-bit data input (associated with C1)`
676			`R => '0', -- 1-bit reset input`
677			`S => '0' -- 1-bit set input`
678			`);`
679
680			`ODDR2_INST4 : ODDR2`
681			`generic map(`
682			`DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"`
683			`INIT => '0', -- Sets initial state of the Q output to '0' or '1'`
684			`SRTYPE => "SYNC"`
685			`) port map (`
686			`Q => TXER, -- 1-bit output data`
687			`C0 => CLK_OUT3, -- 1-bit clock input`
688			`C1 => CLK_OUT3_N, -- 1-bit clock input`
689			`CE => '1', -- 1-bit clock enable input`
690			`D0 => INTERNAL_TXER, -- 1-bit data input (associated with C0)`
691			`D1 => INTERNAL_TXER, -- 1-bit data input (associated with C1)`
692			`R => '0', -- 1-bit reset input`
693			`S => '0' -- 1-bit set input`
694			`);`
695
696
697
698			`-- Chips CLK frequency selection`
699			`-------------------------------------`
700
701			`CLK <= CLK_OUT1; --50 MHz`
702			`--CLK <= CLK_OUT2; --100 MHz`
703			`--CLK <= CLK_OUT3; --125 MHz`
704			`--CLK <= CLK_OUT4; --200 MHz`
705
706			`end architecture RTL;`