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[/] [tcp_socket/] [trunk/] [source/] [serial_in.vhd] - Blame information for rev 2

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--------------------------------------------------------------------------------
---
---  SERIAL INPUT
---
---  :Author: Jonathan P Dawson
---  :Date: 17/10/2013
---  :email: chips@jondawson.org.uk
---  :license: MIT
---  :Copyright: Copyright (C) Jonathan P Dawson 2013
---
---  A Serial Input Component
---
--------------------------------------------------------------------------------
---
---Serial Input
---============
---
---Read a stream of data from a serial UART
---
---Outputs
-----------
---
--- + OUT1 : Serial data stream
---
---Generics
-----------
---
--- + baud_rate
--- + clock frequency
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity SERIAL_INPUT is
 
  generic(
    CLOCK_FREQUENCY : integer;
    BAUD_RATE       : integer
  );
  port(
    CLK      : in std_logic;
    RST      : in std_logic;
    RX       : in std_logic;
 
    OUT1     : out std_logic_vector(7 downto 0);
    OUT1_STB : out std_logic;
    OUT1_ACK : in  std_logic
  );
 
end entity SERIAL_INPUT;
 
architecture RTL of SERIAL_INPUT is
 
  type SERIAL_IN_STATE_TYPE is (IDLE, START, RX0, RX1, RX2, RX3, RX4, RX5, RX6, RX7, STOP, OUTPUT_DATA);
  signal STATE           : SERIAL_IN_STATE_TYPE;
  signal STREAM          : std_logic_vector(7 downto 0);
  signal STREAM_STB      : std_logic;
  signal STREAM_ACK      : std_logic;
  signal COUNT           : integer Range 0 to 3;
  signal BIT_SPACING     : integer Range 0 to 15;
  signal INT_SERIAL      : std_logic;
  signal SERIAL_DEGLITCH : std_logic_Vector(1 downto 0);
  constant CLOCK_DIVIDER : unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/(BAUD_RATE * 16), 12);
  signal BAUD_COUNT      : unsigned(11 downto 0);
  signal X16CLK_EN       : std_logic;
 
begin
 
  process
  begin
    wait until rising_edge(CLK);
    if BAUD_COUNT = CLOCK_DIVIDER then
      BAUD_COUNT <= (others => '0');
      X16CLK_EN  <= '1';
    else
      BAUD_COUNT <= BAUD_COUNT + 1;
      X16CLK_EN  <= '0';
    end if;
    if RST = '1' then
      BAUD_COUNT <= (others => '0');
      X16CLK_EN  <= '0';
    end if;
  end process;
 
  process
  begin
    wait until rising_edge(CLK);
    SERIAL_DEGLITCH <= SERIAL_DEGLITCH(0) & RX;
    if X16CLK_EN = '1' then
      if SERIAL_DEGLITCH(1) = '0' then
        if COUNT = 0 then
          INT_SERIAL <= '0';
        else
          COUNT <= COUNT - 1;
        end if;
      else
        if COUNT = 3 then
          INT_SERIAL <= '1';
        else
          COUNT <= COUNT + 1;
        end if;
      end if;
    end if;
    if RST = '1' then
      SERIAL_DEGLITCH <= "11";
    end if;
  end process;
 
  process
  begin
    wait until rising_edge(CLK);
         if X16CLK_EN = '1' then
      if BIT_SPACING = 15 then
        BIT_SPACING <= 0;
      else
        BIT_SPACING <= BIT_SPACING + 1;
      end if;
    end if;
    case STATE is
      when IDLE =>
        BIT_SPACING <= 0;
        if X16CLK_EN = '1' and INT_SERIAL = '0' then
          STATE <= START;
        end if;
      when START =>
        if X16CLK_EN = '1' and BIT_SPACING = 7 then
          BIT_SPACING <= 0;
          STATE <= RX0;
        end if;
      when RX0 =>
        if X16CLK_EN = '1' and BIT_SPACING = 15 then
          OUT1(0) <= INT_SERIAL;
          BIT_SPACING <= 0;
          STATE <= RX1;
        end if;
      when RX1 =>
        if X16CLK_EN = '1' and BIT_SPACING = 15 then
          OUT1(1) <= INT_SERIAL;
          BIT_SPACING <= 0;
          STATE <= RX2;
        end if;
      when RX2 =>
        if X16CLK_EN = '1' and BIT_SPACING = 15 then
          OUT1(2) <= INT_SERIAL;
          BIT_SPACING <= 0;
          STATE <= RX3;
        end if;
      when RX3 =>
        if X16CLK_EN = '1' and BIT_SPACING = 15 then
          OUT1(3) <= INT_SERIAL;
          BIT_SPACING <= 0;
          STATE <= RX4;
        end if;
      when RX4 =>
        if X16CLK_EN = '1' and BIT_SPACING = 15 then
          OUT1(4) <= INT_SERIAL;
          BIT_SPACING <= 0;
          STATE <= RX5;
        end if;
      when RX5 =>
        if X16CLK_EN = '1' and BIT_SPACING = 15 then
          OUT1(5) <= INT_SERIAL;
          BIT_SPACING <= 0;
          STATE <= RX6;
        end if;
      when RX6 =>
        if X16CLK_EN = '1' and BIT_SPACING = 15 then
          OUT1(6) <= INT_SERIAL;
          BIT_SPACING <= 0;
          STATE <= RX7;
        end if;
      when RX7 =>
        if X16CLK_EN = '1' and BIT_SPACING = 15 then
          OUT1(7) <= INT_SERIAL;
          BIT_SPACING <= 0;
          STATE <= STOP;
        end if;
      when STOP =>
        if X16CLK_EN = '1' and BIT_SPACING = 15 then
            BIT_SPACING <= 0;
            STATE <= OUTPUT_DATA;
            OUT1_STB <= '1';
        end if;
      when OUTPUT_DATA =>
          if OUT1_ACK = '1' then
            OUT1_STB <= '0';
            STATE <= IDLE;
          end if;
      when others =>
        STATE <= IDLE;
    end case;
    if RST = '1' then
      STATE <= IDLE;
      OUT1_STB <= '0';
    end if;
  end process;
end architecture RTL;

Line No.	Rev	Author	Line
1	2	jondawson	`--------------------------------------------------------------------------------`
2			`---`
3			`--- SERIAL INPUT`
4			`---`
5			`--- :Author: Jonathan P Dawson`
6			`--- :Date: 17/10/2013`
7			`--- :email: chips@jondawson.org.uk`
8			`--- :license: MIT`
9			`--- :Copyright: Copyright (C) Jonathan P Dawson 2013`
10			`---`
11			`--- A Serial Input Component`
12			`---`
13			`--------------------------------------------------------------------------------`
14			`---`
15			`---Serial Input`
16			`---============`
17			`---`
18			`---Read a stream of data from a serial UART`
19			`---`
20			`---Outputs`
21			`-----------`
22			`---`
23			`--- + OUT1 : Serial data stream`
24			`---`
25			`---Generics`
26			`-----------`
27			`---`
28			`--- + baud_rate`
29			`--- + clock frequency`
30
31			`library ieee;`
32			`use ieee.std_logic_1164.all;`
33			`use ieee.numeric_std.all;`
34
35			`entity SERIAL_INPUT is`
36
37			`generic(`
38			`CLOCK_FREQUENCY : integer;`
39			`BAUD_RATE : integer`
40			`);`
41			`port(`
42			`CLK : in std_logic;`
43			`RST : in std_logic;`
44			`RX : in std_logic;`
45
46			`OUT1 : out std_logic_vector(7 downto 0);`
47			`OUT1_STB : out std_logic;`
48			`OUT1_ACK : in std_logic`
49			`);`
50
51			`end entity SERIAL_INPUT;`
52
53			`architecture RTL of SERIAL_INPUT is`
54
55			`type SERIAL_IN_STATE_TYPE is (IDLE, START, RX0, RX1, RX2, RX3, RX4, RX5, RX6, RX7, STOP, OUTPUT_DATA);`
56			`signal STATE : SERIAL_IN_STATE_TYPE;`
57			`signal STREAM : std_logic_vector(7 downto 0);`
58			`signal STREAM_STB : std_logic;`
59			`signal STREAM_ACK : std_logic;`
60			`signal COUNT : integer Range 0 to 3;`
61			`signal BIT_SPACING : integer Range 0 to 15;`
62			`signal INT_SERIAL : std_logic;`
63			`signal SERIAL_DEGLITCH : std_logic_Vector(1 downto 0);`
64			`constant CLOCK_DIVIDER : unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/(BAUD_RATE * 16), 12);`
65			`signal BAUD_COUNT : unsigned(11 downto 0);`
66			`signal X16CLK_EN : std_logic;`
67
68			`begin`
69
70			`process`
71			`begin`
72			`wait until rising_edge(CLK);`
73			`if BAUD_COUNT = CLOCK_DIVIDER then`
74			`BAUD_COUNT <= (others => '0');`
75			`X16CLK_EN <= '1';`
76			`else`
77			`BAUD_COUNT <= BAUD_COUNT + 1;`
78			`X16CLK_EN <= '0';`
79			`end if;`
80			`if RST = '1' then`
81			`BAUD_COUNT <= (others => '0');`
82			`X16CLK_EN <= '0';`
83			`end if;`
84			`end process;`
85
86			`process`
87			`begin`
88			`wait until rising_edge(CLK);`
89			`SERIAL_DEGLITCH <= SERIAL_DEGLITCH(0) & RX;`
90			`if X16CLK_EN = '1' then`
91			`if SERIAL_DEGLITCH(1) = '0' then`
92			`if COUNT = 0 then`
93			`INT_SERIAL <= '0';`
94			`else`
95			`COUNT <= COUNT - 1;`
96			`end if;`
97			`else`
98			`if COUNT = 3 then`
99			`INT_SERIAL <= '1';`
100			`else`
101			`COUNT <= COUNT + 1;`
102			`end if;`
103			`end if;`
104			`end if;`
105			`if RST = '1' then`
106			`SERIAL_DEGLITCH <= "11";`
107			`end if;`
108			`end process;`
109
110			`process`
111			`begin`
112			`wait until rising_edge(CLK);`
113			`if X16CLK_EN = '1' then`
114			`if BIT_SPACING = 15 then`
115			`BIT_SPACING <= 0;`
116			`else`
117			`BIT_SPACING <= BIT_SPACING + 1;`
118			`end if;`
119			`end if;`
120			`case STATE is`
121			`when IDLE =>`
122			`BIT_SPACING <= 0;`
123			`if X16CLK_EN = '1' and INT_SERIAL = '0' then`
124			`STATE <= START;`
125			`end if;`
126			`when START =>`
127			`if X16CLK_EN = '1' and BIT_SPACING = 7 then`
128			`BIT_SPACING <= 0;`
129			`STATE <= RX0;`
130			`end if;`
131			`when RX0 =>`
132			`if X16CLK_EN = '1' and BIT_SPACING = 15 then`
133			`OUT1(0) <= INT_SERIAL;`
134			`BIT_SPACING <= 0;`
135			`STATE <= RX1;`
136			`end if;`
137			`when RX1 =>`
138			`if X16CLK_EN = '1' and BIT_SPACING = 15 then`
139			`OUT1(1) <= INT_SERIAL;`
140			`BIT_SPACING <= 0;`
141			`STATE <= RX2;`
142			`end if;`
143			`when RX2 =>`
144			`if X16CLK_EN = '1' and BIT_SPACING = 15 then`
145			`OUT1(2) <= INT_SERIAL;`
146			`BIT_SPACING <= 0;`
147			`STATE <= RX3;`
148			`end if;`
149			`when RX3 =>`
150			`if X16CLK_EN = '1' and BIT_SPACING = 15 then`
151			`OUT1(3) <= INT_SERIAL;`
152			`BIT_SPACING <= 0;`
153			`STATE <= RX4;`
154			`end if;`
155			`when RX4 =>`
156			`if X16CLK_EN = '1' and BIT_SPACING = 15 then`
157			`OUT1(4) <= INT_SERIAL;`
158			`BIT_SPACING <= 0;`
159			`STATE <= RX5;`
160			`end if;`
161			`when RX5 =>`
162			`if X16CLK_EN = '1' and BIT_SPACING = 15 then`
163			`OUT1(5) <= INT_SERIAL;`
164			`BIT_SPACING <= 0;`
165			`STATE <= RX6;`
166			`end if;`
167			`when RX6 =>`
168			`if X16CLK_EN = '1' and BIT_SPACING = 15 then`
169			`OUT1(6) <= INT_SERIAL;`
170			`BIT_SPACING <= 0;`
171			`STATE <= RX7;`
172			`end if;`
173			`when RX7 =>`
174			`if X16CLK_EN = '1' and BIT_SPACING = 15 then`
175			`OUT1(7) <= INT_SERIAL;`
176			`BIT_SPACING <= 0;`
177			`STATE <= STOP;`
178			`end if;`
179			`when STOP =>`
180			`if X16CLK_EN = '1' and BIT_SPACING = 15 then`
181			`BIT_SPACING <= 0;`
182			`STATE <= OUTPUT_DATA;`
183			`OUT1_STB <= '1';`
184			`end if;`
185			`when OUTPUT_DATA =>`
186			`if OUT1_ACK = '1' then`
187			`OUT1_STB <= '0';`
188			`STATE <= IDLE;`
189			`end if;`
190			`when others =>`
191			`STATE <= IDLE;`
192			`end case;`
193			`if RST = '1' then`
194			`STATE <= IDLE;`
195			`OUT1_STB <= '0';`
196			`end if;`
197			`end process;`
198			`end architecture RTL;`

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[/] [tcp_socket/] [trunk/] [source/] [serial_in.vhd] - Blame information for rev 2