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[/] [tdm_switch/] [web_uploads/] [tdm_switch_top_timesim.v] - Blame information for rev 6

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1 6 root 
// Xilinx Verilog produced by program ngd2ver F.28
2 
// Command: -quiet -gp GSR -tp GTS -w -log __projnav/ngd2ver.log tdm_switch_top.nga tdm_switch_top_timesim.v
3 
// Input file: tdm_switch_top.nga
4 
// Output file: tdm_switch_top_timesim.v
5 
// Design name: tdm_switch_top
6 
// Xilinx: E:/Xilinx
7 
// # of Entities: 1
8 
// Device: 2s50tq144-6 (PRODUCTION 1.27 2002-12-13)
9 
 
10 
// The output of ngd2ver is a simulation model. This netlist uses simulation
11 
// primitives which may not represent the true implementation of the device,
12 
// however the netlist is functionally correct and should not be modified.
13 
// This file cannot be synthesized and should only be used with supported
14 
// simulation, static timing analysis and formal verification software tools.
15 
// Please refer to the documentation on using third party static timing analysis
16 
// and formal verification software to use the netlist for that purpose.
17 
 
18 
`timescale 1 ns/1 ps
19 
 
20 
module tdm_switch_top (
21 
  frame_sync, clk_out, mpi_rw, mpi_cs, reset, clk_in, mpi_clk, GSR, GTS, tx_stream, mpi_data_out, rx_stream, mpi_data_in, mpi_addr
22 
);
23 
  output frame_sync;
24 
  output clk_out;
25 
  input mpi_rw;
26 
  input mpi_cs;
27 
  input reset;
28 
  input clk_in;
29 
  input mpi_clk;
30 
  input GSR;
31 
  input GTS;
32 
  output [7 : 0] tx_stream;
33 
  output [8 : 0] mpi_data_out;
34 
  input [7 : 0] rx_stream;
35 
  input [8 : 0] mpi_data_in;
36 
  input [8 : 0] mpi_addr;
37 
  wire frame_sync_OBUF;
38 
  wire mpi_clk_BUFGP;
39 
  wire _n0045;
40 
  wire mpi_data_in_0_IBUF;
41 
  wire mpi_data_in_1_IBUF;
42 
  wire mpi_data_in_2_IBUF;
43 
  wire mpi_data_in_3_IBUF;
44 
  wire mpi_data_in_4_IBUF;
45 
  wire mpi_data_in_5_IBUF;
46 
  wire mpi_data_in_6_IBUF;
47 
  wire mpi_data_in_7_IBUF;
48 
  wire mpi_data_in_8_IBUF;
49 
  wire mpi_addr_0_IBUF;
50 
  wire mpi_addr_1_IBUF;
51 
  wire mpi_addr_2_IBUF;
52 
  wire mpi_addr_3_IBUF;
53 
  wire mpi_addr_4_IBUF;
54 
  wire mpi_addr_5_IBUF;
55 
  wire mpi_addr_6_IBUF;
56 
  wire mpi_addr_7_IBUF;
57 
  wire mpi_addr_8_IBUF;
58 
  wire reset_IBUF;
59 
  wire \clk_in_BUFGP/IBUFG ;
60 
  wire mpi_cs_IBUF;
61 
  wire div_reg_2;
62 
  wire div_reg_1;
63 
  wire \mpi_clk_BUFGP/IBUFG ;
64 
  wire mpi_rw_IBUF;
65 
  wire div_reg;
66 
  wire clk_in_BUFGP;
67 
  wire ram_en;
68 
  wire frame_cnt_1_1;
69 
  wire GLOBAL_LOGIC0;
70 
  wire _n0054;
71 
  wire mem_page_sel;
72 
  wire Mmux__n0074__net2;
73 
  wire Mmux__n0074__net9;
74 
  wire N8791;
75 
  wire GLOBAL_LOGIC1;
76 
  wire \_n00631/O ;
77 
  wire frame_delay_cnt_0_1_0;
78 
  wire frame_delay_cnt_0_0_0;
79 
  wire \_n00621/O ;
80 
  wire frame_delay_cnt_1_1_0;
81 
  wire frame_delay_cnt_1_0_0;
82 
  wire \_n00611/O ;
83 
  wire frame_delay_cnt_2_1_0;
84 
  wire frame_delay_cnt_2_0_0;
85 
  wire \_n00601/O ;
86 
  wire frame_delay_cnt_3_1_0;
87 
  wire frame_delay_cnt_3_0_0;
88 
  wire \_n00591/O ;
89 
  wire frame_delay_cnt_4_1_0;
90 
  wire frame_delay_cnt_4_0_0;
91 
  wire \_n00581/O ;
92 
  wire frame_delay_cnt_5_1_0;
93 
  wire frame_delay_cnt_5_0_0;
94 
  wire \_n00571/O ;
95 
  wire frame_delay_cnt_6_1_0;
96 
  wire frame_delay_cnt_6_0_0;
97 
  wire \_n00561/O ;
98 
  wire frame_delay_cnt_7_1_0;
99 
  wire frame_delay_cnt_7_0_0;
100 
  wire \_n00311/O ;
101 
  wire \_n00321/O ;
102 
  wire Ker87891_1;
103 
  wire N8682;
104 
  wire _n0225;
105 
  wire frame_delay_cnt_0_0_0__n0000;
106 
  wire N8676;
107 
  wire frame_delay_cnt_0_0_1__n0000;
108 
  wire _n0227;
109 
  wire frame_delay_cnt_1_0_0__n0000;
110 
  wire N8670;
111 
  wire frame_delay_cnt_1_0_1__n0000;
112 
  wire _n0228;
113 
  wire frame_delay_cnt_2_0_0__n0000;
114 
  wire N8664;
115 
  wire frame_delay_cnt_2_0_1__n0000;
116 
  wire _n0229;
117 
  wire frame_delay_cnt_3_0_0__n0000;
118 
  wire N8658;
119 
  wire frame_delay_cnt_3_0_1__n0000;
120 
  wire _n0230;
121 
  wire frame_delay_cnt_4_0_0__n0000;
122 
  wire N8652;
123 
  wire frame_delay_cnt_4_0_1__n0000;
124 
  wire _n0231;
125 
  wire frame_delay_cnt_5_0_0__n0000;
126 
  wire N8646;
127 
  wire frame_delay_cnt_5_0_1__n0000;
128 
  wire _n0232;
129 
  wire frame_delay_cnt_6_0_0__n0000;
130 
  wire N8640;
131 
  wire frame_delay_cnt_6_0_1__n0000;
132 
  wire _n0233;
133 
  wire frame_delay_cnt_7_0_0__n0000;
134 
  wire N8634;
135 
  wire frame_delay_cnt_7_0_1__n0000;
136 
  wire N8954;
137 
  wire N8728;
138 
  wire _n0038;
139 
  wire _n0028;
140 
  wire _n0030;
141 
  wire _n0039;
142 
  wire _n0040;
143 
  wire _n0029;
144 
  wire _n0033;
145 
  wire _n0042;
146 
  wire _n0041;
147 
  wire _n0027;
148 
  wire _n0034;
149 
  wire _n0044;
150 
  wire _n0043;
151 
  wire GLOBAL_LOGIC1_0;
152 
  wire GLOBAL_LOGIC1_1;
153 
  wire GLOBAL_LOGIC0_0;
154 
  wire GLOBAL_LOGIC0_1;
155 
  wire GLOBAL_LOGIC0_2;
156 
  wire GLOBAL_LOGIC0_3;
157 
  wire GLOBAL_LOGIC0_4;
158 
  wire GLOBAL_LOGIC0_5;
159 
  wire GLOBAL_LOGIC0_6;
160 
  wire GTS_0;
161 
  wire \mpi_data_in<1>/IBUF ;
162 
  wire \mpi_data_in<1>/IDELAY ;
163 
  wire \mpi_data_in<0>/IBUF ;
164 
  wire \mpi_data_in<0>/IDELAY ;
165 
  wire \frame_sync/OUTMUX ;
166 
  wire \frame_sync/TORGTS ;
167 
  wire \frame_sync/ENABLE ;
168 
  wire \mpi_data_in<1>/IFF/RST ;
169 
  wire \mpi_data_in<0>/IFF/RST ;
170 
  wire \mpi_data_out<0>/TDATANOT ;
171 
  wire \mpi_data_out<0>/OUTMUX ;
172 
  wire \mpi_data_out<0>/TORGTS ;
173 
  wire \mpi_data_out<0>/ENABLE ;
174 
  wire \mpi_data_out<1>/TDATANOT ;
175 
  wire \mpi_data_out<1>/OUTMUX ;
176 
  wire \mpi_data_out<1>/TORGTS ;
177 
  wire \mpi_data_out<1>/ENABLE ;
178 
  wire \mpi_data_out<2>/TDATANOT ;
179 
  wire \mpi_data_out<2>/OUTMUX ;
180 
  wire \mpi_data_out<2>/TORGTS ;
181 
  wire \mpi_data_out<2>/ENABLE ;
182 
  wire \mpi_data_out<3>/TDATANOT ;
183 
  wire \mpi_data_out<3>/OUTMUX ;
184 
  wire \mpi_data_out<3>/TORGTS ;
185 
  wire \mpi_data_out<3>/ENABLE ;
186 
  wire \mpi_data_out<4>/TDATANOT ;
187 
  wire \mpi_data_out<4>/OUTMUX ;
188 
  wire \mpi_data_out<4>/TORGTS ;
189 
  wire \mpi_data_out<4>/ENABLE ;
190 
  wire \mpi_data_out<5>/TDATANOT ;
191 
  wire \mpi_data_out<5>/OUTMUX ;
192 
  wire \mpi_data_out<5>/TORGTS ;
193 
  wire \mpi_data_out<5>/ENABLE ;
194 
  wire \mpi_data_out<6>/TDATANOT ;
195 
  wire \mpi_data_out<6>/OUTMUX ;
196 
  wire \mpi_data_out<6>/TORGTS ;
197 
  wire \mpi_data_out<6>/ENABLE ;
198 
  wire \mpi_data_out<7>/TDATANOT ;
199 
  wire \mpi_data_out<7>/OUTMUX ;
200 
  wire \mpi_data_out<7>/TORGTS ;
201 
  wire \mpi_data_out<7>/ENABLE ;
202 
  wire \mpi_data_out<8>/TDATANOT ;
203 
  wire \mpi_data_out<8>/OUTMUX ;
204 
  wire \mpi_data_out<8>/TORGTS ;
205 
  wire \mpi_data_out<8>/ENABLE ;
206 
  wire rx_stream_0_IBUF;
207 
  wire \rx_stream<0>/IDELAY ;
208 
  wire \rx_stream<0>/ICLKNOT ;
209 
  wire \rx_stream<0>/IFF/RST ;
210 
  wire rx_stream_1_IBUF;
211 
  wire \rx_stream<1>/IDELAY ;
212 
  wire \rx_stream<1>/ICLKNOT ;
213 
  wire \rx_stream<1>/IFF/RST ;
214 
  wire rx_stream_2_IBUF;
215 
  wire \rx_stream<2>/IDELAY ;
216 
  wire \rx_stream<2>/ICLKNOT ;
217 
  wire \rx_stream<2>/IFF/RST ;
218 
  wire rx_stream_3_IBUF;
219 
  wire \rx_stream<3>/IDELAY ;
220 
  wire \rx_stream<3>/ICLKNOT ;
221 
  wire \rx_stream<3>/IFF/RST ;
222 
  wire rx_stream_4_IBUF;
223 
  wire \rx_stream<4>/IDELAY ;
224 
  wire \rx_stream<4>/ICLKNOT ;
225 
  wire \rx_stream<4>/IFF/RST ;
226 
  wire rx_stream_5_IBUF;
227 
  wire \rx_stream<5>/IDELAY ;
228 
  wire \rx_stream<5>/ICLKNOT ;
229 
  wire \rx_stream<5>/IFF/RST ;
230 
  wire rx_stream_6_IBUF;
231 
  wire \rx_stream<6>/IDELAY ;
232 
  wire \rx_stream<6>/ICLKNOT ;
233 
  wire \rx_stream<6>/IFF/RST ;
234 
  wire rx_stream_7_IBUF;
235 
  wire \rx_stream<7>/IDELAY ;
236 
  wire \rx_stream<7>/ICLKNOT ;
237 
  wire \rx_stream<7>/IFF/RST ;
238 
  wire \tx_stream<0>/OD ;
239 
  wire \tx_stream<0>/OUTMUX ;
240 
  wire \tx_stream<0>/TORGTS ;
241 
  wire \tx_stream<0>/ENABLE ;
242 
  wire \tx_stream<0>/OFF/RST ;
243 
  wire \tx_stream<1>/OD ;
244 
  wire \tx_stream<1>/OUTMUX ;
245 
  wire \tx_stream<1>/TORGTS ;
246 
  wire \tx_stream<1>/ENABLE ;
247 
  wire \tx_stream<1>/OFF/RST ;
248 
  wire \tx_stream<2>/OD ;
249 
  wire \tx_stream<2>/OUTMUX ;
250 
  wire \tx_stream<2>/TORGTS ;
251 
  wire \tx_stream<2>/ENABLE ;
252 
  wire \tx_stream<2>/OFF/RST ;
253 
  wire \tx_stream<3>/OD ;
254 
  wire \tx_stream<3>/OUTMUX ;
255 
  wire \tx_stream<3>/TORGTS ;
256 
  wire \tx_stream<3>/ENABLE ;
257 
  wire \tx_stream<3>/OFF/RST ;
258 
  wire \tx_stream<4>/OD ;
259 
  wire \tx_stream<4>/OUTMUX ;
260 
  wire \tx_stream<4>/TORGTS ;
261 
  wire \tx_stream<4>/ENABLE ;
262 
  wire \tx_stream<4>/OFF/RST ;
263 
  wire \tx_stream<5>/OD ;
264 
  wire \tx_stream<5>/OUTMUX ;
265 
  wire \tx_stream<5>/TORGTS ;
266 
  wire \tx_stream<5>/ENABLE ;
267 
  wire \tx_stream<5>/OFF/RST ;
268 
  wire \tx_stream<6>/OD ;
269 
  wire \tx_stream<6>/OUTMUX ;
270 
  wire \tx_stream<6>/TORGTS ;
271 
  wire \tx_stream<6>/ENABLE ;
272 
  wire \tx_stream<6>/OFF/RST ;
273 
  wire \tx_stream<7>/OD ;
274 
  wire \tx_stream<7>/OUTMUX ;
275 
  wire \tx_stream<7>/TORGTS ;
276 
  wire \tx_stream<7>/ENABLE ;
277 
  wire \tx_stream<7>/OFF/RST ;
278 
  wire \clk_out/OUTMUX ;
279 
  wire \clk_out/TORGTS ;
280 
  wire \clk_out/ENABLE ;
281 
  wire \c_mem/ENA_INTNOT ;
282 
  wire \c_mem/RSTA_INTNOT ;
283 
  wire \c_mem/RSTB_INTNOT ;
284 
  wire \c_mem/LOGIC_ZERO ;
285 
  wire \c_mem/WEB_INTNOT ;
286 
  wire \c_mem/ADDRA0 ;
287 
  wire \c_mem/ADDRA1 ;
288 
  wire \c_mem/ADDRA2 ;
289 
  wire \c_mem/ADDRA3 ;
290 
  wire \c_mem/ADDRB0 ;
291 
  wire \c_mem/ADDRB1 ;
292 
  wire \c_mem/ADDRB2 ;
293 
  wire \c_mem/ADDRB3 ;
294 
  wire \c_mem/DOA8 ;
295 
  wire \c_mem/DOA9 ;
296 
  wire \c_mem/DOA10 ;
297 
  wire \c_mem/DOA11 ;
298 
  wire \c_mem/DOA12 ;
299 
  wire \c_mem/DOA13 ;
300 
  wire \c_mem/DOA14 ;
301 
  wire \c_mem/DOA15 ;
302 
  wire \c_mem/DOB9 ;
303 
  wire \c_mem/DOB10 ;
304 
  wire \c_mem/DOB11 ;
305 
  wire \c_mem/DOB12 ;
306 
  wire \c_mem/DOB13 ;
307 
  wire \c_mem/DOB14 ;
308 
  wire \c_mem/DOB15 ;
309 
  wire \d_mem/LOGIC_ONE ;
310 
  wire \d_mem/RSTA_INTNOT ;
311 
  wire \d_mem/RSTB_INTNOT ;
312 
  wire \d_mem/LOGIC_ZERO ;
313 
  wire \d_mem/ADDRA0 ;
314 
  wire \d_mem/ADDRA1 ;
315 
  wire \d_mem/ADDRA2 ;
316 
  wire \d_mem/ADDRB0 ;
317 
  wire \d_mem/ADDRB1 ;
318 
  wire \d_mem/ADDRB2 ;
319 
  wire \d_mem/ADDRB3 ;
320 
  wire \d_mem/DIA8 ;
321 
  wire \d_mem/DIA9 ;
322 
  wire \d_mem/DIA10 ;
323 
  wire \d_mem/DIA11 ;
324 
  wire \d_mem/DIA12 ;
325 
  wire \d_mem/DIA13 ;
326 
  wire \d_mem/DIA14 ;
327 
  wire \d_mem/DIA15 ;
328 
  wire \d_mem/DOA8 ;
329 
  wire \d_mem/DOA9 ;
330 
  wire \d_mem/DOA10 ;
331 
  wire \d_mem/DOA11 ;
332 
  wire \d_mem/DOA12 ;
333 
  wire \d_mem/DOA13 ;
334 
  wire \d_mem/DOA14 ;
335 
  wire \d_mem/DOA15 ;
336 
  wire \d_mem/DOB0 ;
337 
  wire \d_mem/DOB1 ;
338 
  wire \d_mem/DOB2 ;
339 
  wire \d_mem/DOB3 ;
340 
  wire \d_mem/DOB4 ;
341 
  wire \d_mem/DOB5 ;
342 
  wire \d_mem/DOB6 ;
343 
  wire \d_mem/DOB7 ;
344 
  wire \d_mem/DOB8 ;
345 
  wire \d_mem/DOB9 ;
346 
  wire \d_mem/DOB10 ;
347 
  wire \d_mem/DOB11 ;
348 
  wire \d_mem/DOB12 ;
349 
  wire \d_mem/DOB13 ;
350 
  wire \d_mem/DOB14 ;
351 
  wire \d_mem/DOB15 ;
352 
  wire \data_in_bus<12>/F5MUX ;
353 
  wire N9669;
354 
  wire N9671;
355 
  wire \data_in_bus<3>/F5MUX ;
356 
  wire N9619;
357 
  wire N9621;
358 
  wire \data_in_bus<13>/F5MUX ;
359 
  wire N9659;
360 
  wire N9661;
361 
  wire \data_in_bus<4>/F5MUX ;
362 
  wire N9614;
363 
  wire N9616;
364 
  wire \data_in_bus<14>/F5MUX ;
365 
  wire N9649;
366 
  wire N9651;
367 
  wire \data_in_bus<5>/F5MUX ;
368 
  wire N9664;
369 
  wire N9666;
370 
  wire \data_in_bus<15>/F5MUX ;
371 
  wire N9674;
372 
  wire N9676;
373 
  wire \Mmux__n0074__net2/F5MUX ;
374 
  wire Mmux__n0074__net0;
375 
  wire Mmux__n0074__net1;
376 
  wire Mmux__n0074__net5;
377 
  wire \_n0246<2>/F6MUX ;
378 
  wire Mmux__n0074__net3;
379 
  wire Mmux__n0074__net4;
380 
  wire \Mmux__n0074__net9/F5MUX ;
381 
  wire Mmux__n0074__net7;
382 
  wire Mmux__n0074__net8;
383 
  wire Mmux__n0074__net12;
384 
  wire \_n0246<3>/F6MUX ;
385 
  wire Mmux__n0074__net10;
386 
  wire Mmux__n0074__net11;
387 
  wire \data_in_bus<6>/F5MUX ;
388 
  wire N9654;
389 
  wire N9656;
390 
  wire \data_in_bus<7>/F5MUX ;
391 
  wire N9644;
392 
  wire N9646;
393 
  wire \data_in_bus<8>/F5MUX ;
394 
  wire N9634;
395 
  wire N9636;
396 
  wire \data_in_bus<9>/F5MUX ;
397 
  wire N9629;
398 
  wire N9631;
399 
  wire \data_in_bus<0>/F5MUX ;
400 
  wire N9679;
401 
  wire N9681;
402 
  wire \data_in_bus<10>/F5MUX ;
403 
  wire N9624;
404 
  wire N9626;
405 
  wire \data_in_bus<1>/F5MUX ;
406 
  wire N9609;
407 
  wire N9611;
408 
  wire \data_in_bus<11>/F5MUX ;
409 
  wire N9639;
410 
  wire N9641;
411 
  wire \data_in_bus<2>/F5MUX ;
412 
  wire N9604;
413 
  wire N9606;
414 
  wire \d_mem_addr_cnt<0>/LOGIC_ZERO ;
415 
  wire d_mem_addr_cnt_Madd__n0000_inst_cy_0;
416 
  wire \d_mem_addr_cnt<0>/GROM ;
417 
  wire \d_mem_addr_cnt<0>/CYMUXG ;
418 
  wire d_mem_addr_cnt_Madd__n0000_inst_lut2_0;
419 
  wire \d_mem_addr_cnt<2>/CYINIT ;
420 
  wire d_mem_addr_cnt_Madd__n0000_inst_cy_2;
421 
  wire \d_mem_addr_cnt<2>/GROM ;
422 
  wire \d_mem_addr_cnt<2>/LOGIC_ZERO ;
423 
  wire \d_mem_addr_cnt<2>/CYMUXG ;
424 
  wire \d_mem_addr_cnt<2>/FROM ;
425 
  wire \d_mem_addr_cnt<4>/CYINIT ;
426 
  wire \d_mem_addr_cnt<4>_rt ;
427 
  wire \c_mem_addr_cnt<0>/LOGIC_ZERO ;
428 
  wire c_mem_addr_cnt_Madd__n0000_inst_cy_0;
429 
  wire \c_mem_addr_cnt<0>/GROM ;
430 
  wire \c_mem_addr_cnt<0>/CYMUXG ;
431 
  wire c_mem_addr_cnt_Madd__n0000_inst_lut2_0;
432 
  wire \c_mem_addr_cnt<2>/CYINIT ;
433 
  wire c_mem_addr_cnt_Madd__n0000_inst_cy_2;
434 
  wire \c_mem_addr_cnt<2>/GROM ;
435 
  wire \c_mem_addr_cnt<2>/LOGIC_ZERO ;
436 
  wire \c_mem_addr_cnt<2>/CYMUXG ;
437 
  wire \c_mem_addr_cnt<2>/FROM ;
438 
  wire \c_mem_addr_cnt<4>/CYINIT ;
439 
  wire \c_mem_addr_cnt<4>_rt ;
440 
  wire \frame_cnt<0>/CKMUXNOT ;
441 
  wire \frame_cnt<0>/XORG ;
442 
  wire \frame_cnt<0>/SRMUX_OUTPUTNOT ;
443 
  wire \frame_cnt<0>/LOGIC_ZERO ;
444 
  wire frame_cnt_Madd__n0000_inst_cy_5;
445 
  wire \frame_cnt<0>/GROM ;
446 
  wire \frame_cnt<0>/CYMUXG ;
447 
  wire frame_cnt_Madd__n0000_inst_lut2_5;
448 
  wire \frame_cnt<0>/FFX/RST ;
449 
  wire \frame_cnt<0>/FFY/RST ;
450 
  wire \frame_cnt<2>/CKMUXNOT ;
451 
  wire \frame_cnt<2>/SRMUX_OUTPUTNOT ;
452 
  wire \frame_cnt<2>/CYINIT ;
453 
  wire frame_cnt_Madd__n0000_inst_cy_7;
454 
  wire \frame_cnt<2>/GROM ;
455 
  wire \frame_cnt<2>/LOGIC_ZERO ;
456 
  wire \frame_cnt<2>/CYMUXG ;
457 
  wire \frame_cnt<2>/FROM ;
458 
  wire \frame_cnt<2>/FFX/RST ;
459 
  wire \frame_cnt<4>/CKMUXNOT ;
460 
  wire \frame_cnt<4>/SRMUX_OUTPUTNOT ;
461 
  wire \frame_cnt<4>/CYINIT ;
462 
  wire frame_cnt_Madd__n0000_inst_cy_9;
463 
  wire \frame_cnt<4>/GROM ;
464 
  wire \frame_cnt<4>/LOGIC_ZERO ;
465 
  wire \frame_cnt<4>/CYMUXG ;
466 
  wire \frame_cnt<4>/FROM ;
467 
  wire \frame_cnt<4>/FFX/RST ;
468 
  wire \frame_cnt<4>/FFY/RST ;
469 
  wire \frame_cnt<6>/CKMUXNOT ;
470 
  wire \frame_cnt<6>/SRMUX_OUTPUTNOT ;
471 
  wire \frame_cnt<6>/CYINIT ;
472 
  wire frame_cnt_Madd__n0000_inst_cy_11;
473 
  wire \frame_cnt<6>/GROM ;
474 
  wire \frame_cnt<6>/LOGIC_ZERO ;
475 
  wire \frame_cnt<6>/CYMUXG ;
476 
  wire \frame_cnt<6>/FROM ;
477 
  wire \frame_cnt<6>/FFX/RST ;
478 
  wire \frame_cnt<6>/FFY/RST ;
479 
  wire \frame_cnt<8>/CYINIT ;
480 
  wire \frame_cnt<8>/SRMUX_OUTPUTNOT ;
481 
  wire \frame_cnt<8>/CKMUXNOT ;
482 
  wire \frame_cnt<8>_rt ;
483 
  wire \frame_cnt<8>/FFX/RST ;
484 
  wire \rx_buf_reg_0<1>/GROM ;
485 
  wire \rx_buf_reg_0<1>/FFY/RST ;
486 
  wire \rx_buf_reg_0<1>/FFX/RST ;
487 
  wire \rx_buf_reg_1<1>/GROM ;
488 
  wire \rx_buf_reg_1<1>/FFY/RST ;
489 
  wire \rx_buf_reg_1<1>/FFX/RST ;
490 
  wire \rx_buf_reg_2<1>/GROM ;
491 
  wire \rx_buf_reg_2<1>/FFX/RST ;
492 
  wire \rx_buf_reg_2<1>/FFY/RST ;
493 
  wire \rx_buf_reg_3<1>/GROM ;
494 
  wire \rx_buf_reg_3<1>/FFX/RST ;
495 
  wire \rx_buf_reg_3<1>/FFY/RST ;
496 
  wire \rx_buf_reg_4<1>/GROM ;
497 
  wire \rx_buf_reg_4<1>/FFX/RST ;
498 
  wire \rx_buf_reg_4<1>/FFY/RST ;
499 
  wire \rx_buf_reg_5<1>/GROM ;
500 
  wire \rx_buf_reg_5<1>/FFY/RST ;
501 
  wire \rx_buf_reg_5<1>/FFX/RST ;
502 
  wire \rx_buf_reg_6<1>/GROM ;
503 
  wire \rx_buf_reg_6<1>/FFY/RST ;
504 
  wire \rx_buf_reg_6<1>/FFX/RST ;
505 
  wire \rx_buf_reg_7<1>/GROM ;
506 
  wire \rx_buf_reg_7<1>/FFY/RST ;
507 
  wire \rx_buf_reg_7<1>/FFX/RST ;
508 
  wire \tx_buf_reg_4<1>/GROM ;
509 
  wire \tx_buf_reg_4<1>/FFY/RST ;
510 
  wire \tx_buf_reg_4<1>/FFX/RST ;
511 
  wire \tx_buf_reg_5<1>/GROM ;
512 
  wire \tx_buf_reg_5<1>/FFY/RST ;
513 
  wire \tx_buf_reg_5<1>/FFX/RST ;
514 
  wire \tx_shift_reg_0<2>/FFY/RST ;
515 
  wire \tx_shift_reg_0<2>/FFX/RST ;
516 
  wire \tx_shift_reg_0<4>/FFY/RST ;
517 
  wire \tx_shift_reg_0<4>/FFX/RST ;
518 
  wire \tx_shift_reg_1<2>/FFY/RST ;
519 
  wire \tx_shift_reg_1<2>/FFX/RST ;
520 
  wire \tx_shift_reg_0<6>/FFY/RST ;
521 
  wire \tx_shift_reg_0<6>/FFX/RST ;
522 
  wire \tx_shift_reg_0<7>/FROM ;
523 
  wire \tx_shift_reg_0<7>/FFY/RST ;
524 
  wire \tx_shift_reg_1<4>/FFX/RST ;
525 
  wire \tx_shift_reg_1<4>/FFY/RST ;
526 
  wire \tx_shift_reg_6<4>/FFX/RST ;
527 
  wire \tx_shift_reg_6<4>/FFY/RST ;
528 
  wire \tx_shift_reg_6<6>/FFY/RST ;
529 
  wire \tx_shift_reg_6<6>/FFX/RST ;
530 
  wire \tx_shift_reg_7<4>/FFY/RST ;
531 
  wire \tx_shift_reg_7<4>/FFX/RST ;
532 
  wire \tx_shift_reg_7<7>/FROM ;
533 
  wire \ctrl_out_reg<0>/FROM ;
534 
  wire \ctrl_out_reg<1>/FROM ;
535 
  wire \frame_delay_cnt_0_0_0/CKMUXNOT ;
536 
  wire \frame_delay_cnt_0_0_0/FROM ;
537 
  wire \frame_delay_cnt_0_1_0/CKMUXNOT ;
538 
  wire \frame_delay_cnt_0_1_0/FROM ;
539 
  wire \frame_delay_cnt_1_0_0/CKMUXNOT ;
540 
  wire \frame_delay_cnt_1_0_0/FROM ;
541 
  wire \frame_delay_cnt_1_1_0/CKMUXNOT ;
542 
  wire \frame_delay_cnt_1_1_0/FROM ;
543 
  wire \frame_delay_cnt_2_0_0/CKMUXNOT ;
544 
  wire \frame_delay_cnt_2_0_0/FROM ;
545 
  wire \frame_delay_cnt_2_1_0/CKMUXNOT ;
546 
  wire \frame_delay_cnt_2_1_0/FROM ;
547 
  wire \frame_delay_cnt_3_0_0/CKMUXNOT ;
548 
  wire \frame_delay_cnt_3_0_0/FROM ;
549 
  wire \frame_delay_cnt_3_1_0/CKMUXNOT ;
550 
  wire \frame_delay_cnt_3_1_0/FROM ;
551 
  wire \frame_delay_cnt_4_0_0/CKMUXNOT ;
552 
  wire \frame_delay_cnt_4_0_0/FROM ;
553 
  wire \frame_delay_cnt_4_1_0/CKMUXNOT ;
554 
  wire \frame_delay_cnt_4_1_0/FROM ;
555 
  wire \frame_delay_cnt_5_0_0/CKMUXNOT ;
556 
  wire \frame_delay_cnt_5_0_0/FROM ;
557 
  wire \frame_delay_cnt_5_1_0/CKMUXNOT ;
558 
  wire \frame_delay_cnt_5_1_0/FROM ;
559 
  wire \frame_delay_cnt_5_1_0/FFY/RST ;
560 
  wire \frame_delay_cnt_5_1_0/FFY/SET ;
561 
  wire \mem_page_sel/GROM ;
562 
  wire \mem_page_sel/SRMUX_OUTPUTNOT ;
563 
  wire \mem_page_sel/FROM ;
564 
  wire \frame_delay_cnt_6_0_0/CKMUXNOT ;
565 
  wire \frame_delay_cnt_6_0_0/FROM ;
566 
  wire \frame_delay_cnt_6_1_0/CKMUXNOT ;
567 
  wire \frame_delay_cnt_6_1_0/FROM ;
568 
  wire \frame_delay_cnt_6_1_0/FFY/RST ;
569 
  wire \frame_delay_cnt_6_1_0/FFY/SET ;
570 
  wire \frame_delay_cnt_7_0_0/CKMUXNOT ;
571 
  wire \frame_delay_cnt_7_0_0/FROM ;
572 
  wire \frame_delay_cnt_7_1_0/CKMUXNOT ;
573 
  wire \frame_delay_cnt_7_1_0/FROM ;
574 
  wire \N8954/GROM ;
575 
  wire \N8954/FROM ;
576 
  wire \N8728/GROM ;
577 
  wire \N8728/FROM ;
578 
  wire \_n0028/GROM ;
579 
  wire \_n0028/FROM ;
580 
  wire \_n0039/GROM ;
581 
  wire \_n0039/FROM ;
582 
  wire \_n0029/GROM ;
583 
  wire \_n0029/FROM ;
584 
  wire \_n0042/GROM ;
585 
  wire \_n0042/FROM ;
586 
  wire \_n0027/GROM ;
587 
  wire \_n0027/FROM ;
588 
  wire \_n0044/GROM ;
589 
  wire \_n0044/FROM ;
590 
  wire \_n0045/GROM ;
591 
  wire \_COND_1<2>/GROM ;
592 
  wire \_COND_1<2>/FROM ;
593 
  wire \_n0230/GROM ;
594 
  wire \_n0231/GROM ;
595 
  wire \_n0232/GROM ;
596 
  wire \_n0225/GROM ;
597 
  wire \_n0233/GROM ;
598 
  wire \_n0227/GROM ;
599 
  wire \_n0228/GROM ;
600 
  wire \_n0229/GROM ;
601 
  wire \div_reg/BYMUXNOT ;
602 
  wire \div_reg/SRMUX_OUTPUTNOT ;
603 
  wire \rx_shift_reg_0<1>/CKMUXNOT ;
604 
  wire \rx_shift_reg_0<3>/CKMUXNOT ;
605 
  wire \rx_shift_reg_0<5>/CKMUXNOT ;
606 
  wire \rx_shift_reg_1<1>/CKMUXNOT ;
607 
  wire \rx_shift_reg_1<3>/CKMUXNOT ;
608 
  wire \rx_shift_reg_0<6>/CKMUXNOT ;
609 
  wire \rx_shift_reg_1<5>/CKMUXNOT ;
610 
  wire \rx_shift_reg_2<1>/CKMUXNOT ;
611 
  wire \rx_shift_reg_1<6>/CKMUXNOT ;
612 
  wire \rx_shift_reg_2<3>/CKMUXNOT ;
613 
  wire \rx_shift_reg_2<5>/CKMUXNOT ;
614 
  wire \rx_shift_reg_3<1>/CKMUXNOT ;
615 
  wire \rx_shift_reg_2<6>/CKMUXNOT ;
616 
  wire \rx_shift_reg_3<3>/CKMUXNOT ;
617 
  wire \rx_shift_reg_3<3>/FFY/RST ;
618 
  wire \rx_shift_reg_3<3>/FFX/RST ;
619 
  wire \rx_shift_reg_3<5>/CKMUXNOT ;
620 
  wire \rx_shift_reg_4<1>/CKMUXNOT ;
621 
  wire \rx_shift_reg_3<6>/CKMUXNOT ;
622 
  wire \rx_shift_reg_3<6>/FFY/RST ;
623 
  wire \rx_shift_reg_4<3>/CKMUXNOT ;
624 
  wire \rx_shift_reg_4<5>/CKMUXNOT ;
625 
  wire \rx_shift_reg_4<5>/FFX/RST ;
626 
  wire \rx_shift_reg_4<5>/FFY/RST ;
627 
  wire \rx_shift_reg_5<1>/CKMUXNOT ;
628 
  wire \rx_shift_reg_4<6>/CKMUXNOT ;
629 
  wire \rx_shift_reg_5<3>/CKMUXNOT ;
630 
  wire \rx_shift_reg_5<5>/CKMUXNOT ;
631 
  wire \rx_shift_reg_6<1>/CKMUXNOT ;
632 
  wire \rx_shift_reg_5<6>/CKMUXNOT ;
633 
  wire \rx_shift_reg_6<3>/CKMUXNOT ;
634 
  wire \rx_shift_reg_7<1>/CKMUXNOT ;
635 
  wire \rx_shift_reg_6<5>/CKMUXNOT ;
636 
  wire \rx_shift_reg_6<6>/CKMUXNOT ;
637 
  wire \rx_shift_reg_7<3>/CKMUXNOT ;
638 
  wire \rx_shift_reg_7<5>/CKMUXNOT ;
639 
  wire \rx_shift_reg_7<6>/CKMUXNOT ;
640 
  wire \ram_en/GROM ;
641 
  wire \ram_en/FROM ;
642 
  wire \mpi_data_out_5_OBUFT/GROM ;
643 
  wire \mpi_data_out_5_OBUFT/FROM ;
644 
  wire \_n0019<0>/GROM ;
645 
  wire \_n0019<0>/FROM ;
646 
  wire \_n0022<0>/GROM ;
647 
  wire \_n0022<0>/FROM ;
648 
  wire \_n0024<0>/GROM ;
649 
  wire \_n0024<0>/FROM ;
650 
  wire \_n0026<0>/GROM ;
651 
  wire \_n0026<0>/FROM ;
652 
  wire \mpi_data_out_4_OBUFT/GROM ;
653 
  wire \mpi_data_out_4_OBUFT/FROM ;
654 
  wire \div_reg_2/BYMUXNOT ;
655 
  wire \div_reg_2/SRMUX_OUTPUTNOT ;
656 
  wire \div_reg_2/BXMUXNOT ;
657 
  wire \frame_delay_cnt_0_0_1__n0000/GROM ;
658 
  wire \frame_delay_cnt_0_0_1__n0000/FROM ;
659 
  wire \frame_delay_cnt_1_0_1__n0000/GROM ;
660 
  wire \frame_delay_cnt_1_0_1__n0000/FROM ;
661 
  wire \d_mem_addr<0>/GROM ;
662 
  wire \frame_delay_cnt_2_0_1__n0000/GROM ;
663 
  wire \frame_delay_cnt_2_0_1__n0000/FROM ;
664 
  wire \rx_buf_reg_2<5>/FFY/RST ;
665 
  wire \rx_buf_reg_2<5>/FFX/RST ;
666 
  wire \rx_buf_reg_3<3>/FFY/RST ;
667 
  wire \rx_buf_reg_3<3>/FFX/RST ;
668 
  wire \rx_buf_reg_3<7>/FFX/RST ;
669 
  wire \rx_buf_reg_4<5>/FFX/RST ;
670 
  wire \frame_delay_cnt_3_0_1__n0000/GROM ;
671 
  wire \frame_delay_cnt_3_0_1__n0000/FROM ;
672 
  wire \frame_delay_cnt_4_0_1__n0000/GROM ;
673 
  wire \frame_delay_cnt_4_0_1__n0000/FROM ;
674 
  wire \frame_delay_cnt_5_0_1__n0000/GROM ;
675 
  wire \frame_delay_cnt_5_0_1__n0000/FROM ;
676 
  wire \frame_delay_cnt_6_0_1__n0000/GROM ;
677 
  wire \frame_delay_cnt_6_0_1__n0000/FROM ;
678 
  wire \frame_delay_cnt_7_0_1__n0000/GROM ;
679 
  wire \frame_delay_cnt_7_0_1__n0000/FROM ;
680 
  wire \mpi_data_out_3_OBUFT/GROM ;
681 
  wire \mpi_data_out_3_OBUFT/FROM ;
682 
  wire \frame_cnt_1_1/CKMUXNOT ;
683 
  wire \frame_cnt_1_1/SRMUX_OUTPUTNOT ;
684 
  wire \frame_cnt_1_1/FROM ;
685 
  wire \frame_delay_cnt_1_0_1__n0001/GROM ;
686 
  wire \frame_delay_cnt_1_0_1__n0001/FROM ;
687 
  wire \tx_buf_reg_2<7>/FFY/RST ;
688 
  wire \tx_buf_reg_3<5>/FFY/RST ;
689 
  wire \frame_delay_cnt_3_0_1__n0001/GROM ;
690 
  wire \frame_delay_cnt_3_0_1__n0001/FROM ;
691 
  wire \frame_delay_cnt_5_0_1__n0001/GROM ;
692 
  wire \frame_delay_cnt_5_0_1__n0001/FROM ;
693 
  wire \frame_cnt<2>/FFY/RST ;
694 
  wire \frame_delay_cnt_7_0_1__n0001/GROM ;
695 
  wire \frame_delay_cnt_7_0_1__n0001/FROM ;
696 
  wire \mpi_data_out_7_OBUFT/GROM ;
697 
  wire \tx_shift_reg_1<6>/FFY/RST ;
698 
  wire \tx_shift_reg_2<4>/FFX/RST ;
699 
  wire \tx_shift_reg_2<7>/FFX/RST ;
700 
  wire \tx_shift_reg_2<2>/FFY/RST ;
701 
  wire \tx_shift_reg_2<2>/FFX/RST ;
702 
  wire \tx_shift_reg_1<6>/FFX/RST ;
703 
  wire \tx_shift_reg_3<6>/FFY/RST ;
704 
  wire \tx_shift_reg_2<4>/FFY/RST ;
705 
  wire \tx_shift_reg_2<7>/FFY/RST ;
706 
  wire \tx_shift_reg_2<6>/FFY/RST ;
707 
  wire \tx_shift_reg_2<6>/FFX/RST ;
708 
  wire \tx_shift_reg_3<2>/FFY/RST ;
709 
  wire \tx_shift_reg_3<2>/FFX/RST ;
710 
  wire \tx_shift_reg_4<7>/FFY/RST ;
711 
  wire \tx_shift_reg_5<2>/FFY/RST ;
712 
  wire \tx_shift_reg_3<4>/FFX/RST ;
713 
  wire \tx_shift_reg_3<4>/FFY/RST ;
714 
  wire \tx_shift_reg_4<2>/FFY/RST ;
715 
  wire \rx_buf_reg_3<7>/FFY/RST ;
716 
  wire \tx_shift_reg_3<6>/FFX/RST ;
717 
  wire \tx_shift_reg_4<6>/FFY/RST ;
718 
  wire \tx_shift_reg_4<2>/FFX/RST ;
719 
  wire \tx_shift_reg_4<4>/FFY/RST ;
720 
  wire \tx_shift_reg_4<4>/FFX/RST ;
721 
  wire \tx_shift_reg_5<6>/FFY/RST ;
722 
  wire \tx_shift_reg_4<7>/FFX/RST ;
723 
  wire \tx_shift_reg_4<6>/FFX/RST ;
724 
  wire \tx_shift_reg_5<2>/FFX/RST ;
725 
  wire \tx_shift_reg_7<2>/FFY/RST ;
726 
  wire \tx_shift_reg_7<6>/FFY/RST ;
727 
  wire \tx_shift_reg_5<4>/FFX/RST ;
728 
  wire \tx_shift_reg_5<4>/FFY/RST ;
729 
  wire \tx_shift_reg_6<2>/FFY/RST ;
730 
  wire \tx_shift_reg_5<6>/FFX/RST ;
731 
  wire \tx_shift_reg_6<7>/FFY/RST ;
732 
  wire \tx_buf_reg_4<3>/FFX/RST ;
733 
  wire \tx_shift_reg_6<2>/FFX/RST ;
734 
  wire \tx_shift_reg_6<7>/FFX/RST ;
735 
  wire \frame_delay_cnt_7_1_0/FFY/RST ;
736 
  wire \frame_delay_cnt_7_1_0/FFY/SET ;
737 
  wire \tx_shift_reg_7<6>/FFX/RST ;
738 
  wire \tx_shift_reg_7<2>/FFX/RST ;
739 
  wire \mem_page_sel/FFY/RST ;
740 
  wire \tx_buf_reg_2<7>/FFX/RST ;
741 
  wire \rx_shift_reg_4<6>/FFY/RST ;
742 
  wire \ctrl_out_reg<1>/FFY/RST ;
743 
  wire \rx_shift_reg_5<5>/FFX/RST ;
744 
  wire \tx_shift_reg_7<7>/FFY/RST ;
745 
  wire \ctrl_out_reg<0>/FFY/RST ;
746 
  wire \frame_delay_cnt_0_0_0/FFY/RST ;
747 
  wire \frame_delay_cnt_0_0_0/FFY/SET ;
748 
  wire \frame_delay_cnt_0_1_0/FFY/RST ;
749 
  wire \frame_delay_cnt_0_1_0/FFY/SET ;
750 
  wire \frame_delay_cnt_1_0_0/FFY/RST ;
751 
  wire \frame_delay_cnt_1_0_0/FFY/SET ;
752 
  wire \rx_buf_reg_4<5>/FFY/RST ;
753 
  wire \frame_delay_cnt_6_0_0/FFY/RST ;
754 
  wire \frame_delay_cnt_6_0_0/FFY/SET ;
755 
  wire \frame_delay_cnt_1_1_0/FFY/RST ;
756 
  wire \frame_delay_cnt_1_1_0/FFY/SET ;
757 
  wire \frame_delay_cnt_2_0_0/FFY/RST ;
758 
  wire \frame_delay_cnt_2_0_0/FFY/SET ;
759 
  wire \frame_delay_cnt_2_1_0/FFY/RST ;
760 
  wire \frame_delay_cnt_2_1_0/FFY/SET ;
761 
  wire \frame_delay_cnt_3_0_0/FFY/RST ;
762 
  wire \frame_delay_cnt_3_0_0/FFY/SET ;
763 
  wire \frame_delay_cnt_3_1_0/FFY/RST ;
764 
  wire \frame_delay_cnt_3_1_0/FFY/SET ;
765 
  wire \frame_delay_cnt_4_0_0/FFY/RST ;
766 
  wire \frame_delay_cnt_4_0_0/FFY/SET ;
767 
  wire \frame_delay_cnt_4_1_0/FFY/RST ;
768 
  wire \frame_delay_cnt_4_1_0/FFY/SET ;
769 
  wire \rx_shift_reg_3<5>/FFX/RST ;
770 
  wire \rx_shift_reg_5<5>/FFY/RST ;
771 
  wire \frame_delay_cnt_5_0_0/FFY/RST ;
772 
  wire \frame_delay_cnt_5_0_0/FFY/SET ;
773 
  wire \tx_buf_reg_3<5>/FFX/RST ;
774 
  wire \rx_shift_reg_3<5>/FFY/RST ;
775 
  wire \frame_delay_cnt_7_0_0/FFY/RST ;
776 
  wire \frame_delay_cnt_7_0_0/FFY/SET ;
777 
  wire \rx_shift_reg_4<3>/FFY/RST ;
778 
  wire \rx_shift_reg_0<1>/FFX/RST ;
779 
  wire \rx_shift_reg_5<1>/FFY/RST ;
780 
  wire \rx_shift_reg_1<5>/FFX/RST ;
781 
  wire \div_reg/FFY/RST ;
782 
  wire \rx_shift_reg_0<1>/FFY/RST ;
783 
  wire \rx_shift_reg_1<1>/FFX/RST ;
784 
  wire \rx_shift_reg_2<3>/FFX/RST ;
785 
  wire \rx_shift_reg_2<3>/FFY/RST ;
786 
  wire \rx_shift_reg_0<5>/FFX/RST ;
787 
  wire \rx_shift_reg_1<3>/FFX/RST ;
788 
  wire \rx_shift_reg_0<3>/FFY/RST ;
789 
  wire \rx_shift_reg_0<3>/FFX/RST ;
790 
  wire \rx_shift_reg_0<5>/FFY/RST ;
791 
  wire \rx_shift_reg_2<1>/FFY/RST ;
792 
  wire \rx_shift_reg_4<3>/FFX/RST ;
793 
  wire \rx_buf_reg_5<3>/FFY/RST ;
794 
  wire \rx_shift_reg_1<1>/FFY/RST ;
795 
  wire \rx_shift_reg_1<5>/FFY/RST ;
796 
  wire \rx_shift_reg_2<1>/FFX/RST ;
797 
  wire \rx_shift_reg_0<6>/FFY/RST ;
798 
  wire \rx_shift_reg_1<3>/FFY/RST ;
799 
  wire \rx_shift_reg_6<1>/FFY/RST ;
800 
  wire \rx_shift_reg_4<1>/FFY/RST ;
801 
  wire \rx_shift_reg_1<6>/FFY/RST ;
802 
  wire \rx_shift_reg_4<1>/FFX/RST ;
803 
  wire \rx_shift_reg_2<5>/FFX/RST ;
804 
  wire \rx_shift_reg_6<1>/FFX/RST ;
805 
  wire \rx_shift_reg_3<1>/FFX/RST ;
806 
  wire \rx_shift_reg_2<5>/FFY/RST ;
807 
  wire \rx_shift_reg_3<1>/FFY/RST ;
808 
  wire \rx_shift_reg_2<6>/FFY/RST ;
809 
  wire \rx_buf_reg_5<3>/FFX/RST ;
810 
  wire \tx_buf_reg_4<3>/FFY/RST ;
811 
  wire \rx_shift_reg_5<3>/FFY/RST ;
812 
  wire \rx_shift_reg_5<3>/FFX/RST ;
813 
  wire \rx_shift_reg_5<1>/FFX/RST ;
814 
  wire \rx_shift_reg_7<1>/FFX/RST ;
815 
  wire \rx_shift_reg_5<6>/FFY/RST ;
816 
  wire \rx_shift_reg_6<3>/FFX/RST ;
817 
  wire \rx_shift_reg_7<3>/FFX/RST ;
818 
  wire \rx_shift_reg_7<5>/FFY/RST ;
819 
  wire \rx_shift_reg_6<3>/FFY/RST ;
820 
  wire \rx_shift_reg_6<5>/FFX/RST ;
821 
  wire \rx_shift_reg_7<3>/FFY/RST ;
822 
  wire \rx_shift_reg_7<1>/FFY/RST ;
823 
  wire \rx_shift_reg_7<5>/FFX/RST ;
824 
  wire \rx_shift_reg_6<6>/FFY/RST ;
825 
  wire \rx_shift_reg_6<5>/FFY/RST ;
826 
  wire \rx_buf_reg_1<5>/FFY/RST ;
827 
  wire \div_reg_2/FFY/RST ;
828 
  wire \div_reg_2/FFX/RST ;
829 
  wire \rx_shift_reg_7<6>/FFY/RST ;
830 
  wire \tx_buf_reg_5<7>/FFX/RST ;
831 
  wire \rx_buf_reg_0<3>/FFY/RST ;
832 
  wire \rx_buf_reg_1<3>/FFX/RST ;
833 
  wire \rx_buf_reg_2<3>/FFY/RST ;
834 
  wire \rx_buf_reg_2<3>/FFX/RST ;
835 
  wire \rx_buf_reg_0<5>/FFY/RST ;
836 
  wire \rx_buf_reg_5<5>/FFY/RST ;
837 
  wire \rx_buf_reg_1<7>/FFX/RST ;
838 
  wire \rx_buf_reg_4<7>/FFX/RST ;
839 
  wire \rx_buf_reg_1<7>/FFY/RST ;
840 
  wire \rx_buf_reg_4<7>/FFY/RST ;
841 
  wire \rx_buf_reg_1<5>/FFX/RST ;
842 
  wire \rx_buf_reg_0<3>/FFX/RST ;
843 
  wire \tx_buf_reg_5<5>/FFX/RST ;
844 
  wire \rx_buf_reg_0<5>/FFX/RST ;
845 
  wire \rx_buf_reg_0<7>/FFX/RST ;
846 
  wire \rx_buf_reg_0<7>/FFY/RST ;
847 
  wire \rx_buf_reg_3<5>/FFX/RST ;
848 
  wire \rx_buf_reg_1<3>/FFY/RST ;
849 
  wire \rx_buf_reg_2<7>/FFY/RST ;
850 
  wire \tx_buf_reg_4<7>/FFX/RST ;
851 
  wire \tx_buf_reg_5<7>/FFY/RST ;
852 
  wire \rx_buf_reg_2<7>/FFX/RST ;
853 
  wire \rx_buf_reg_3<5>/FFY/RST ;
854 
  wire \tx_buf_reg_5<5>/FFY/RST ;
855 
  wire \rx_buf_reg_4<3>/FFY/RST ;
856 
  wire \rx_buf_reg_4<3>/FFX/RST ;
857 
  wire \tx_buf_reg_4<7>/FFY/RST ;
858 
  wire \rx_buf_reg_5<5>/FFX/RST ;
859 
  wire \rx_buf_reg_7<7>/FFX/RST ;
860 
  wire \tx_buf_reg_1<7>/FFX/RST ;
861 
  wire \rx_buf_reg_5<7>/FFY/RST ;
862 
  wire \frame_cnt_1_1/FFY/RST ;
863 
  wire \rx_buf_reg_5<7>/FFX/RST ;
864 
  wire \rx_buf_reg_6<3>/FFX/RST ;
865 
  wire \rx_buf_reg_6<7>/FFY/RST ;
866 
  wire \rx_buf_reg_7<3>/FFX/RST ;
867 
  wire \rx_buf_reg_6<3>/FFY/RST ;
868 
  wire \rx_buf_reg_6<5>/FFX/RST ;
869 
  wire \tx_buf_reg_0<5>/FFY/RST ;
870 
  wire \rx_buf_reg_7<3>/FFY/RST ;
871 
  wire \rx_buf_reg_7<7>/FFY/RST ;
872 
  wire \rx_buf_reg_7<5>/FFY/RST ;
873 
  wire \rx_buf_reg_7<5>/FFX/RST ;
874 
  wire \rx_buf_reg_6<5>/FFY/RST ;
875 
  wire \rx_buf_reg_6<6>/FFY/RST ;
876 
  wire \tx_buf_reg_0<1>/FFY/RST ;
877 
  wire \tx_buf_reg_4<5>/FFY/RST ;
878 
  wire \tx_buf_reg_5<3>/FFX/RST ;
879 
  wire \tx_buf_reg_0<5>/FFX/RST ;
880 
  wire \tx_buf_reg_1<5>/FFX/RST ;
881 
  wire \tx_buf_reg_0<3>/FFY/RST ;
882 
  wire \tx_buf_reg_0<1>/FFX/RST ;
883 
  wire \tx_buf_reg_6<1>/FFY/RST ;
884 
  wire \tx_buf_reg_0<3>/FFX/RST ;
885 
  wire \tx_buf_reg_1<3>/FFX/RST ;
886 
  wire \tx_buf_reg_1<1>/FFX/RST ;
887 
  wire \tx_buf_reg_2<5>/FFX/RST ;
888 
  wire \tx_buf_reg_2<1>/FFY/RST ;
889 
  wire \tx_buf_reg_0<7>/FFX/RST ;
890 
  wire \tx_buf_reg_1<1>/FFY/RST ;
891 
  wire \tx_buf_reg_1<3>/FFY/RST ;
892 
  wire \tx_buf_reg_0<7>/FFY/RST ;
893 
  wire \tx_buf_reg_6<1>/FFX/RST ;
894 
  wire \tx_buf_reg_2<1>/FFX/RST ;
895 
  wire \tx_buf_reg_1<5>/FFY/RST ;
896 
  wire \tx_buf_reg_2<3>/FFX/RST ;
897 
  wire \tx_buf_reg_3<3>/FFY/RST ;
898 
  wire \tx_buf_reg_3<1>/FFY/RST ;
899 
  wire \tx_buf_reg_2<3>/FFY/RST ;
900 
  wire \tx_buf_reg_1<7>/FFY/RST ;
901 
  wire \tx_buf_reg_3<7>/FFX/RST ;
902 
  wire \tx_buf_reg_3<1>/FFX/RST ;
903 
  wire \tx_buf_reg_2<5>/FFY/RST ;
904 
  wire \tx_buf_reg_4<5>/FFX/RST ;
905 
  wire \tx_buf_reg_5<3>/FFY/RST ;
906 
  wire \tx_buf_reg_3<7>/FFY/RST ;
907 
  wire \tx_buf_reg_3<3>/FFX/RST ;
908 
  wire \tx_buf_reg_6<5>/FFX/RST ;
909 
  wire \tx_buf_reg_6<3>/FFY/RST ;
910 
  wire \tx_buf_reg_6<3>/FFX/RST ;
911 
  wire \tx_buf_reg_7<7>/FFY/RST ;
912 
  wire \tx_buf_reg_7<3>/FFX/RST ;
913 
  wire \tx_buf_reg_6<7>/FFX/RST ;
914 
  wire \frame_delay_buf_4<1>/FFY/RST ;
915 
  wire \tx_buf_reg_6<5>/FFY/RST ;
916 
  wire \tx_buf_reg_7<1>/FFY/RST ;
917 
  wire \tx_buf_reg_7<5>/FFX/RST ;
918 
  wire \tx_buf_reg_7<1>/FFX/RST ;
919 
  wire \frame_delay_buf_0<1>/FFY/RST ;
920 
  wire \tx_buf_reg_7<3>/FFY/RST ;
921 
  wire \tx_buf_reg_6<7>/FFY/RST ;
922 
  wire \frame_delay_buf_1<1>/FFY/RST ;
923 
  wire \frame_delay_buf_6<1>/FFY/RST ;
924 
  wire \tx_buf_reg_7<7>/FFX/RST ;
925 
  wire \tx_buf_reg_7<5>/FFY/RST ;
926 
  wire \frame_delay_buf_4<1>/FFX/RST ;
927 
  wire \frame_delay_buf_3<1>/FFY/RST ;
928 
  wire \frame_delay_buf_0<1>/FFX/RST ;
929 
  wire \frame_delay_buf_2<1>/FFX/RST ;
930 
  wire \frame_delay_buf_2<1>/FFY/RST ;
931 
  wire \frame_delay_buf_1<1>/FFX/RST ;
932 
  wire \frame_delay_buf_3<1>/FFX/RST ;
933 
  wire \frame_delay_buf_5<1>/FFX/RST ;
934 
  wire \frame_delay_buf_5<1>/FFY/RST ;
935 
  wire \frame_delay_buf_6<1>/FFX/RST ;
936 
  wire \clk_in_BUFGP/BUFG/CE ;
937 
  wire \mpi_clk_BUFGP/BUFG/CE ;
938 
  wire \PWR_VCC_0/GROM ;
939 
  wire \PWR_VCC_0/FROM ;
940 
  wire \PWR_VCC_1/FROM ;
941 
  wire \PWR_VCC_2/FROM ;
942 
  wire \PWR_GND_0/GROM ;
943 
  wire \PWR_GND_1/GROM ;
944 
  wire \PWR_GND_2/GROM ;
945 
  wire \PWR_GND_3/GROM ;
946 
  wire \PWR_GND_4/GROM ;
947 
  wire GND;
948 
  wire VCC;
949 
  wire [1 : 0] frame_delay_buf_7;
950 
  wire [7 : 0] rx_shift_reg_0;
951 
  wire [7 : 0] rx_shift_reg_1;
952 
  wire [7 : 0] rx_shift_reg_2;
953 
  wire [7 : 0] rx_shift_reg_3;
954 
  wire [7 : 0] rx_shift_reg_4;
955 
  wire [7 : 0] rx_shift_reg_5;
956 
  wire [7 : 0] rx_shift_reg_6;
957 
  wire [7 : 0] rx_shift_reg_7;
958 
  wire [8 : 0] frame_cnt;
959 
  wire [4 : 0] c_mem_addr_cnt;
960 
  wire [7 : 0] cd_data;
961 
  wire [8 : 0] mpi_mem_bus_out;
962 
  wire [8 : 8] cd_mem_addr;
963 
  wire [4 : 0] d_mem_addr_cnt;
964 
  wire [2 : 2] _COND_1;
965 
  wire [0 : 0] d_mem_addr;
966 
  wire [15 : 0] data_in_bus;
967 
  wire [7 : 0] data_out_bus;
968 
  wire [7 : 0] rx_buf_reg_1;
969 
  wire [7 : 0] rx_buf_reg_5;
970 
  wire [7 : 0] rx_buf_reg_3;
971 
  wire [7 : 0] rx_buf_reg_7;
972 
  wire [7 : 0] rx_buf_reg_0;
973 
  wire [7 : 0] rx_buf_reg_4;
974 
  wire [7 : 0] rx_buf_reg_2;
975 
  wire [7 : 0] rx_buf_reg_6;
976 
  wire [1 : 0] frame_delay_buf_2;
977 
  wire [1 : 0] frame_delay_buf_3;
978 
  wire [1 : 0] frame_delay_buf_0;
979 
  wire [1 : 0] frame_delay_buf_1;
980 
  wire [1 : 0] frame_delay_buf_6;
981 
  wire [1 : 0] frame_delay_buf_4;
982 
  wire [1 : 0] frame_delay_buf_5;
983 
  wire [3 : 2] _n0246;
984 
  wire [8 : 1] frame_cnt__n0000;
985 
  wire [7 : 0] tx_buf_reg_4;
986 
  wire [7 : 0] tx_buf_reg_5;
987 
  wire [7 : 0] tx_shift_reg_0;
988 
  wire [7 : 0] tx_buf_reg_0;
989 
  wire [7 : 0] tx_shift_reg_1;
990 
  wire [7 : 0] tx_buf_reg_1;
991 
  wire [7 : 0] tx_shift_reg_2;
992 
  wire [7 : 0] tx_buf_reg_2;
993 
  wire [7 : 0] tx_shift_reg_3;
994 
  wire [7 : 0] tx_buf_reg_3;
995 
  wire [7 : 0] tx_shift_reg_4;
996 
  wire [7 : 0] tx_shift_reg_5;
997 
  wire [7 : 0] tx_shift_reg_6;
998 
  wire [7 : 0] tx_buf_reg_6;
999 
  wire [7 : 0] tx_shift_reg_7;
1000 
  wire [7 : 0] tx_buf_reg_7;
1001 
  wire [1 : 0] ctrl_out_reg;
1002 
  wire [4 : 1] d_mem_addr_cnt__n0000;
1003 
  wire [4 : 1] c_mem_addr_cnt__n0000;
1004 
  wire [7 : 1] _n0019;
1005 
  wire [7 : 1] _n0020;
1006 
  wire [7 : 1] _n0021;
1007 
  wire [7 : 1] _n0022;
1008 
  wire [7 : 1] _n0023;
1009 
  wire [7 : 1] _n0024;
1010 
  wire [7 : 1] _n0025;
1011 
  wire [7 : 1] _n0026;
1012 
  wire [1 : 0] _n0046;
1013 
  wire [1 : 0] frame_delay_cnt_0__n0001;
1014 
  wire [1 : 0] frame_delay_cnt_1__n0001;
1015 
  wire [1 : 0] frame_delay_cnt_2__n0001;
1016 
  wire [1 : 0] frame_delay_cnt_3__n0001;
1017 
  wire [1 : 0] frame_delay_cnt_4__n0001;
1018 
  wire [1 : 0] frame_delay_cnt_5__n0001;
1019 
  wire [1 : 0] frame_delay_cnt_6__n0001;
1020 
  wire [1 : 0] frame_delay_cnt_7__n0001;
1021 
  assign
1022 
    GTS_0 = GTS;
1023 
  initial $sdf_annotate("tdm_switch_top_timesim.sdf");
1024 
  X_BUF mpi_addr_1_IBUF_1 (
1025 
    .I(mpi_addr[1]),
1026 
    .O(mpi_addr_1_IBUF)
1027 
  );
1028 
  X_IPAD \mpi_addr<1>/PAD  (
1029 
    .PAD(mpi_addr[1])
1030 
  );
1031 
  X_BUF mpi_addr_0_IBUF_2 (
1032 
    .I(mpi_addr[0]),
1033 
    .O(mpi_addr_0_IBUF)
1034 
  );
1035 
  X_IPAD \mpi_addr<0>/PAD  (
1036 
    .PAD(mpi_addr[0])
1037 
  );
1038 
  X_BUF mpi_data_in_8_IBUF_3 (
1039 
    .I(mpi_data_in[8]),
1040 
    .O(mpi_data_in_8_IBUF)
1041 
  );
1042 
  X_IPAD \mpi_data_in<8>/PAD  (
1043 
    .PAD(mpi_data_in[8])
1044 
  );
1045 
  X_BUF mpi_data_in_7_IBUF_4 (
1046 
    .I(mpi_data_in[7]),
1047 
    .O(mpi_data_in_7_IBUF)
1048 
  );
1049 
  X_IPAD \mpi_data_in<7>/PAD  (
1050 
    .PAD(mpi_data_in[7])
1051 
  );
1052 
  X_BUF mpi_data_in_6_IBUF_5 (
1053 
    .I(mpi_data_in[6]),
1054 
    .O(mpi_data_in_6_IBUF)
1055 
  );
1056 
  X_IPAD \mpi_data_in<6>/PAD  (
1057 
    .PAD(mpi_data_in[6])
1058 
  );
1059 
  X_BUF mpi_data_in_5_IBUF_6 (
1060 
    .I(mpi_data_in[5]),
1061 
    .O(mpi_data_in_5_IBUF)
1062 
  );
1063 
  X_IPAD \mpi_data_in<5>/PAD  (
1064 
    .PAD(mpi_data_in[5])
1065 
  );
1066 
  X_BUF mpi_data_in_4_IBUF_7 (
1067 
    .I(mpi_data_in[4]),
1068 
    .O(mpi_data_in_4_IBUF)
1069 
  );
1070 
  X_IPAD \mpi_data_in<4>/PAD  (
1071 
    .PAD(mpi_data_in[4])
1072 
  );
1073 
  X_BUF mpi_data_in_3_IBUF_8 (
1074 
    .I(mpi_data_in[3]),
1075 
    .O(mpi_data_in_3_IBUF)
1076 
  );
1077 
  X_IPAD \mpi_data_in<3>/PAD  (
1078 
    .PAD(mpi_data_in[3])
1079 
  );
1080 
  X_BUF mpi_data_in_2_IBUF_9 (
1081 
    .I(mpi_data_in[2]),
1082 
    .O(mpi_data_in_2_IBUF)
1083 
  );
1084 
  X_IPAD \mpi_data_in<2>/PAD  (
1085 
    .PAD(mpi_data_in[2])
1086 
  );
1087 
  X_BUF \mpi_data_in<1>/DELAY  (
1088 
    .I(\mpi_data_in<1>/IBUF ),
1089 
    .O(\mpi_data_in<1>/IDELAY )
1090 
  );
1091 
  X_BUF mpi_data_in_1_IBUF_10 (
1092 
    .I(mpi_data_in[1]),
1093 
    .O(\mpi_data_in<1>/IBUF )
1094 
  );
1095 
  X_BUF \mpi_data_in<1>/IMUX  (
1096 
    .I(\mpi_data_in<1>/IBUF ),
1097 
    .O(mpi_data_in_1_IBUF)
1098 
  );
1099 
  X_IPAD \mpi_data_in<1>/PAD  (
1100 
    .PAD(mpi_data_in[1])
1101 
  );
1102 
  X_BUF \mpi_data_in<0>/DELAY  (
1103 
    .I(\mpi_data_in<0>/IBUF ),
1104 
    .O(\mpi_data_in<0>/IDELAY )
1105 
  );
1106 
  X_BUF mpi_data_in_0_IBUF_11 (
1107 
    .I(mpi_data_in[0]),
1108 
    .O(\mpi_data_in<0>/IBUF )
1109 
  );
1110 
  X_BUF \mpi_data_in<0>/IMUX  (
1111 
    .I(\mpi_data_in<0>/IBUF ),
1112 
    .O(mpi_data_in_0_IBUF)
1113 
  );
1114 
  X_IPAD \mpi_data_in<0>/PAD  (
1115 
    .PAD(mpi_data_in[0])
1116 
  );
1117 
  X_BUF \frame_sync/OUTMUX_12  (
1118 
    .I(frame_sync_OBUF),
1119 
    .O(\frame_sync/OUTMUX )
1120 
  );
1121 
  X_BUF \frame_sync/GTS_OR  (
1122 
    .I(GTS_0),
1123 
    .O(\frame_sync/TORGTS )
1124 
  );
1125 
  X_INV \frame_sync/ENABLEINV  (
1126 
    .I(\frame_sync/TORGTS ),
1127 
    .O(\frame_sync/ENABLE )
1128 
  );
1129 
  X_TRI frame_sync_OBUF_13 (
1130 
    .I(\frame_sync/OUTMUX ),
1131 
    .CTL(\frame_sync/ENABLE ),
1132 
    .O(frame_sync)
1133 
  );
1134 
  X_OPAD \frame_sync/PAD  (
1135 
    .PAD(frame_sync)
1136 
  );
1137 
  X_BUF \mpi_data_in<1>/IFF/RSTOR  (
1138 
    .I(GSR),
1139 
    .O(\mpi_data_in<1>/IFF/RST )
1140 
  );
1141 
  X_FF frame_delay_buf_7_1 (
1142 
    .I(\mpi_data_in<1>/IDELAY ),
1143 
    .CE(_n0045),
1144 
    .CLK(mpi_clk_BUFGP),
1145 
    .SET(GND),
1146 
    .RST(\mpi_data_in<1>/IFF/RST ),
1147 
    .O(frame_delay_buf_7[1])
1148 
  );
1149 
  X_BUF \mpi_data_in<0>/IFF/RSTOR  (
1150 
    .I(GSR),
1151 
    .O(\mpi_data_in<0>/IFF/RST )
1152 
  );
1153 
  X_FF frame_delay_buf_7_0 (
1154 
    .I(\mpi_data_in<0>/IDELAY ),
1155 
    .CE(_n0045),
1156 
    .CLK(mpi_clk_BUFGP),
1157 
    .SET(GND),
1158 
    .RST(\mpi_data_in<0>/IFF/RST ),
1159 
    .O(frame_delay_buf_7[0])
1160 
  );
1161 
  X_BUF mpi_addr_2_IBUF_14 (
1162 
    .I(mpi_addr[2]),
1163 
    .O(mpi_addr_2_IBUF)
1164 
  );
1165 
  X_IPAD \mpi_addr<2>/PAD  (
1166 
    .PAD(mpi_addr[2])
1167 
  );
1168 
  X_BUF mpi_addr_3_IBUF_15 (
1169 
    .I(mpi_addr[3]),
1170 
    .O(mpi_addr_3_IBUF)
1171 
  );
1172 
  X_IPAD \mpi_addr<3>/PAD  (
1173 
    .PAD(mpi_addr[3])
1174 
  );
1175 
  X_BUF mpi_addr_4_IBUF_16 (
1176 
    .I(mpi_addr[4]),
1177 
    .O(mpi_addr_4_IBUF)
1178 
  );
1179 
  X_IPAD \mpi_addr<4>/PAD  (
1180 
    .PAD(mpi_addr[4])
1181 
  );
1182 
  X_BUF mpi_addr_5_IBUF_17 (
1183 
    .I(mpi_addr[5]),
1184 
    .O(mpi_addr_5_IBUF)
1185 
  );
1186 
  X_IPAD \mpi_addr<5>/PAD  (
1187 
    .PAD(mpi_addr[5])
1188 
  );
1189 
  X_BUF mpi_addr_6_IBUF_18 (
1190 
    .I(mpi_addr[6]),
1191 
    .O(mpi_addr_6_IBUF)
1192 
  );
1193 
  X_IPAD \mpi_addr<6>/PAD  (
1194 
    .PAD(mpi_addr[6])
1195 
  );
1196 
  X_BUF mpi_addr_7_IBUF_19 (
1197 
    .I(mpi_addr[7]),
1198 
    .O(mpi_addr_7_IBUF)
1199 
  );
1200 
  X_IPAD \mpi_addr<7>/PAD  (
1201 
    .PAD(mpi_addr[7])
1202 
  );
1203 
  X_BUF mpi_addr_8_IBUF_20 (
1204 
    .I(mpi_addr[8]),
1205 
    .O(mpi_addr_8_IBUF)
1206 
  );
1207 
  X_IPAD \mpi_addr<8>/PAD  (
1208 
    .PAD(mpi_addr[8])
1209 
  );
1210 
  X_BUF reset_IBUF_21 (
1211 
    .I(reset),
1212 
    .O(reset_IBUF)
1213 
  );
1214 
  X_IPAD \reset/PAD  (
1215 
    .PAD(reset)
1216 
  );
1217 
  X_INV \mpi_data_out<0>/TRIMUX  (
1218 
    .I(mpi_cs_IBUF),
1219 
    .O(\mpi_data_out<0>/TDATANOT )
1220 
  );
1221 
  X_BUF \mpi_data_out<0>/OUTMUX_22  (
1222 
    .I(\ctrl_out_reg<0>/FROM ),
1223 
    .O(\mpi_data_out<0>/OUTMUX )
1224 
  );
1225 
  X_OR2 \mpi_data_out<0>/GTS_OR  (
1226 
    .I0(GTS_0),
1227 
    .I1(\mpi_data_out<0>/TDATANOT ),
1228 
    .O(\mpi_data_out<0>/TORGTS )
1229 
  );
1230 
  X_INV \mpi_data_out<0>/ENABLEINV  (
1231 
    .I(\mpi_data_out<0>/TORGTS ),
1232 
    .O(\mpi_data_out<0>/ENABLE )
1233 
  );
1234 
  X_TRI mpi_data_out_0_OBUFT (
1235 
    .I(\mpi_data_out<0>/OUTMUX ),
1236 
    .CTL(\mpi_data_out<0>/ENABLE ),
1237 
    .O(mpi_data_out[0])
1238 
  );
1239 
  X_OPAD \mpi_data_out<0>/PAD  (
1240 
    .PAD(mpi_data_out[0])
1241 
  );
1242 
  X_INV \mpi_data_out<1>/TRIMUX  (
1243 
    .I(mpi_cs_IBUF),
1244 
    .O(\mpi_data_out<1>/TDATANOT )
1245 
  );
1246 
  X_BUF \mpi_data_out<1>/OUTMUX_23  (
1247 
    .I(\mpi_data_out_4_OBUFT/GROM ),
1248 
    .O(\mpi_data_out<1>/OUTMUX )
1249 
  );
1250 
  X_OR2 \mpi_data_out<1>/GTS_OR  (
1251 
    .I0(GTS_0),
1252 
    .I1(\mpi_data_out<1>/TDATANOT ),
1253 
    .O(\mpi_data_out<1>/TORGTS )
1254 
  );
1255 
  X_INV \mpi_data_out<1>/ENABLEINV  (
1256 
    .I(\mpi_data_out<1>/TORGTS ),
1257 
    .O(\mpi_data_out<1>/ENABLE )
1258 
  );
1259 
  X_TRI mpi_data_out_1_OBUFT (
1260 
    .I(\mpi_data_out<1>/OUTMUX ),
1261 
    .CTL(\mpi_data_out<1>/ENABLE ),
1262 
    .O(mpi_data_out[1])
1263 
  );
1264 
  X_OPAD \mpi_data_out<1>/PAD  (
1265 
    .PAD(mpi_data_out[1])
1266 
  );
1267 
  X_INV \mpi_data_out<2>/TRIMUX  (
1268 
    .I(mpi_cs_IBUF),
1269 
    .O(\mpi_data_out<2>/TDATANOT )
1270 
  );
1271 
  X_BUF \mpi_data_out<2>/OUTMUX_24  (
1272 
    .I(\mpi_data_out_5_OBUFT/GROM ),
1273 
    .O(\mpi_data_out<2>/OUTMUX )
1274 
  );
1275 
  X_OR2 \mpi_data_out<2>/GTS_OR  (
1276 
    .I0(GTS_0),
1277 
    .I1(\mpi_data_out<2>/TDATANOT ),
1278 
    .O(\mpi_data_out<2>/TORGTS )
1279 
  );
1280 
  X_INV \mpi_data_out<2>/ENABLEINV  (
1281 
    .I(\mpi_data_out<2>/TORGTS ),
1282 
    .O(\mpi_data_out<2>/ENABLE )
1283 
  );
1284 
  X_TRI mpi_data_out_2_OBUFT (
1285 
    .I(\mpi_data_out<2>/OUTMUX ),
1286 
    .CTL(\mpi_data_out<2>/ENABLE ),
1287 
    .O(mpi_data_out[2])
1288 
  );
1289 
  X_OPAD \mpi_data_out<2>/PAD  (
1290 
    .PAD(mpi_data_out[2])
1291 
  );
1292 
  X_INV \mpi_data_out<3>/TRIMUX  (
1293 
    .I(mpi_cs_IBUF),
1294 
    .O(\mpi_data_out<3>/TDATANOT )
1295 
  );
1296 
  X_BUF \mpi_data_out<3>/OUTMUX_25  (
1297 
    .I(\mpi_data_out_3_OBUFT/FROM ),
1298 
    .O(\mpi_data_out<3>/OUTMUX )
1299 
  );
1300 
  X_OR2 \mpi_data_out<3>/GTS_OR  (
1301 
    .I0(GTS_0),
1302 
    .I1(\mpi_data_out<3>/TDATANOT ),
1303 
    .O(\mpi_data_out<3>/TORGTS )
1304 
  );
1305 
  X_INV \mpi_data_out<3>/ENABLEINV  (
1306 
    .I(\mpi_data_out<3>/TORGTS ),
1307 
    .O(\mpi_data_out<3>/ENABLE )
1308 
  );
1309 
  X_TRI mpi_data_out_3_OBUFT (
1310 
    .I(\mpi_data_out<3>/OUTMUX ),
1311 
    .CTL(\mpi_data_out<3>/ENABLE ),
1312 
    .O(mpi_data_out[3])
1313 
  );
1314 
  X_OPAD \mpi_data_out<3>/PAD  (
1315 
    .PAD(mpi_data_out[3])
1316 
  );
1317 
  X_INV \mpi_data_out<4>/TRIMUX  (
1318 
    .I(mpi_cs_IBUF),
1319 
    .O(\mpi_data_out<4>/TDATANOT )
1320 
  );
1321 
  X_BUF \mpi_data_out<4>/OUTMUX_26  (
1322 
    .I(\mpi_data_out_4_OBUFT/FROM ),
1323 
    .O(\mpi_data_out<4>/OUTMUX )
1324 
  );
1325 
  X_OR2 \mpi_data_out<4>/GTS_OR  (
1326 
    .I0(GTS_0),
1327 
    .I1(\mpi_data_out<4>/TDATANOT ),
1328 
    .O(\mpi_data_out<4>/TORGTS )
1329 
  );
1330 
  X_INV \mpi_data_out<4>/ENABLEINV  (
1331 
    .I(\mpi_data_out<4>/TORGTS ),
1332 
    .O(\mpi_data_out<4>/ENABLE )
1333 
  );
1334 
  X_TRI mpi_data_out_4_OBUFT (
1335 
    .I(\mpi_data_out<4>/OUTMUX ),
1336 
    .CTL(\mpi_data_out<4>/ENABLE ),
1337 
    .O(mpi_data_out[4])
1338 
  );
1339 
  X_OPAD \mpi_data_out<4>/PAD  (
1340 
    .PAD(mpi_data_out[4])
1341 
  );
1342 
  X_INV \mpi_data_out<5>/TRIMUX  (
1343 
    .I(mpi_cs_IBUF),
1344 
    .O(\mpi_data_out<5>/TDATANOT )
1345 
  );
1346 
  X_BUF \mpi_data_out<5>/OUTMUX_27  (
1347 
    .I(\mpi_data_out_5_OBUFT/FROM ),
1348 
    .O(\mpi_data_out<5>/OUTMUX )
1349 
  );
1350 
  X_OR2 \mpi_data_out<5>/GTS_OR  (
1351 
    .I0(GTS_0),
1352 
    .I1(\mpi_data_out<5>/TDATANOT ),
1353 
    .O(\mpi_data_out<5>/TORGTS )
1354 
  );
1355 
  X_INV \mpi_data_out<5>/ENABLEINV  (
1356 
    .I(\mpi_data_out<5>/TORGTS ),
1357 
    .O(\mpi_data_out<5>/ENABLE )
1358 
  );
1359 
  X_TRI mpi_data_out_5_OBUFT (
1360 
    .I(\mpi_data_out<5>/OUTMUX ),
1361 
    .CTL(\mpi_data_out<5>/ENABLE ),
1362 
    .O(mpi_data_out[5])
1363 
  );
1364 
  X_OPAD \mpi_data_out<5>/PAD  (
1365 
    .PAD(mpi_data_out[5])
1366 
  );
1367 
  X_INV \mpi_data_out<6>/TRIMUX  (
1368 
    .I(mpi_cs_IBUF),
1369 
    .O(\mpi_data_out<6>/TDATANOT )
1370 
  );
1371 
  X_BUF \mpi_data_out<6>/OUTMUX_28  (
1372 
    .I(\ram_en/GROM ),
1373 
    .O(\mpi_data_out<6>/OUTMUX )
1374 
  );
1375 
  X_OR2 \mpi_data_out<6>/GTS_OR  (
1376 
    .I0(GTS_0),
1377 
    .I1(\mpi_data_out<6>/TDATANOT ),
1378 
    .O(\mpi_data_out<6>/TORGTS )
1379 
  );
1380 
  X_INV \mpi_data_out<6>/ENABLEINV  (
1381 
    .I(\mpi_data_out<6>/TORGTS ),
1382 
    .O(\mpi_data_out<6>/ENABLE )
1383 
  );
1384 
  X_TRI mpi_data_out_6_OBUFT (
1385 
    .I(\mpi_data_out<6>/OUTMUX ),
1386 
    .CTL(\mpi_data_out<6>/ENABLE ),
1387 
    .O(mpi_data_out[6])
1388 
  );
1389 
  X_OPAD \mpi_data_out<6>/PAD  (
1390 
    .PAD(mpi_data_out[6])
1391 
  );
1392 
  X_INV \mpi_data_out<7>/TRIMUX  (
1393 
    .I(mpi_cs_IBUF),
1394 
    .O(\mpi_data_out<7>/TDATANOT )
1395 
  );
1396 
  X_BUF \mpi_data_out<7>/OUTMUX_29  (
1397 
    .I(\mpi_data_out_7_OBUFT/GROM ),
1398 
    .O(\mpi_data_out<7>/OUTMUX )
1399 
  );
1400 
  X_OR2 \mpi_data_out<7>/GTS_OR  (
1401 
    .I0(GTS_0),
1402 
    .I1(\mpi_data_out<7>/TDATANOT ),
1403 
    .O(\mpi_data_out<7>/TORGTS )
1404 
  );
1405 
  X_INV \mpi_data_out<7>/ENABLEINV  (
1406 
    .I(\mpi_data_out<7>/TORGTS ),
1407 
    .O(\mpi_data_out<7>/ENABLE )
1408 
  );
1409 
  X_TRI mpi_data_out_7_OBUFT (
1410 
    .I(\mpi_data_out<7>/OUTMUX ),
1411 
    .CTL(\mpi_data_out<7>/ENABLE ),
1412 
    .O(mpi_data_out[7])
1413 
  );
1414 
  X_OPAD \mpi_data_out<7>/PAD  (
1415 
    .PAD(mpi_data_out[7])
1416 
  );
1417 
  X_INV \mpi_data_out<8>/TRIMUX  (
1418 
    .I(mpi_cs_IBUF),
1419 
    .O(\mpi_data_out<8>/TDATANOT )
1420 
  );
1421 
  X_BUF \mpi_data_out<8>/OUTMUX_30  (
1422 
    .I(\mpi_data_out_3_OBUFT/GROM ),
1423 
    .O(\mpi_data_out<8>/OUTMUX )
1424 
  );
1425 
  X_OR2 \mpi_data_out<8>/GTS_OR  (
1426 
    .I0(GTS_0),
1427 
    .I1(\mpi_data_out<8>/TDATANOT ),
1428 
    .O(\mpi_data_out<8>/TORGTS )
1429 
  );
1430 
  X_INV \mpi_data_out<8>/ENABLEINV  (
1431 
    .I(\mpi_data_out<8>/TORGTS ),
1432 
    .O(\mpi_data_out<8>/ENABLE )
1433 
  );
1434 
  X_TRI mpi_data_out_8_OBUFT (
1435 
    .I(\mpi_data_out<8>/OUTMUX ),
1436 
    .CTL(\mpi_data_out<8>/ENABLE ),
1437 
    .O(mpi_data_out[8])
1438 
  );
1439 
  X_OPAD \mpi_data_out<8>/PAD  (
1440 
    .PAD(mpi_data_out[8])
1441 
  );
1442 
  X_BUF \rx_stream<0>/DELAY  (
1443 
    .I(rx_stream_0_IBUF),
1444 
    .O(\rx_stream<0>/IDELAY )
1445 
  );
1446 
  X_BUF rx_stream_0_IBUF_31 (
1447 
    .I(rx_stream[0]),
1448 
    .O(rx_stream_0_IBUF)
1449 
  );
1450 
  X_INV \rx_stream<0>/ICKINV  (
1451 
    .I(div_reg_2),
1452 
    .O(\rx_stream<0>/ICLKNOT )
1453 
  );
1454 
  X_IPAD \rx_stream<0>/PAD  (
1455 
    .PAD(rx_stream[0])
1456 
  );
1457 
  X_BUF \rx_stream<0>/IFF/RSTOR  (
1458 
    .I(GSR),
1459 
    .O(\rx_stream<0>/IFF/RST )
1460 
  );
1461 
  X_FF rx_shift_reg_0_7 (
1462 
    .I(\rx_stream<0>/IDELAY ),
1463 
    .CE(VCC),
1464 
    .CLK(\rx_stream<0>/ICLKNOT ),
1465 
    .SET(GND),
1466 
    .RST(\rx_stream<0>/IFF/RST ),
1467 
    .O(rx_shift_reg_0[7])
1468 
  );
1469 
  X_BUF \rx_stream<1>/DELAY  (
1470 
    .I(rx_stream_1_IBUF),
1471 
    .O(\rx_stream<1>/IDELAY )
1472 
  );
1473 
  X_BUF rx_stream_1_IBUF_32 (
1474 
    .I(rx_stream[1]),
1475 
    .O(rx_stream_1_IBUF)
1476 
  );
1477 
  X_INV \rx_stream<1>/ICKINV  (
1478 
    .I(div_reg_2),
1479 
    .O(\rx_stream<1>/ICLKNOT )
1480 
  );
1481 
  X_IPAD \rx_stream<1>/PAD  (
1482 
    .PAD(rx_stream[1])
1483 
  );
1484 
  X_BUF \rx_stream<1>/IFF/RSTOR  (
1485 
    .I(GSR),
1486 
    .O(\rx_stream<1>/IFF/RST )
1487 
  );
1488 
  X_FF rx_shift_reg_1_7 (
1489 
    .I(\rx_stream<1>/IDELAY ),
1490 
    .CE(VCC),
1491 
    .CLK(\rx_stream<1>/ICLKNOT ),
1492 
    .SET(GND),
1493 
    .RST(\rx_stream<1>/IFF/RST ),
1494 
    .O(rx_shift_reg_1[7])
1495 
  );
1496 
  X_BUF \rx_stream<2>/DELAY  (
1497 
    .I(rx_stream_2_IBUF),
1498 
    .O(\rx_stream<2>/IDELAY )
1499 
  );
1500 
  X_BUF rx_stream_2_IBUF_33 (
1501 
    .I(rx_stream[2]),
1502 
    .O(rx_stream_2_IBUF)
1503 
  );
1504 
  X_INV \rx_stream<2>/ICKINV  (
1505 
    .I(div_reg_2),
1506 
    .O(\rx_stream<2>/ICLKNOT )
1507 
  );
1508 
  X_IPAD \rx_stream<2>/PAD  (
1509 
    .PAD(rx_stream[2])
1510 
  );
1511 
  X_BUF \rx_stream<2>/IFF/RSTOR  (
1512 
    .I(GSR),
1513 
    .O(\rx_stream<2>/IFF/RST )
1514 
  );
1515 
  X_FF rx_shift_reg_2_7 (
1516 
    .I(\rx_stream<2>/IDELAY ),
1517 
    .CE(VCC),
1518 
    .CLK(\rx_stream<2>/ICLKNOT ),
1519 
    .SET(GND),
1520 
    .RST(\rx_stream<2>/IFF/RST ),
1521 
    .O(rx_shift_reg_2[7])
1522 
  );
1523 
  X_BUF \rx_stream<3>/DELAY  (
1524 
    .I(rx_stream_3_IBUF),
1525 
    .O(\rx_stream<3>/IDELAY )
1526 
  );
1527 
  X_BUF rx_stream_3_IBUF_34 (
1528 
    .I(rx_stream[3]),
1529 
    .O(rx_stream_3_IBUF)
1530 
  );
1531 
  X_INV \rx_stream<3>/ICKINV  (
1532 
    .I(div_reg_2),
1533 
    .O(\rx_stream<3>/ICLKNOT )
1534 
  );
1535 
  X_IPAD \rx_stream<3>/PAD  (
1536 
    .PAD(rx_stream[3])
1537 
  );
1538 
  X_BUF \rx_stream<3>/IFF/RSTOR  (
1539 
    .I(GSR),
1540 
    .O(\rx_stream<3>/IFF/RST )
1541 
  );
1542 
  X_FF rx_shift_reg_3_7 (
1543 
    .I(\rx_stream<3>/IDELAY ),
1544 
    .CE(VCC),
1545 
    .CLK(\rx_stream<3>/ICLKNOT ),
1546 
    .SET(GND),
1547 
    .RST(\rx_stream<3>/IFF/RST ),
1548 
    .O(rx_shift_reg_3[7])
1549 
  );
1550 
  X_BUF \rx_stream<4>/DELAY  (
1551 
    .I(rx_stream_4_IBUF),
1552 
    .O(\rx_stream<4>/IDELAY )
1553 
  );
1554 
  X_BUF rx_stream_4_IBUF_35 (
1555 
    .I(rx_stream[4]),
1556 
    .O(rx_stream_4_IBUF)
1557 
  );
1558 
  X_INV \rx_stream<4>/ICKINV  (
1559 
    .I(div_reg_2),
1560 
    .O(\rx_stream<4>/ICLKNOT )
1561 
  );
1562 
  X_IPAD \rx_stream<4>/PAD  (
1563 
    .PAD(rx_stream[4])
1564 
  );
1565 
  X_BUF \rx_stream<4>/IFF/RSTOR  (
1566 
    .I(GSR),
1567 
    .O(\rx_stream<4>/IFF/RST )
1568 
  );
1569 
  X_FF rx_shift_reg_4_7 (
1570 
    .I(\rx_stream<4>/IDELAY ),
1571 
    .CE(VCC),
1572 
    .CLK(\rx_stream<4>/ICLKNOT ),
1573 
    .SET(GND),
1574 
    .RST(\rx_stream<4>/IFF/RST ),
1575 
    .O(rx_shift_reg_4[7])
1576 
  );
1577 
  X_BUF \rx_stream<5>/DELAY  (
1578 
    .I(rx_stream_5_IBUF),
1579 
    .O(\rx_stream<5>/IDELAY )
1580 
  );
1581 
  X_BUF rx_stream_5_IBUF_36 (
1582 
    .I(rx_stream[5]),
1583 
    .O(rx_stream_5_IBUF)
1584 
  );
1585 
  X_INV \rx_stream<5>/ICKINV  (
1586 
    .I(div_reg_2),
1587 
    .O(\rx_stream<5>/ICLKNOT )
1588 
  );
1589 
  X_IPAD \rx_stream<5>/PAD  (
1590 
    .PAD(rx_stream[5])
1591 
  );
1592 
  X_BUF \rx_stream<5>/IFF/RSTOR  (
1593 
    .I(GSR),
1594 
    .O(\rx_stream<5>/IFF/RST )
1595 
  );
1596 
  X_FF rx_shift_reg_5_7 (
1597 
    .I(\rx_stream<5>/IDELAY ),
1598 
    .CE(VCC),
1599 
    .CLK(\rx_stream<5>/ICLKNOT ),
1600 
    .SET(GND),
1601 
    .RST(\rx_stream<5>/IFF/RST ),
1602 
    .O(rx_shift_reg_5[7])
1603 
  );
1604 
  X_BUF \rx_stream<6>/DELAY  (
1605 
    .I(rx_stream_6_IBUF),
1606 
    .O(\rx_stream<6>/IDELAY )
1607 
  );
1608 
  X_BUF rx_stream_6_IBUF_37 (
1609 
    .I(rx_stream[6]),
1610 
    .O(rx_stream_6_IBUF)
1611 
  );
1612 
  X_INV \rx_stream<6>/ICKINV  (
1613 
    .I(div_reg_2),
1614 
    .O(\rx_stream<6>/ICLKNOT )
1615 
  );
1616 
  X_IPAD \rx_stream<6>/PAD  (
1617 
    .PAD(rx_stream[6])
1618 
  );
1619 
  X_BUF \rx_stream<6>/IFF/RSTOR  (
1620 
    .I(GSR),
1621 
    .O(\rx_stream<6>/IFF/RST )
1622 
  );
1623 
  X_FF rx_shift_reg_6_7 (
1624 
    .I(\rx_stream<6>/IDELAY ),
1625 
    .CE(VCC),
1626 
    .CLK(\rx_stream<6>/ICLKNOT ),
1627 
    .SET(GND),
1628 
    .RST(\rx_stream<6>/IFF/RST ),
1629 
    .O(rx_shift_reg_6[7])
1630 
  );
1631 
  X_BUF \rx_stream<7>/DELAY  (
1632 
    .I(rx_stream_7_IBUF),
1633 
    .O(\rx_stream<7>/IDELAY )
1634 
  );
1635 
  X_BUF rx_stream_7_IBUF_38 (
1636 
    .I(rx_stream[7]),
1637 
    .O(rx_stream_7_IBUF)
1638 
  );
1639 
  X_INV \rx_stream<7>/ICKINV  (
1640 
    .I(div_reg_1),
1641 
    .O(\rx_stream<7>/ICLKNOT )
1642 
  );
1643 
  X_IPAD \rx_stream<7>/PAD  (
1644 
    .PAD(rx_stream[7])
1645 
  );
1646 
  X_BUF \rx_stream<7>/IFF/RSTOR  (
1647 
    .I(GSR),
1648 
    .O(\rx_stream<7>/IFF/RST )
1649 
  );
1650 
  X_FF rx_shift_reg_7_7 (
1651 
    .I(\rx_stream<7>/IDELAY ),
1652 
    .CE(VCC),
1653 
    .CLK(\rx_stream<7>/ICLKNOT ),
1654 
    .SET(GND),
1655 
    .RST(\rx_stream<7>/IFF/RST ),
1656 
    .O(rx_shift_reg_7[7])
1657 
  );
1658 
  X_BUF \tx_stream<0>/OMUX  (
1659 
    .I(\_n0019<0>/FROM ),
1660 
    .O(\tx_stream<0>/OD )
1661 
  );
1662 
  X_BUF \tx_stream<0>/OUTMUX_39  (
1663 
    .I(tx_shift_reg_0[0]),
1664 
    .O(\tx_stream<0>/OUTMUX )
1665 
  );
1666 
  X_BUF \tx_stream<0>/GTS_OR  (
1667 
    .I(GTS_0),
1668 
    .O(\tx_stream<0>/TORGTS )
1669 
  );
1670 
  X_INV \tx_stream<0>/ENABLEINV  (
1671 
    .I(\tx_stream<0>/TORGTS ),
1672 
    .O(\tx_stream<0>/ENABLE )
1673 
  );
1674 
  X_TRI tx_stream_0_OBUF (
1675 
    .I(\tx_stream<0>/OUTMUX ),
1676 
    .CTL(\tx_stream<0>/ENABLE ),
1677 
    .O(tx_stream[0])
1678 
  );
1679 
  X_OPAD \tx_stream<0>/PAD  (
1680 
    .PAD(tx_stream[0])
1681 
  );
1682 
  X_BUF \tx_stream<0>/OFF/RSTOR  (
1683 
    .I(GSR),
1684 
    .O(\tx_stream<0>/OFF/RST )
1685 
  );
1686 
  X_FF tx_shift_reg_0_0 (
1687 
    .I(\tx_stream<0>/OD ),
1688 
    .CE(VCC),
1689 
    .CLK(div_reg_1),
1690 
    .SET(GND),
1691 
    .RST(\tx_stream<0>/OFF/RST ),
1692 
    .O(tx_shift_reg_0[0])
1693 
  );
1694 
  X_BUF \tx_stream<1>/OMUX  (
1695 
    .I(\_n0019<0>/GROM ),
1696 
    .O(\tx_stream<1>/OD )
1697 
  );
1698 
  X_BUF \tx_stream<1>/OUTMUX_40  (
1699 
    .I(tx_shift_reg_1[0]),
1700 
    .O(\tx_stream<1>/OUTMUX )
1701 
  );
1702 
  X_BUF \tx_stream<1>/GTS_OR  (
1703 
    .I(GTS_0),
1704 
    .O(\tx_stream<1>/TORGTS )
1705 
  );
1706 
  X_INV \tx_stream<1>/ENABLEINV  (
1707 
    .I(\tx_stream<1>/TORGTS ),
1708 
    .O(\tx_stream<1>/ENABLE )
1709 
  );
1710 
  X_TRI tx_stream_1_OBUF (
1711 
    .I(\tx_stream<1>/OUTMUX ),
1712 
    .CTL(\tx_stream<1>/ENABLE ),
1713 
    .O(tx_stream[1])
1714 
  );
1715 
  X_OPAD \tx_stream<1>/PAD  (
1716 
    .PAD(tx_stream[1])
1717 
  );
1718 
  X_BUF \tx_stream<1>/OFF/RSTOR  (
1719 
    .I(GSR),
1720 
    .O(\tx_stream<1>/OFF/RST )
1721 
  );
1722 
  X_FF tx_shift_reg_1_0 (
1723 
    .I(\tx_stream<1>/OD ),
1724 
    .CE(VCC),
1725 
    .CLK(div_reg_1),
1726 
    .SET(GND),
1727 
    .RST(\tx_stream<1>/OFF/RST ),
1728 
    .O(tx_shift_reg_1[0])
1729 
  );
1730 
  X_BUF \tx_stream<2>/OMUX  (
1731 
    .I(\_n0022<0>/GROM ),
1732 
    .O(\tx_stream<2>/OD )
1733 
  );
1734 
  X_BUF \tx_stream<2>/OUTMUX_41  (
1735 
    .I(tx_shift_reg_2[0]),
1736 
    .O(\tx_stream<2>/OUTMUX )
1737 
  );
1738 
  X_BUF \tx_stream<2>/GTS_OR  (
1739 
    .I(GTS_0),
1740 
    .O(\tx_stream<2>/TORGTS )
1741 
  );
1742 
  X_INV \tx_stream<2>/ENABLEINV  (
1743 
    .I(\tx_stream<2>/TORGTS ),
1744 
    .O(\tx_stream<2>/ENABLE )
1745 
  );
1746 
  X_TRI tx_stream_2_OBUF (
1747 
    .I(\tx_stream<2>/OUTMUX ),
1748 
    .CTL(\tx_stream<2>/ENABLE ),
1749 
    .O(tx_stream[2])
1750 
  );
1751 
  X_OPAD \tx_stream<2>/PAD  (
1752 
    .PAD(tx_stream[2])
1753 
  );
1754 
  X_BUF \tx_stream<2>/OFF/RSTOR  (
1755 
    .I(GSR),
1756 
    .O(\tx_stream<2>/OFF/RST )
1757 
  );
1758 
  X_FF tx_shift_reg_2_0 (
1759 
    .I(\tx_stream<2>/OD ),
1760 
    .CE(VCC),
1761 
    .CLK(div_reg_1),
1762 
    .SET(GND),
1763 
    .RST(\tx_stream<2>/OFF/RST ),
1764 
    .O(tx_shift_reg_2[0])
1765 
  );
1766 
  X_BUF \tx_stream<3>/OMUX  (
1767 
    .I(\_n0022<0>/FROM ),
1768 
    .O(\tx_stream<3>/OD )
1769 
  );
1770 
  X_BUF \tx_stream<3>/OUTMUX_42  (
1771 
    .I(tx_shift_reg_3[0]),
1772 
    .O(\tx_stream<3>/OUTMUX )
1773 
  );
1774 
  X_BUF \tx_stream<3>/GTS_OR  (
1775 
    .I(GTS_0),
1776 
    .O(\tx_stream<3>/TORGTS )
1777 
  );
1778 
  X_INV \tx_stream<3>/ENABLEINV  (
1779 
    .I(\tx_stream<3>/TORGTS ),
1780 
    .O(\tx_stream<3>/ENABLE )
1781 
  );
1782 
  X_TRI tx_stream_3_OBUF (
1783 
    .I(\tx_stream<3>/OUTMUX ),
1784 
    .CTL(\tx_stream<3>/ENABLE ),
1785 
    .O(tx_stream[3])
1786 
  );
1787 
  X_OPAD \tx_stream<3>/PAD  (
1788 
    .PAD(tx_stream[3])
1789 
  );
1790 
  X_BUF \tx_stream<3>/OFF/RSTOR  (
1791 
    .I(GSR),
1792 
    .O(\tx_stream<3>/OFF/RST )
1793 
  );
1794 
  X_FF tx_shift_reg_3_0 (
1795 
    .I(\tx_stream<3>/OD ),
1796 
    .CE(VCC),
1797 
    .CLK(div_reg_1),
1798 
    .SET(GND),
1799 
    .RST(\tx_stream<3>/OFF/RST ),
1800 
    .O(tx_shift_reg_3[0])
1801 
  );
1802 
  X_BUF \tx_stream<4>/OMUX  (
1803 
    .I(\_n0024<0>/GROM ),
1804 
    .O(\tx_stream<4>/OD )
1805 
  );
1806 
  X_BUF \tx_stream<4>/OUTMUX_43  (
1807 
    .I(tx_shift_reg_4[0]),
1808 
    .O(\tx_stream<4>/OUTMUX )
1809 
  );
1810 
  X_BUF \tx_stream<4>/GTS_OR  (
1811 
    .I(GTS_0),
1812 
    .O(\tx_stream<4>/TORGTS )
1813 
  );
1814 
  X_INV \tx_stream<4>/ENABLEINV  (
1815 
    .I(\tx_stream<4>/TORGTS ),
1816 
    .O(\tx_stream<4>/ENABLE )
1817 
  );
1818 
  X_TRI tx_stream_4_OBUF (
1819 
    .I(\tx_stream<4>/OUTMUX ),
1820 
    .CTL(\tx_stream<4>/ENABLE ),
1821 
    .O(tx_stream[4])
1822 
  );
1823 
  X_OPAD \tx_stream<4>/PAD  (
1824 
    .PAD(tx_stream[4])
1825 
  );
1826 
  X_BUF \tx_stream<4>/OFF/RSTOR  (
1827 
    .I(GSR),
1828 
    .O(\tx_stream<4>/OFF/RST )
1829 
  );
1830 
  X_FF tx_shift_reg_4_0 (
1831 
    .I(\tx_stream<4>/OD ),
1832 
    .CE(VCC),
1833 
    .CLK(div_reg_1),
1834 
    .SET(GND),
1835 
    .RST(\tx_stream<4>/OFF/RST ),
1836 
    .O(tx_shift_reg_4[0])
1837 
  );
1838 
  X_BUF \tx_stream<5>/OMUX  (
1839 
    .I(\_n0024<0>/FROM ),
1840 
    .O(\tx_stream<5>/OD )
1841 
  );
1842 
  X_BUF \tx_stream<5>/OUTMUX_44  (
1843 
    .I(tx_shift_reg_5[0]),
1844 
    .O(\tx_stream<5>/OUTMUX )
1845 
  );
1846 
  X_BUF \tx_stream<5>/GTS_OR  (
1847 
    .I(GTS_0),
1848 
    .O(\tx_stream<5>/TORGTS )
1849 
  );
1850 
  X_INV \tx_stream<5>/ENABLEINV  (
1851 
    .I(\tx_stream<5>/TORGTS ),
1852 
    .O(\tx_stream<5>/ENABLE )
1853 
  );
1854 
  X_TRI tx_stream_5_OBUF (
1855 
    .I(\tx_stream<5>/OUTMUX ),
1856 
    .CTL(\tx_stream<5>/ENABLE ),
1857 
    .O(tx_stream[5])
1858 
  );
1859 
  X_OPAD \tx_stream<5>/PAD  (
1860 
    .PAD(tx_stream[5])
1861 
  );
1862 
  X_BUF \tx_stream<5>/OFF/RSTOR  (
1863 
    .I(GSR),
1864 
    .O(\tx_stream<5>/OFF/RST )
1865 
  );
1866 
  X_FF tx_shift_reg_5_0 (
1867 
    .I(\tx_stream<5>/OD ),
1868 
    .CE(VCC),
1869 
    .CLK(div_reg_1),
1870 
    .SET(GND),
1871 
    .RST(\tx_stream<5>/OFF/RST ),
1872 
    .O(tx_shift_reg_5[0])
1873 
  );
1874 
  X_BUF \tx_stream<6>/OMUX  (
1875 
    .I(\_n0026<0>/GROM ),
1876 
    .O(\tx_stream<6>/OD )
1877 
  );
1878 
  X_BUF \tx_stream<6>/OUTMUX_45  (
1879 
    .I(tx_shift_reg_6[0]),
1880 
    .O(\tx_stream<6>/OUTMUX )
1881 
  );
1882 
  X_BUF \tx_stream<6>/GTS_OR  (
1883 
    .I(GTS_0),
1884 
    .O(\tx_stream<6>/TORGTS )
1885 
  );
1886 
  X_INV \tx_stream<6>/ENABLEINV  (
1887 
    .I(\tx_stream<6>/TORGTS ),
1888 
    .O(\tx_stream<6>/ENABLE )
1889 
  );
1890 
  X_TRI tx_stream_6_OBUF (
1891 
    .I(\tx_stream<6>/OUTMUX ),
1892 
    .CTL(\tx_stream<6>/ENABLE ),
1893 
    .O(tx_stream[6])
1894 
  );
1895 
  X_OPAD \tx_stream<6>/PAD  (
1896 
    .PAD(tx_stream[6])
1897 
  );
1898 
  X_BUF \tx_stream<6>/OFF/RSTOR  (
1899 
    .I(GSR),
1900 
    .O(\tx_stream<6>/OFF/RST )
1901 
  );
1902 
  X_FF tx_shift_reg_6_0 (
1903 
    .I(\tx_stream<6>/OD ),
1904 
    .CE(VCC),
1905 
    .CLK(div_reg_1),
1906 
    .SET(GND),
1907 
    .RST(\tx_stream<6>/OFF/RST ),
1908 
    .O(tx_shift_reg_6[0])
1909 
  );
1910 
  X_BUF \tx_stream<7>/OMUX  (
1911 
    .I(\_n0026<0>/FROM ),
1912 
    .O(\tx_stream<7>/OD )
1913 
  );
1914 
  X_BUF \tx_stream<7>/OUTMUX_46  (
1915 
    .I(tx_shift_reg_7[0]),
1916 
    .O(\tx_stream<7>/OUTMUX )
1917 
  );
1918 
  X_BUF \tx_stream<7>/GTS_OR  (
1919 
    .I(GTS_0),
1920 
    .O(\tx_stream<7>/TORGTS )
1921 
  );
1922 
  X_INV \tx_stream<7>/ENABLEINV  (
1923 
    .I(\tx_stream<7>/TORGTS ),
1924 
    .O(\tx_stream<7>/ENABLE )
1925 
  );
1926 
  X_TRI tx_stream_7_OBUF (
1927 
    .I(\tx_stream<7>/OUTMUX ),
1928 
    .CTL(\tx_stream<7>/ENABLE ),
1929 
    .O(tx_stream[7])
1930 
  );
1931 
  X_OPAD \tx_stream<7>/PAD  (
1932 
    .PAD(tx_stream[7])
1933 
  );
1934 
  X_BUF \tx_stream<7>/OFF/RSTOR  (
1935 
    .I(GSR),
1936 
    .O(\tx_stream<7>/OFF/RST )
1937 
  );
1938 
  X_FF tx_shift_reg_7_0 (
1939 
    .I(\tx_stream<7>/OD ),
1940 
    .CE(VCC),
1941 
    .CLK(div_reg_1),
1942 
    .SET(GND),
1943 
    .RST(\tx_stream<7>/OFF/RST ),
1944 
    .O(tx_shift_reg_7[0])
1945 
  );
1946 
  X_BUF mpi_cs_IBUF_47 (
1947 
    .I(mpi_cs),
1948 
    .O(mpi_cs_IBUF)
1949 
  );
1950 
  X_IPAD \mpi_cs/PAD  (
1951 
    .PAD(mpi_cs)
1952 
  );
1953 
  X_BUF mpi_rw_IBUF_48 (
1954 
    .I(mpi_rw),
1955 
    .O(mpi_rw_IBUF)
1956 
  );
1957 
  X_IPAD \mpi_rw/PAD  (
1958 
    .PAD(mpi_rw)
1959 
  );
1960 
  X_BUF \clk_out/OUTMUX_49  (
1961 
    .I(div_reg),
1962 
    .O(\clk_out/OUTMUX )
1963 
  );
1964 
  X_BUF \clk_out/GTS_OR  (
1965 
    .I(GTS_0),
1966 
    .O(\clk_out/TORGTS )
1967 
  );
1968 
  X_INV \clk_out/ENABLEINV  (
1969 
    .I(\clk_out/TORGTS ),
1970 
    .O(\clk_out/ENABLE )
1971 
  );
1972 
  X_TRI clk_out_OBUF (
1973 
    .I(\clk_out/OUTMUX ),
1974 
    .CTL(\clk_out/ENABLE ),
1975 
    .O(clk_out)
1976 
  );
1977 
  X_OPAD \clk_out/PAD  (
1978 
    .PAD(clk_out)
1979 
  );
1980 
  defparam c_mem.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1981 
  defparam c_mem.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1982 
  defparam c_mem.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1983 
  defparam c_mem.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1984 
  defparam c_mem.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1985 
  defparam c_mem.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1986 
  defparam c_mem.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1987 
  defparam c_mem.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1988 
  defparam c_mem.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1989 
  defparam c_mem.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1990 
  defparam c_mem.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1991 
  defparam c_mem.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1992 
  defparam c_mem.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1993 
  defparam c_mem.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1994 
  defparam c_mem.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1995 
  defparam c_mem.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
1996 
  defparam c_mem.SETUP_ALL = 3139;
1997 
  X_RAMB4_S16_S16 c_mem (
1998 
    .CLKA(clk_in_BUFGP),
1999 
    .CLKB(mpi_clk_BUFGP),
2000 
    .ENA(\c_mem/ENA_INTNOT ),
2001 
    .ENB(ram_en),
2002 
    .RSTA(\c_mem/RSTA_INTNOT ),
2003 
    .RSTB(\c_mem/RSTB_INTNOT ),
2004 
    .WEA(\c_mem/LOGIC_ZERO ),
2005 
    .WEB(\c_mem/WEB_INTNOT ),
2006 
    .GSR(GSR),
2007 
    .ADDRA({c_mem_addr_cnt[4], c_mem_addr_cnt[3], c_mem_addr_cnt[2], c_mem_addr_cnt[1], c_mem_addr_cnt[0], frame_cnt[2], frame_cnt_1_1, frame_cnt[0]})
2008 
,
2009 
    .ADDRB({mpi_addr_7_IBUF, mpi_addr_6_IBUF, mpi_addr_5_IBUF, mpi_addr_4_IBUF, mpi_addr_3_IBUF, mpi_addr_2_IBUF, mpi_addr_1_IBUF, mpi_addr_0_IBUF}),
2010 
    .DIA({GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_5, GLOBAL_LOGIC0_5, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6,
2011 
GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_5, GLOBAL_LOGIC0_4, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6}),
2012 
    .DIB({GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_6, GLOBAL_LOGIC0_3, GLOBAL_LOGIC0_6, mpi_data_in_8_IBUF,
2013 
mpi_data_in_7_IBUF, mpi_data_in_6_IBUF, mpi_data_in_5_IBUF, mpi_data_in_4_IBUF, mpi_data_in_3_IBUF, mpi_data_in_2_IBUF, mpi_data_in_1_IBUF,
2014 
mpi_data_in_0_IBUF}),
2015 
    .DOA({\c_mem/DOA15 , \c_mem/DOA14 , \c_mem/DOA13 , \c_mem/DOA12 , \c_mem/DOA11 , \c_mem/DOA10 , \c_mem/DOA9 , \c_mem/DOA8 , cd_data[7], cd_data[6]
2016 
, cd_data[5], cd_data[4], cd_data[3], cd_data[2], cd_data[1], cd_data[0]}),
2017 
    .DOB({\c_mem/DOB15 , \c_mem/DOB14 , \c_mem/DOB13 , \c_mem/DOB12 , \c_mem/DOB11 , \c_mem/DOB10 , \c_mem/DOB9 , mpi_mem_bus_out[8],
2018 
mpi_mem_bus_out[7], mpi_mem_bus_out[6], mpi_mem_bus_out[5], mpi_mem_bus_out[4], mpi_mem_bus_out[3], mpi_mem_bus_out[2], mpi_mem_bus_out[1],
2019 
mpi_mem_bus_out[0]})
2020 
  );
2021 
  X_INV \c_mem/WEBMUX  (
2022 
    .I(mpi_rw_IBUF),
2023 
    .O(\c_mem/WEB_INTNOT )
2024 
  );
2025 
  X_INV \c_mem/ENAMUX  (
2026 
    .I(frame_cnt[3]),
2027 
    .O(\c_mem/ENA_INTNOT )
2028 
  );
2029 
  X_INV \c_mem/RSTAMUX  (
2030 
    .I(reset_IBUF),
2031 
    .O(\c_mem/RSTA_INTNOT )
2032 
  );
2033 
  X_INV \c_mem/RSTBMUX  (
2034 
    .I(reset_IBUF),
2035 
    .O(\c_mem/RSTB_INTNOT )
2036 
  );
2037 
  X_ZERO \c_mem/LOGIC_ZERO_50  (
2038 
    .O(\c_mem/LOGIC_ZERO )
2039 
  );
2040 
  defparam d_mem.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2041 
  defparam d_mem.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2042 
  defparam d_mem.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2043 
  defparam d_mem.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2044 
  defparam d_mem.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2045 
  defparam d_mem.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2046 
  defparam d_mem.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2047 
  defparam d_mem.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2048 
  defparam d_mem.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2049 
  defparam d_mem.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2050 
  defparam d_mem.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2051 
  defparam d_mem.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2052 
  defparam d_mem.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2053 
  defparam d_mem.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2054 
  defparam d_mem.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2055 
  defparam d_mem.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
2056 
  defparam d_mem.SETUP_ALL = 3139;
2057 
  X_RAMB4_S8_S16 d_mem (
2058 
    .CLKA(clk_in_BUFGP),
2059 
    .CLKB(div_reg),
2060 
    .ENA(\d_mem/LOGIC_ONE ),
2061 
    .ENB(_n0054),
2062 
    .RSTA(\d_mem/RSTA_INTNOT ),
2063 
    .RSTB(\d_mem/RSTB_INTNOT ),
2064 
    .WEA(\d_mem/LOGIC_ZERO ),
2065 
    .WEB(\d_mem/LOGIC_ONE ),
2066 
    .GSR(GSR),
2067 
    .ADDRA({cd_mem_addr[8], cd_data[7], cd_data[6], cd_data[5], cd_data[4], cd_data[3], cd_data[2], cd_data[1], cd_data[0]}),
2068 
    .ADDRB({mem_page_sel, d_mem_addr_cnt[4], d_mem_addr_cnt[3], d_mem_addr_cnt[2], d_mem_addr_cnt[1], d_mem_addr_cnt[0], _COND_1[2], d_mem_addr[0]}),
2069 
    .DIA({GLOBAL_LOGIC0, GLOBAL_LOGIC0, GLOBAL_LOGIC0, GLOBAL_LOGIC0, GLOBAL_LOGIC0, GLOBAL_LOGIC0, GLOBAL_LOGIC0, GLOBAL_LOGIC0}),
2070 
    .DIB({data_in_bus[15], data_in_bus[14], data_in_bus[13], data_in_bus[12], data_in_bus[11], data_in_bus[10], data_in_bus[9], data_in_bus[8],
2071 
data_in_bus[7], data_in_bus[6], data_in_bus[5], data_in_bus[4], data_in_bus[3], data_in_bus[2], data_in_bus[1], data_in_bus[0]}),
2072 
    .DOA({data_out_bus[7], data_out_bus[6], data_out_bus[5], data_out_bus[4], data_out_bus[3], data_out_bus[2], data_out_bus[1], data_out_bus[0]}),
2073 
    .DOB({\d_mem/DOB15 , \d_mem/DOB14 , \d_mem/DOB13 , \d_mem/DOB12 , \d_mem/DOB11 , \d_mem/DOB10 , \d_mem/DOB9 , \d_mem/DOB8 , \d_mem/DOB7 ,
2074 
\d_mem/DOB6 , \d_mem/DOB5 , \d_mem/DOB4 , \d_mem/DOB3 , \d_mem/DOB2 , \d_mem/DOB1 , \d_mem/DOB0 })
2075 
  );
2076 
  X_INV \d_mem/RSTAMUX  (
2077 
    .I(reset_IBUF),
2078 
    .O(\d_mem/RSTA_INTNOT )
2079 
  );
2080 
  X_INV \d_mem/RSTBMUX  (
2081 
    .I(reset_IBUF),
2082 
    .O(\d_mem/RSTB_INTNOT )
2083 
  );
2084 
  X_ONE \d_mem/LOGIC_ONE_51  (
2085 
    .O(\d_mem/LOGIC_ONE )
2086 
  );
2087 
  X_ZERO \d_mem/LOGIC_ZERO_52  (
2088 
    .O(\d_mem/LOGIC_ZERO )
2089 
  );
2090 
  X_BUF \data_in_bus<12>/XUSED  (
2091 
    .I(\data_in_bus<12>/F5MUX ),
2092 
    .O(data_in_bus[12])
2093 
  );
2094 
  defparam Mmux_data_in_bus_inst_mux_f5_16111_F.INIT = 16'hAAF0;
2095 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_16111_F (
2096 
    .ADR0(rx_buf_reg_7[4]),
2097 
    .ADR1(VCC),
2098 
    .ADR2(rx_buf_reg_3[4]),
2099 
    .ADR3(_COND_1[2]),
2100 
    .O(N9669)
2101 
  );
2102 
  defparam Mmux_data_in_bus_inst_mux_f5_16111_G.INIT = 16'hFC30;
2103 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_16111_G (
2104 
    .ADR0(VCC),
2105 
    .ADR1(_COND_1[2]),
2106 
    .ADR2(rx_buf_reg_1[4]),
2107 
    .ADR3(rx_buf_reg_5[4]),
2108 
    .O(N9671)
2109 
  );
2110 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_16111 (
2111 
    .IA(N9669),
2112 
    .IB(N9671),
2113 
    .SEL(frame_cnt_1_1),
2114 
    .O(\data_in_bus<12>/F5MUX )
2115 
  );
2116 
  X_BUF \data_in_bus<3>/XUSED  (
2117 
    .I(\data_in_bus<3>/F5MUX ),
2118 
    .O(data_in_bus[3])
2119 
  );
2120 
  defparam Mmux_data_in_bus_inst_mux_f5_7111_F.INIT = 16'hACAC;
2121 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_7111_F (
2122 
    .ADR0(rx_buf_reg_6[3]),
2123 
    .ADR1(rx_buf_reg_2[3]),
2124 
    .ADR2(_COND_1[2]),
2125 
    .ADR3(VCC),
2126 
    .O(N9619)
2127 
  );
2128 
  defparam Mmux_data_in_bus_inst_mux_f5_7111_G.INIT = 16'hFC0C;
2129 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_7111_G (
2130 
    .ADR0(VCC),
2131 
    .ADR1(rx_buf_reg_0[3]),
2132 
    .ADR2(_COND_1[2]),
2133 
    .ADR3(rx_buf_reg_4[3]),
2134 
    .O(N9621)
2135 
  );
2136 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_7111 (
2137 
    .IA(N9619),
2138 
    .IB(N9621),
2139 
    .SEL(frame_cnt_1_1),
2140 
    .O(\data_in_bus<3>/F5MUX )
2141 
  );
2142 
  X_BUF \data_in_bus<13>/XUSED  (
2143 
    .I(\data_in_bus<13>/F5MUX ),
2144 
    .O(data_in_bus[13])
2145 
  );
2146 
  defparam Mmux_data_in_bus_inst_mux_f5_17111_F.INIT = 16'hE2E2;
2147 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_17111_F (
2148 
    .ADR0(rx_buf_reg_3[5]),
2149 
    .ADR1(_COND_1[2]),
2150 
    .ADR2(rx_buf_reg_7[5]),
2151 
    .ADR3(VCC),
2152 
    .O(N9659)
2153 
  );
2154 
  defparam Mmux_data_in_bus_inst_mux_f5_17111_G.INIT = 16'hF3C0;
2155 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_17111_G (
2156 
    .ADR0(VCC),
2157 
    .ADR1(_COND_1[2]),
2158 
    .ADR2(rx_buf_reg_5[5]),
2159 
    .ADR3(rx_buf_reg_1[5]),
2160 
    .O(N9661)
2161 
  );
2162 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_17111 (
2163 
    .IA(N9659),
2164 
    .IB(N9661),
2165 
    .SEL(frame_cnt_1_1),
2166 
    .O(\data_in_bus<13>/F5MUX )
2167 
  );
2168 
  X_BUF \data_in_bus<4>/XUSED  (
2169 
    .I(\data_in_bus<4>/F5MUX ),
2170 
    .O(data_in_bus[4])
2171 
  );
2172 
  defparam Mmux_data_in_bus_inst_mux_f5_8111_F.INIT = 16'hEE22;
2173 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_8111_F (
2174 
    .ADR0(rx_buf_reg_2[4]),
2175 
    .ADR1(_COND_1[2]),
2176 
    .ADR2(VCC),
2177 
    .ADR3(rx_buf_reg_6[4]),
2178 
    .O(N9614)
2179 
  );
2180 
  defparam Mmux_data_in_bus_inst_mux_f5_8111_G.INIT = 16'hBB88;
2181 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_8111_G (
2182 
    .ADR0(rx_buf_reg_4[4]),
2183 
    .ADR1(_COND_1[2]),
2184 
    .ADR2(VCC),
2185 
    .ADR3(rx_buf_reg_0[4]),
2186 
    .O(N9616)
2187 
  );
2188 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_8111 (
2189 
    .IA(N9614),
2190 
    .IB(N9616),
2191 
    .SEL(frame_cnt_1_1),
2192 
    .O(\data_in_bus<4>/F5MUX )
2193 
  );
2194 
  X_BUF \data_in_bus<14>/XUSED  (
2195 
    .I(\data_in_bus<14>/F5MUX ),
2196 
    .O(data_in_bus[14])
2197 
  );
2198 
  defparam Mmux_data_in_bus_inst_mux_f5_18111_F.INIT = 16'hAFA0;
2199 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_18111_F (
2200 
    .ADR0(rx_buf_reg_7[6]),
2201 
    .ADR1(VCC),
2202 
    .ADR2(_COND_1[2]),
2203 
    .ADR3(rx_buf_reg_3[6]),
2204 
    .O(N9649)
2205 
  );
2206 
  defparam Mmux_data_in_bus_inst_mux_f5_18111_G.INIT = 16'hDD88;
2207 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_18111_G (
2208 
    .ADR0(_COND_1[2]),
2209 
    .ADR1(rx_buf_reg_5[6]),
2210 
    .ADR2(VCC),
2211 
    .ADR3(rx_buf_reg_1[6]),
2212 
    .O(N9651)
2213 
  );
2214 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_18111 (
2215 
    .IA(N9649),
2216 
    .IB(N9651),
2217 
    .SEL(frame_cnt_1_1),
2218 
    .O(\data_in_bus<14>/F5MUX )
2219 
  );
2220 
  X_BUF \data_in_bus<5>/XUSED  (
2221 
    .I(\data_in_bus<5>/F5MUX ),
2222 
    .O(data_in_bus[5])
2223 
  );
2224 
  defparam Mmux_data_in_bus_inst_mux_f5_9111_F.INIT = 16'hAFA0;
2225 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_9111_F (
2226 
    .ADR0(rx_buf_reg_6[5]),
2227 
    .ADR1(VCC),
2228 
    .ADR2(_COND_1[2]),
2229 
    .ADR3(rx_buf_reg_2[5]),
2230 
    .O(N9664)
2231 
  );
2232 
  defparam Mmux_data_in_bus_inst_mux_f5_9111_G.INIT = 16'hF0CC;
2233 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_9111_G (
2234 
    .ADR0(VCC),
2235 
    .ADR1(rx_buf_reg_0[5]),
2236 
    .ADR2(rx_buf_reg_4[5]),
2237 
    .ADR3(_COND_1[2]),
2238 
    .O(N9666)
2239 
  );
2240 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_9111 (
2241 
    .IA(N9664),
2242 
    .IB(N9666),
2243 
    .SEL(frame_cnt_1_1),
2244 
    .O(\data_in_bus<5>/F5MUX )
2245 
  );
2246 
  X_BUF \data_in_bus<15>/XUSED  (
2247 
    .I(\data_in_bus<15>/F5MUX ),
2248 
    .O(data_in_bus[15])
2249 
  );
2250 
  defparam Mmux_data_in_bus_inst_mux_f5_19111_F.INIT = 16'hACAC;
2251 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_19111_F (
2252 
    .ADR0(rx_buf_reg_7[7]),
2253 
    .ADR1(rx_buf_reg_3[7]),
2254 
    .ADR2(_COND_1[2]),
2255 
    .ADR3(VCC),
2256 
    .O(N9674)
2257 
  );
2258 
  defparam Mmux_data_in_bus_inst_mux_f5_19111_G.INIT = 16'hEE22;
2259 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_19111_G (
2260 
    .ADR0(rx_buf_reg_1[7]),
2261 
    .ADR1(_COND_1[2]),
2262 
    .ADR2(VCC),
2263 
    .ADR3(rx_buf_reg_5[7]),
2264 
    .O(N9676)
2265 
  );
2266 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_19111 (
2267 
    .IA(N9674),
2268 
    .IB(N9676),
2269 
    .SEL(frame_cnt_1_1),
2270 
    .O(\data_in_bus<15>/F5MUX )
2271 
  );
2272 
  X_BUF \Mmux__n0074__net2/F5USED  (
2273 
    .I(\Mmux__n0074__net2/F5MUX ),
2274 
    .O(Mmux__n0074__net2)
2275 
  );
2276 
  defparam Mmux__n0074_inst_lut3_01.INIT = 16'hCCF0;
2277 
  X_LUT4 Mmux__n0074_inst_lut3_01 (
2278 
    .ADR0(VCC),
2279 
    .ADR1(frame_delay_buf_1[0]),
2280 
    .ADR2(frame_delay_buf_0[0]),
2281 
    .ADR3(mpi_addr_0_IBUF),
2282 
    .O(Mmux__n0074__net0)
2283 
  );
2284 
  defparam Mmux__n0074_inst_lut3_11.INIT = 16'hAFA0;
2285 
  X_LUT4 Mmux__n0074_inst_lut3_11 (
2286 
    .ADR0(frame_delay_buf_3[0]),
2287 
    .ADR1(VCC),
2288 
    .ADR2(mpi_addr_0_IBUF),
2289 
    .ADR3(frame_delay_buf_2[0]),
2290 
    .O(Mmux__n0074__net1)
2291 
  );
2292 
  X_MUX2 Mmux__n0074_inst_mux_f5_0 (
2293 
    .IA(Mmux__n0074__net0),
2294 
    .IB(Mmux__n0074__net1),
2295 
    .SEL(mpi_addr_1_IBUF),
2296 
    .O(\Mmux__n0074__net2/F5MUX )
2297 
  );
2298 
  X_MUX2 Mmux__n0074_inst_mux_f6_0 (
2299 
    .IA(Mmux__n0074__net2),
2300 
    .IB(Mmux__n0074__net5),
2301 
    .SEL(mpi_addr_2_IBUF),
2302 
    .O(\_n0246<2>/F6MUX )
2303 
  );
2304 
  X_BUF \_n0246<2>/YUSED  (
2305 
    .I(\_n0246<2>/F6MUX ),
2306 
    .O(_n0246[2])
2307 
  );
2308 
  defparam Mmux__n0074_inst_lut3_21.INIT = 16'hF5A0;
2309 
  X_LUT4 Mmux__n0074_inst_lut3_21 (
2310 
    .ADR0(mpi_addr_0_IBUF),
2311 
    .ADR1(VCC),
2312 
    .ADR2(frame_delay_buf_5[0]),
2313 
    .ADR3(frame_delay_buf_4[0]),
2314 
    .O(Mmux__n0074__net3)
2315 
  );
2316 
  defparam Mmux__n0074_inst_lut3_31.INIT = 16'hE4E4;
2317 
  X_LUT4 Mmux__n0074_inst_lut3_31 (
2318 
    .ADR0(mpi_addr_0_IBUF),
2319 
    .ADR1(frame_delay_buf_6[0]),
2320 
    .ADR2(frame_delay_buf_7[0]),
2321 
    .ADR3(VCC),
2322 
    .O(Mmux__n0074__net4)
2323 
  );
2324 
  X_MUX2 Mmux__n0074_inst_mux_f5_1 (
2325 
    .IA(Mmux__n0074__net3),
2326 
    .IB(Mmux__n0074__net4),
2327 
    .SEL(mpi_addr_1_IBUF),
2328 
    .O(Mmux__n0074__net5)
2329 
  );
2330 
  X_BUF \Mmux__n0074__net9/F5USED  (
2331 
    .I(\Mmux__n0074__net9/F5MUX ),
2332 
    .O(Mmux__n0074__net9)
2333 
  );
2334 
  defparam Mmux__n0074_inst_lut3_41.INIT = 16'hCACA;
2335 
  X_LUT4 Mmux__n0074_inst_lut3_41 (
2336 
    .ADR0(frame_delay_buf_0[1]),
2337 
    .ADR1(frame_delay_buf_1[1]),
2338 
    .ADR2(mpi_addr_0_IBUF),
2339 
    .ADR3(VCC),
2340 
    .O(Mmux__n0074__net7)
2341 
  );
2342 
  defparam Mmux__n0074_inst_lut3_51.INIT = 16'hF0CC;
2343 
  X_LUT4 Mmux__n0074_inst_lut3_51 (
2344 
    .ADR0(VCC),
2345 
    .ADR1(frame_delay_buf_2[1]),
2346 
    .ADR2(frame_delay_buf_3[1]),
2347 
    .ADR3(mpi_addr_0_IBUF),
2348 
    .O(Mmux__n0074__net8)
2349 
  );
2350 
  X_MUX2 Mmux__n0074_inst_mux_f5_2 (
2351 
    .IA(Mmux__n0074__net7),
2352 
    .IB(Mmux__n0074__net8),
2353 
    .SEL(mpi_addr_1_IBUF),
2354 
    .O(\Mmux__n0074__net9/F5MUX )
2355 
  );
2356 
  X_MUX2 Mmux__n0074_inst_mux_f6_1 (
2357 
    .IA(Mmux__n0074__net9),
2358 
    .IB(Mmux__n0074__net12),
2359 
    .SEL(mpi_addr_2_IBUF),
2360 
    .O(\_n0246<3>/F6MUX )
2361 
  );
2362 
  X_BUF \_n0246<3>/YUSED  (
2363 
    .I(\_n0246<3>/F6MUX ),
2364 
    .O(_n0246[3])
2365 
  );
2366 
  defparam Mmux__n0074_inst_lut3_61.INIT = 16'hCFC0;
2367 
  X_LUT4 Mmux__n0074_inst_lut3_61 (
2368 
    .ADR0(VCC),
2369 
    .ADR1(frame_delay_buf_5[1]),
2370 
    .ADR2(mpi_addr_0_IBUF),
2371 
    .ADR3(frame_delay_buf_4[1]),
2372 
    .O(Mmux__n0074__net10)
2373 
  );
2374 
  defparam Mmux__n0074_inst_lut3_71.INIT = 16'hFC30;
2375 
  X_LUT4 Mmux__n0074_inst_lut3_71 (
2376 
    .ADR0(VCC),
2377 
    .ADR1(mpi_addr_0_IBUF),
2378 
    .ADR2(frame_delay_buf_6[1]),
2379 
    .ADR3(frame_delay_buf_7[1]),
2380 
    .O(Mmux__n0074__net11)
2381 
  );
2382 
  X_MUX2 Mmux__n0074_inst_mux_f5_3 (
2383 
    .IA(Mmux__n0074__net10),
2384 
    .IB(Mmux__n0074__net11),
2385 
    .SEL(mpi_addr_1_IBUF),
2386 
    .O(Mmux__n0074__net12)
2387 
  );
2388 
  X_BUF \data_in_bus<6>/XUSED  (
2389 
    .I(\data_in_bus<6>/F5MUX ),
2390 
    .O(data_in_bus[6])
2391 
  );
2392 
  defparam Mmux_data_in_bus_inst_mux_f5_10111_F.INIT = 16'hFA0A;
2393 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_10111_F (
2394 
    .ADR0(rx_buf_reg_2[6]),
2395 
    .ADR1(VCC),
2396 
    .ADR2(_COND_1[2]),
2397 
    .ADR3(rx_buf_reg_6[6]),
2398 
    .O(N9654)
2399 
  );
2400 
  defparam Mmux_data_in_bus_inst_mux_f5_10111_G.INIT = 16'hAFA0;
2401 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_10111_G (
2402 
    .ADR0(rx_buf_reg_4[6]),
2403 
    .ADR1(VCC),
2404 
    .ADR2(_COND_1[2]),
2405 
    .ADR3(rx_buf_reg_0[6]),
2406 
    .O(N9656)
2407 
  );
2408 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_10111 (
2409 
    .IA(N9654),
2410 
    .IB(N9656),
2411 
    .SEL(frame_cnt_1_1),
2412 
    .O(\data_in_bus<6>/F5MUX )
2413 
  );
2414 
  X_BUF \data_in_bus<7>/XUSED  (
2415 
    .I(\data_in_bus<7>/F5MUX ),
2416 
    .O(data_in_bus[7])
2417 
  );
2418 
  defparam Mmux_data_in_bus_inst_mux_f5_11111_F.INIT = 16'hAFA0;
2419 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_11111_F (
2420 
    .ADR0(rx_buf_reg_6[7]),
2421 
    .ADR1(VCC),
2422 
    .ADR2(_COND_1[2]),
2423 
    .ADR3(rx_buf_reg_2[7]),
2424 
    .O(N9644)
2425 
  );
2426 
  defparam Mmux_data_in_bus_inst_mux_f5_11111_G.INIT = 16'hEE44;
2427 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_11111_G (
2428 
    .ADR0(_COND_1[2]),
2429 
    .ADR1(rx_buf_reg_0[7]),
2430 
    .ADR2(VCC),
2431 
    .ADR3(rx_buf_reg_4[7]),
2432 
    .O(N9646)
2433 
  );
2434 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_11111 (
2435 
    .IA(N9644),
2436 
    .IB(N9646),
2437 
    .SEL(frame_cnt_1_1),
2438 
    .O(\data_in_bus<7>/F5MUX )
2439 
  );
2440 
  X_BUF \data_in_bus<8>/XUSED  (
2441 
    .I(\data_in_bus<8>/F5MUX ),
2442 
    .O(data_in_bus[8])
2443 
  );
2444 
  defparam Mmux_data_in_bus_inst_mux_f5_12111_F.INIT = 16'hAFA0;
2445 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_12111_F (
2446 
    .ADR0(rx_buf_reg_7[0]),
2447 
    .ADR1(VCC),
2448 
    .ADR2(_COND_1[2]),
2449 
    .ADR3(rx_buf_reg_3[0]),
2450 
    .O(N9634)
2451 
  );
2452 
  defparam Mmux_data_in_bus_inst_mux_f5_12111_G.INIT = 16'hACAC;
2453 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_12111_G (
2454 
    .ADR0(rx_buf_reg_5[0]),
2455 
    .ADR1(rx_buf_reg_1[0]),
2456 
    .ADR2(_COND_1[2]),
2457 
    .ADR3(VCC),
2458 
    .O(N9636)
2459 
  );
2460 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_12111 (
2461 
    .IA(N9634),
2462 
    .IB(N9636),
2463 
    .SEL(frame_cnt_1_1),
2464 
    .O(\data_in_bus<8>/F5MUX )
2465 
  );
2466 
  X_BUF \data_in_bus<9>/XUSED  (
2467 
    .I(\data_in_bus<9>/F5MUX ),
2468 
    .O(data_in_bus[9])
2469 
  );
2470 
  defparam Mmux_data_in_bus_inst_mux_f5_13111_F.INIT = 16'hEE22;
2471 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_13111_F (
2472 
    .ADR0(rx_buf_reg_3[1]),
2473 
    .ADR1(_COND_1[2]),
2474 
    .ADR2(VCC),
2475 
    .ADR3(rx_buf_reg_7[1]),
2476 
    .O(N9629)
2477 
  );
2478 
  defparam Mmux_data_in_bus_inst_mux_f5_13111_G.INIT = 16'hFC30;
2479 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_13111_G (
2480 
    .ADR0(VCC),
2481 
    .ADR1(_COND_1[2]),
2482 
    .ADR2(rx_buf_reg_1[1]),
2483 
    .ADR3(rx_buf_reg_5[1]),
2484 
    .O(N9631)
2485 
  );
2486 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_13111 (
2487 
    .IA(N9629),
2488 
    .IB(N9631),
2489 
    .SEL(frame_cnt_1_1),
2490 
    .O(\data_in_bus<9>/F5MUX )
2491 
  );
2492 
  X_BUF \data_in_bus<0>/XUSED  (
2493 
    .I(\data_in_bus<0>/F5MUX ),
2494 
    .O(data_in_bus[0])
2495 
  );
2496 
  defparam Mmux_data_in_bus_inst_mux_f5_4111_F.INIT = 16'hCCAA;
2497 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_4111_F (
2498 
    .ADR0(rx_buf_reg_2[0]),
2499 
    .ADR1(rx_buf_reg_6[0]),
2500 
    .ADR2(VCC),
2501 
    .ADR3(_COND_1[2]),
2502 
    .O(N9679)
2503 
  );
2504 
  defparam Mmux_data_in_bus_inst_mux_f5_4111_G.INIT = 16'hCCF0;
2505 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_4111_G (
2506 
    .ADR0(VCC),
2507 
    .ADR1(rx_buf_reg_4[0]),
2508 
    .ADR2(rx_buf_reg_0[0]),
2509 
    .ADR3(_COND_1[2]),
2510 
    .O(N9681)
2511 
  );
2512 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_4111 (
2513 
    .IA(N9679),
2514 
    .IB(N9681),
2515 
    .SEL(frame_cnt_1_1),
2516 
    .O(\data_in_bus<0>/F5MUX )
2517 
  );
2518 
  X_BUF \data_in_bus<10>/XUSED  (
2519 
    .I(\data_in_bus<10>/F5MUX ),
2520 
    .O(data_in_bus[10])
2521 
  );
2522 
  defparam Mmux_data_in_bus_inst_mux_f5_14111_F.INIT = 16'hCFC0;
2523 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_14111_F (
2524 
    .ADR0(VCC),
2525 
    .ADR1(rx_buf_reg_7[2]),
2526 
    .ADR2(_COND_1[2]),
2527 
    .ADR3(rx_buf_reg_3[2]),
2528 
    .O(N9624)
2529 
  );
2530 
  defparam Mmux_data_in_bus_inst_mux_f5_14111_G.INIT = 16'hDD88;
2531 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_14111_G (
2532 
    .ADR0(_COND_1[2]),
2533 
    .ADR1(rx_buf_reg_5[2]),
2534 
    .ADR2(VCC),
2535 
    .ADR3(rx_buf_reg_1[2]),
2536 
    .O(N9626)
2537 
  );
2538 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_14111 (
2539 
    .IA(N9624),
2540 
    .IB(N9626),
2541 
    .SEL(frame_cnt_1_1),
2542 
    .O(\data_in_bus<10>/F5MUX )
2543 
  );
2544 
  X_BUF \data_in_bus<1>/XUSED  (
2545 
    .I(\data_in_bus<1>/F5MUX ),
2546 
    .O(data_in_bus[1])
2547 
  );
2548 
  defparam Mmux_data_in_bus_inst_mux_f5_5111_F.INIT = 16'hFC30;
2549 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_5111_F (
2550 
    .ADR0(VCC),
2551 
    .ADR1(_COND_1[2]),
2552 
    .ADR2(rx_buf_reg_2[1]),
2553 
    .ADR3(rx_buf_reg_6[1]),
2554 
    .O(N9609)
2555 
  );
2556 
  defparam Mmux_data_in_bus_inst_mux_f5_5111_G.INIT = 16'hF3C0;
2557 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_5111_G (
2558 
    .ADR0(VCC),
2559 
    .ADR1(_COND_1[2]),
2560 
    .ADR2(rx_buf_reg_4[1]),
2561 
    .ADR3(rx_buf_reg_0[1]),
2562 
    .O(N9611)
2563 
  );
2564 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_5111 (
2565 
    .IA(N9609),
2566 
    .IB(N9611),
2567 
    .SEL(frame_cnt_1_1),
2568 
    .O(\data_in_bus<1>/F5MUX )
2569 
  );
2570 
  X_BUF \data_in_bus<11>/XUSED  (
2571 
    .I(\data_in_bus<11>/F5MUX ),
2572 
    .O(data_in_bus[11])
2573 
  );
2574 
  defparam Mmux_data_in_bus_inst_mux_f5_15111_F.INIT = 16'hF3C0;
2575 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_15111_F (
2576 
    .ADR0(VCC),
2577 
    .ADR1(_COND_1[2]),
2578 
    .ADR2(rx_buf_reg_7[3]),
2579 
    .ADR3(rx_buf_reg_3[3]),
2580 
    .O(N9639)
2581 
  );
2582 
  defparam Mmux_data_in_bus_inst_mux_f5_15111_G.INIT = 16'hEE22;
2583 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_15111_G (
2584 
    .ADR0(rx_buf_reg_1[3]),
2585 
    .ADR1(_COND_1[2]),
2586 
    .ADR2(VCC),
2587 
    .ADR3(rx_buf_reg_5[3]),
2588 
    .O(N9641)
2589 
  );
2590 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_15111 (
2591 
    .IA(N9639),
2592 
    .IB(N9641),
2593 
    .SEL(frame_cnt_1_1),
2594 
    .O(\data_in_bus<11>/F5MUX )
2595 
  );
2596 
  X_BUF \data_in_bus<2>/XUSED  (
2597 
    .I(\data_in_bus<2>/F5MUX ),
2598 
    .O(data_in_bus[2])
2599 
  );
2600 
  defparam Mmux_data_in_bus_inst_mux_f5_6111_F.INIT = 16'hAFA0;
2601 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_6111_F (
2602 
    .ADR0(rx_buf_reg_6[2]),
2603 
    .ADR1(VCC),
2604 
    .ADR2(_COND_1[2]),
2605 
    .ADR3(rx_buf_reg_2[2]),
2606 
    .O(N9604)
2607 
  );
2608 
  defparam Mmux_data_in_bus_inst_mux_f5_6111_G.INIT = 16'hEE44;
2609 
  X_LUT4 Mmux_data_in_bus_inst_mux_f5_6111_G (
2610 
    .ADR0(_COND_1[2]),
2611 
    .ADR1(rx_buf_reg_0[2]),
2612 
    .ADR2(VCC),
2613 
    .ADR3(rx_buf_reg_4[2]),
2614 
    .O(N9606)
2615 
  );
2616 
  X_MUX2 Mmux_data_in_bus_inst_mux_f5_6111 (
2617 
    .IA(N9604),
2618 
    .IB(N9606),
2619 
    .SEL(frame_cnt_1_1),
2620 
    .O(\data_in_bus<2>/F5MUX )
2621 
  );
2622 
  X_XOR2 d_mem_addr_cnt_Madd__n0000_inst_sum_1 (
2623 
    .I0(d_mem_addr_cnt_Madd__n0000_inst_cy_0),
2624 
    .I1(\d_mem_addr_cnt<0>/GROM ),
2625 
    .O(d_mem_addr_cnt__n0000[1])
2626 
  );
2627 
  X_MUX2 d_mem_addr_cnt_Madd__n0000_inst_cy_1 (
2628 
    .IA(GLOBAL_LOGIC0_0),
2629 
    .IB(d_mem_addr_cnt_Madd__n0000_inst_cy_0),
2630 
    .SEL(\d_mem_addr_cnt<0>/GROM ),
2631 
    .O(\d_mem_addr_cnt<0>/CYMUXG )
2632 
  );
2633 
  defparam \d_mem_addr_cnt<0>/G .INIT = 16'hF0F0;
2634 
  X_LUT4 \d_mem_addr_cnt<0>/G  (
2635 
    .ADR0(GLOBAL_LOGIC0_0),
2636 
    .ADR1(VCC),
2637 
    .ADR2(d_mem_addr_cnt[1]),
2638 
    .ADR3(VCC),
2639 
    .O(\d_mem_addr_cnt<0>/GROM )
2640 
  );
2641 
  defparam d_mem_addr_cnt_Madd__n0000_inst_lut2_01.INIT = 16'h3333;
2642 
  X_LUT4 d_mem_addr_cnt_Madd__n0000_inst_lut2_01 (
2643 
    .ADR0(GLOBAL_LOGIC1_1),
2644 
    .ADR1(d_mem_addr_cnt[0]),
2645 
    .ADR2(VCC),
2646 
    .ADR3(VCC),
2647 
    .O(d_mem_addr_cnt_Madd__n0000_inst_lut2_0)
2648 
  );
2649 
  X_MUX2 d_mem_addr_cnt_Madd__n0000_inst_cy_0_53 (
2650 
    .IA(GLOBAL_LOGIC1_1),
2651 
    .IB(\d_mem_addr_cnt<0>/LOGIC_ZERO ),
2652 
    .SEL(d_mem_addr_cnt_Madd__n0000_inst_lut2_0),
2653 
    .O(d_mem_addr_cnt_Madd__n0000_inst_cy_0)
2654 
  );
2655 
  X_ZERO \d_mem_addr_cnt<0>/LOGIC_ZERO_54  (
2656 
    .O(\d_mem_addr_cnt<0>/LOGIC_ZERO )
2657 
  );
2658 
  X_SFF d_mem_addr_cnt_0 (
2659 
    .I(d_mem_addr_cnt_Madd__n0000_inst_lut2_0),
2660 
    .CE(N8791),
2661 
    .CLK(div_reg),
2662 
    .SET(GSR),
2663 
    .RST(GND),
2664 
    .SSET(frame_sync_OBUF),
2665 
    .SRST(GND),
2666 
    .O(d_mem_addr_cnt[0])
2667 
  );
2668 
  X_SFF d_mem_addr_cnt_1 (
2669 
    .I(d_mem_addr_cnt__n0000[1]),
2670 
    .CE(N8791),
2671 
    .CLK(div_reg),
2672 
    .SET(GSR),
2673 
    .RST(GND),
2674 
    .SSET(frame_sync_OBUF),
2675 
    .SRST(GND),
2676 
    .O(d_mem_addr_cnt[1])
2677 
  );
2678 
  X_BUF \d_mem_addr_cnt<2>/CYINIT_55  (
2679 
    .I(\d_mem_addr_cnt<0>/CYMUXG ),
2680 
    .O(\d_mem_addr_cnt<2>/CYINIT )
2681 
  );
2682 
  X_XOR2 d_mem_addr_cnt_Madd__n0000_inst_sum_3 (
2683 
    .I0(d_mem_addr_cnt_Madd__n0000_inst_cy_2),
2684 
    .I1(\d_mem_addr_cnt<2>/GROM ),
2685 
    .O(d_mem_addr_cnt__n0000[3])
2686 
  );
2687 
  X_MUX2 d_mem_addr_cnt_Madd__n0000_inst_cy_3 (
2688 
    .IA(\d_mem_addr_cnt<2>/LOGIC_ZERO ),
2689 
    .IB(d_mem_addr_cnt_Madd__n0000_inst_cy_2),
2690 
    .SEL(\d_mem_addr_cnt<2>/GROM ),
2691 
    .O(\d_mem_addr_cnt<2>/CYMUXG )
2692 
  );
2693 
  defparam \d_mem_addr_cnt<2>/G .INIT = 16'hF0F0;
2694 
  X_LUT4 \d_mem_addr_cnt<2>/G  (
2695 
    .ADR0(VCC),
2696 
    .ADR1(VCC),
2697 
    .ADR2(d_mem_addr_cnt[3]),
2698 
    .ADR3(VCC),
2699 
    .O(\d_mem_addr_cnt<2>/GROM )
2700 
  );
2701 
  defparam \d_mem_addr_cnt<2>/F .INIT = 16'hFF00;
2702 
  X_LUT4 \d_mem_addr_cnt<2>/F  (
2703 
    .ADR0(VCC),
2704 
    .ADR1(VCC),
2705 
    .ADR2(VCC),
2706 
    .ADR3(d_mem_addr_cnt[2]),
2707 
    .O(\d_mem_addr_cnt<2>/FROM )
2708 
  );
2709 
  X_XOR2 d_mem_addr_cnt_Madd__n0000_inst_sum_2 (
2710 
    .I0(\d_mem_addr_cnt<2>/CYINIT ),
2711 
    .I1(\d_mem_addr_cnt<2>/FROM ),
2712 
    .O(d_mem_addr_cnt__n0000[2])
2713 
  );
2714 
  X_MUX2 d_mem_addr_cnt_Madd__n0000_inst_cy_2_56 (
2715 
    .IA(\d_mem_addr_cnt<2>/LOGIC_ZERO ),
2716 
    .IB(\d_mem_addr_cnt<2>/CYINIT ),
2717 
    .SEL(\d_mem_addr_cnt<2>/FROM ),
2718 
    .O(d_mem_addr_cnt_Madd__n0000_inst_cy_2)
2719 
  );
2720 
  X_ZERO \d_mem_addr_cnt<2>/LOGIC_ZERO_57  (
2721 
    .O(\d_mem_addr_cnt<2>/LOGIC_ZERO )
2722 
  );
2723 
  X_SFF d_mem_addr_cnt_2 (
2724 
    .I(d_mem_addr_cnt__n0000[2]),
2725 
    .CE(N8791),
2726 
    .CLK(div_reg),
2727 
    .SET(GSR),
2728 
    .RST(GND),
2729 
    .SSET(frame_sync_OBUF),
2730 
    .SRST(GND),
2731 
    .O(d_mem_addr_cnt[2])
2732 
  );
2733 
  X_SFF d_mem_addr_cnt_3 (
2734 
    .I(d_mem_addr_cnt__n0000[3]),
2735 
    .CE(N8791),
2736 
    .CLK(div_reg),
2737 
    .SET(GSR),
2738 
    .RST(GND),
2739 
    .SSET(frame_sync_OBUF),
2740 
    .SRST(GND),
2741 
    .O(d_mem_addr_cnt[3])
2742 
  );
2743 
  X_BUF \d_mem_addr_cnt<4>/CYINIT_58  (
2744 
    .I(\d_mem_addr_cnt<2>/CYMUXG ),
2745 
    .O(\d_mem_addr_cnt<4>/CYINIT )
2746 
  );
2747 
  defparam \d_mem_addr_cnt<4>_rt_59 .INIT = 16'hFF00;
2748 
  X_LUT4 \d_mem_addr_cnt<4>_rt_59  (
2749 
    .ADR0(VCC),
2750 
    .ADR1(VCC),
2751 
    .ADR2(VCC),
2752 
    .ADR3(d_mem_addr_cnt[4]),
2753 
    .O(\d_mem_addr_cnt<4>_rt )
2754 
  );
2755 
  X_XOR2 d_mem_addr_cnt_Madd__n0000_inst_sum_4 (
2756 
    .I0(\d_mem_addr_cnt<4>/CYINIT ),
2757 
    .I1(\d_mem_addr_cnt<4>_rt ),
2758 
    .O(d_mem_addr_cnt__n0000[4])
2759 
  );
2760 
  X_SFF d_mem_addr_cnt_4 (
2761 
    .I(d_mem_addr_cnt__n0000[4]),
2762 
    .CE(N8791),
2763 
    .CLK(div_reg),
2764 
    .SET(GSR),
2765 
    .RST(GND),
2766 
    .SSET(frame_sync_OBUF),
2767 
    .SRST(GND),
2768 
    .O(d_mem_addr_cnt[4])
2769 
  );
2770 
  X_XOR2 c_mem_addr_cnt_Madd__n0000_inst_sum_1 (
2771 
    .I0(c_mem_addr_cnt_Madd__n0000_inst_cy_0),
2772 
    .I1(\c_mem_addr_cnt<0>/GROM ),
2773 
    .O(c_mem_addr_cnt__n0000[1])
2774 
  );
2775 
  X_MUX2 c_mem_addr_cnt_Madd__n0000_inst_cy_1 (
2776 
    .IA(GLOBAL_LOGIC0_2),
2777 
    .IB(c_mem_addr_cnt_Madd__n0000_inst_cy_0),
2778 
    .SEL(\c_mem_addr_cnt<0>/GROM ),
2779 
    .O(\c_mem_addr_cnt<0>/CYMUXG )
2780 
  );
2781 
  defparam \c_mem_addr_cnt<0>/G .INIT = 16'hCCCC;
2782 
  X_LUT4 \c_mem_addr_cnt<0>/G  (
2783 
    .ADR0(GLOBAL_LOGIC0_2),
2784 
    .ADR1(c_mem_addr_cnt[1]),
2785 
    .ADR2(VCC),
2786 
    .ADR3(VCC),
2787 
    .O(\c_mem_addr_cnt<0>/GROM )
2788 
  );
2789 
  defparam c_mem_addr_cnt_Madd__n0000_inst_lut2_01.INIT = 16'h00FF;
2790 
  X_LUT4 c_mem_addr_cnt_Madd__n0000_inst_lut2_01 (
2791 
    .ADR0(GLOBAL_LOGIC1),
2792 
    .ADR1(VCC),
2793 
    .ADR2(VCC),
2794 
    .ADR3(c_mem_addr_cnt[0]),
2795 
    .O(c_mem_addr_cnt_Madd__n0000_inst_lut2_0)
2796 
  );
2797 
  X_MUX2 c_mem_addr_cnt_Madd__n0000_inst_cy_0_60 (
2798 
    .IA(GLOBAL_LOGIC1),
2799 
    .IB(\c_mem_addr_cnt<0>/LOGIC_ZERO ),
2800 
    .SEL(c_mem_addr_cnt_Madd__n0000_inst_lut2_0),
2801 
    .O(c_mem_addr_cnt_Madd__n0000_inst_cy_0)
2802 
  );
2803 
  X_ZERO \c_mem_addr_cnt<0>/LOGIC_ZERO_61  (
2804 
    .O(\c_mem_addr_cnt<0>/LOGIC_ZERO )
2805 
  );
2806 
  X_SFF c_mem_addr_cnt_0 (
2807 
    .I(c_mem_addr_cnt_Madd__n0000_inst_lut2_0),
2808 
    .CE(N8791),
2809 
    .CLK(div_reg),
2810 
    .SET(GSR),
2811 
    .RST(GND),
2812 
    .SSET(frame_sync_OBUF),
2813 
    .SRST(GND),
2814 
    .O(c_mem_addr_cnt[0])
2815 
  );
2816 
  X_SFF c_mem_addr_cnt_1 (
2817 
    .I(c_mem_addr_cnt__n0000[1]),
2818 
    .CE(N8791),
2819 
    .CLK(div_reg),
2820 
    .SET(GND),
2821 
    .RST(GSR),
2822 
    .SSET(GND),
2823 
    .SRST(frame_sync_OBUF),
2824 
    .O(c_mem_addr_cnt[1])
2825 
  );
2826 
  X_BUF \c_mem_addr_cnt<2>/CYINIT_62  (
2827 
    .I(\c_mem_addr_cnt<0>/CYMUXG ),
2828 
    .O(\c_mem_addr_cnt<2>/CYINIT )
2829 
  );
2830 
  X_XOR2 c_mem_addr_cnt_Madd__n0000_inst_sum_3 (
2831 
    .I0(c_mem_addr_cnt_Madd__n0000_inst_cy_2),
2832 
    .I1(\c_mem_addr_cnt<2>/GROM ),
2833 
    .O(c_mem_addr_cnt__n0000[3])
2834 
  );
2835 
  X_MUX2 c_mem_addr_cnt_Madd__n0000_inst_cy_3 (
2836 
    .IA(\c_mem_addr_cnt<2>/LOGIC_ZERO ),
2837 
    .IB(c_mem_addr_cnt_Madd__n0000_inst_cy_2),
2838 
    .SEL(\c_mem_addr_cnt<2>/GROM ),
2839 
    .O(\c_mem_addr_cnt<2>/CYMUXG )
2840 
  );
2841 
  defparam \c_mem_addr_cnt<2>/G .INIT = 16'hFF00;
2842 
  X_LUT4 \c_mem_addr_cnt<2>/G  (
2843 
    .ADR0(VCC),
2844 
    .ADR1(VCC),
2845 
    .ADR2(VCC),
2846 
    .ADR3(c_mem_addr_cnt[3]),
2847 
    .O(\c_mem_addr_cnt<2>/GROM )
2848 
  );
2849 
  defparam \c_mem_addr_cnt<2>/F .INIT = 16'hCCCC;
2850 
  X_LUT4 \c_mem_addr_cnt<2>/F  (
2851 
    .ADR0(VCC),
2852 
    .ADR1(c_mem_addr_cnt[2]),
2853 
    .ADR2(VCC),
2854 
    .ADR3(VCC),
2855 
    .O(\c_mem_addr_cnt<2>/FROM )
2856 
  );
2857 
  X_XOR2 c_mem_addr_cnt_Madd__n0000_inst_sum_2 (
2858 
    .I0(\c_mem_addr_cnt<2>/CYINIT ),
2859 
    .I1(\c_mem_addr_cnt<2>/FROM ),
2860 
    .O(c_mem_addr_cnt__n0000[2])
2861 
  );
2862 
  X_MUX2 c_mem_addr_cnt_Madd__n0000_inst_cy_2_63 (
2863 
    .IA(\c_mem_addr_cnt<2>/LOGIC_ZERO ),
2864 
    .IB(\c_mem_addr_cnt<2>/CYINIT ),
2865 
    .SEL(\c_mem_addr_cnt<2>/FROM ),
2866 
    .O(c_mem_addr_cnt_Madd__n0000_inst_cy_2)
2867 
  );
2868 
  X_ZERO \c_mem_addr_cnt<2>/LOGIC_ZERO_64  (
2869 
    .O(\c_mem_addr_cnt<2>/LOGIC_ZERO )
2870 
  );
2871 
  X_SFF c_mem_addr_cnt_3 (
2872 
    .I(c_mem_addr_cnt__n0000[3]),
2873 
    .CE(N8791),
2874 
    .CLK(div_reg),
2875 
    .SET(GND),
2876 
    .RST(GSR),
2877 
    .SSET(GND),
2878 
    .SRST(frame_sync_OBUF),
2879 
    .O(c_mem_addr_cnt[3])
2880 
  );
2881 
  X_BUF \c_mem_addr_cnt<4>/CYINIT_65  (
2882 
    .I(\c_mem_addr_cnt<2>/CYMUXG ),
2883 
    .O(\c_mem_addr_cnt<4>/CYINIT )
2884 
  );
2885 
  defparam \c_mem_addr_cnt<4>_rt_66 .INIT = 16'hCCCC;
2886 
  X_LUT4 \c_mem_addr_cnt<4>_rt_66  (
2887 
    .ADR0(VCC),
2888 
    .ADR1(c_mem_addr_cnt[4]),
2889 
    .ADR2(VCC),
2890 
    .ADR3(VCC),
2891 
    .O(\c_mem_addr_cnt<4>_rt )
2892 
  );
2893 
  X_XOR2 c_mem_addr_cnt_Madd__n0000_inst_sum_4 (
2894 
    .I0(\c_mem_addr_cnt<4>/CYINIT ),
2895 
    .I1(\c_mem_addr_cnt<4>_rt ),
2896 
    .O(c_mem_addr_cnt__n0000[4])
2897 
  );
2898 
  X_SFF c_mem_addr_cnt_4 (
2899 
    .I(c_mem_addr_cnt__n0000[4]),
2900 
    .CE(N8791),
2901 
    .CLK(div_reg),
2902 
    .SET(GND),
2903 
    .RST(GSR),
2904 
    .SSET(GND),
2905 
    .SRST(frame_sync_OBUF),
2906 
    .O(c_mem_addr_cnt[4])
2907 
  );
2908 
  X_INV \frame_cnt<0>/SRMUX  (
2909 
    .I(reset_IBUF),
2910 
    .O(\frame_cnt<0>/SRMUX_OUTPUTNOT )
2911 
  );
2912 
  X_XOR2 frame_cnt_Madd__n0000_inst_sum_6 (
2913 
    .I0(frame_cnt_Madd__n0000_inst_cy_5),
2914 
    .I1(\frame_cnt<0>/GROM ),
2915 
    .O(\frame_cnt<0>/XORG )
2916 
  );
2917 
  X_MUX2 frame_cnt_Madd__n0000_inst_cy_6 (
2918 
    .IA(GLOBAL_LOGIC0_1),
2919 
    .IB(frame_cnt_Madd__n0000_inst_cy_5),
2920 
    .SEL(\frame_cnt<0>/GROM ),
2921 
    .O(\frame_cnt<0>/CYMUXG )
2922 
  );
2923 
  X_BUF \frame_cnt<0>/YUSED  (
2924 
    .I(\frame_cnt<0>/XORG ),
2925 
    .O(frame_cnt__n0000[1])
2926 
  );
2927 
  X_INV \frame_cnt<0>/CKINV  (
2928 
    .I(clk_in_BUFGP),
2929 
    .O(\frame_cnt<0>/CKMUXNOT )
2930 
  );
2931 
  defparam \frame_cnt<0>/G .INIT = 16'hFF00;
2932 
  X_LUT4 \frame_cnt<0>/G  (
2933 
    .ADR0(GLOBAL_LOGIC0_1),
2934 
    .ADR1(VCC),
2935 
    .ADR2(VCC),
2936 
    .ADR3(frame_cnt_1_1),
2937 
    .O(\frame_cnt<0>/GROM )
2938 
  );
2939 
  defparam frame_cnt_Madd__n0000_inst_lut2_51.INIT = 16'h3333;
2940 
  X_LUT4 frame_cnt_Madd__n0000_inst_lut2_51 (
2941 
    .ADR0(GLOBAL_LOGIC1_0),
2942 
    .ADR1(frame_cnt[0]),
2943 
    .ADR2(VCC),
2944 
    .ADR3(VCC),
2945 
    .O(frame_cnt_Madd__n0000_inst_lut2_5)
2946 
  );
2947 
  X_MUX2 frame_cnt_Madd__n0000_inst_cy_5_67 (
2948 
    .IA(GLOBAL_LOGIC1_0),
2949 
    .IB(\frame_cnt<0>/LOGIC_ZERO ),
2950 
    .SEL(frame_cnt_Madd__n0000_inst_lut2_5),
2951 
    .O(frame_cnt_Madd__n0000_inst_cy_5)
2952 
  );
2953 
  X_ZERO \frame_cnt<0>/LOGIC_ZERO_68  (
2954 
    .O(\frame_cnt<0>/LOGIC_ZERO )
2955 
  );
2956 
  X_OR2 \frame_cnt<0>/FFX/RSTOR  (
2957 
    .I0(\frame_cnt<0>/SRMUX_OUTPUTNOT ),
2958 
    .I1(GSR),
2959 
    .O(\frame_cnt<0>/FFX/RST )
2960 
  );
2961 
  X_FF frame_cnt_0 (
2962 
    .I(frame_cnt_Madd__n0000_inst_lut2_5),
2963 
    .CE(VCC),
2964 
    .CLK(\frame_cnt<0>/CKMUXNOT ),
2965 
    .SET(GND),
2966 
    .RST(\frame_cnt<0>/FFX/RST ),
2967 
    .O(frame_cnt[0])
2968 
  );
2969 
  X_OR2 \frame_cnt<0>/FFY/RSTOR  (
2970 
    .I0(\frame_cnt<0>/SRMUX_OUTPUTNOT ),
2971 
    .I1(GSR),
2972 
    .O(\frame_cnt<0>/FFY/RST )
2973 
  );
2974 
  X_FF frame_cnt_1 (
2975 
    .I(\frame_cnt<0>/XORG ),
2976 
    .CE(VCC),
2977 
    .CLK(\frame_cnt<0>/CKMUXNOT ),
2978 
    .SET(GND),
2979 
    .RST(\frame_cnt<0>/FFY/RST ),
2980 
    .O(frame_cnt[1])
2981 
  );
2982 
  X_BUF \frame_cnt<2>/CYINIT_69  (
2983 
    .I(\frame_cnt<0>/CYMUXG ),
2984 
    .O(\frame_cnt<2>/CYINIT )
2985 
  );
2986 
  X_INV \frame_cnt<2>/SRMUX  (
2987 
    .I(reset_IBUF),
2988 
    .O(\frame_cnt<2>/SRMUX_OUTPUTNOT )
2989 
  );
2990 
  X_XOR2 frame_cnt_Madd__n0000_inst_sum_8 (
2991 
    .I0(frame_cnt_Madd__n0000_inst_cy_7),
2992 
    .I1(\frame_cnt<2>/GROM ),
2993 
    .O(frame_cnt__n0000[3])
2994 
  );
2995 
  X_MUX2 frame_cnt_Madd__n0000_inst_cy_8 (
2996 
    .IA(\frame_cnt<2>/LOGIC_ZERO ),
2997 
    .IB(frame_cnt_Madd__n0000_inst_cy_7),
2998 
    .SEL(\frame_cnt<2>/GROM ),
2999 
    .O(\frame_cnt<2>/CYMUXG )
3000 
  );
3001 
  X_INV \frame_cnt<2>/CKINV  (
3002 
    .I(clk_in_BUFGP),
3003 
    .O(\frame_cnt<2>/CKMUXNOT )
3004 
  );
3005 
  defparam \frame_cnt<2>/G .INIT = 16'hF0F0;
3006 
  X_LUT4 \frame_cnt<2>/G  (
3007 
    .ADR0(VCC),
3008 
    .ADR1(VCC),
3009 
    .ADR2(frame_cnt[3]),
3010 
    .ADR3(VCC),
3011 
    .O(\frame_cnt<2>/GROM )
3012 
  );
3013 
  defparam \frame_cnt<2>/F .INIT = 16'hAAAA;
3014 
  X_LUT4 \frame_cnt<2>/F  (
3015 
    .ADR0(frame_cnt[2]),
3016 
    .ADR1(VCC),
3017 
    .ADR2(VCC),
3018 
    .ADR3(VCC),
3019 
    .O(\frame_cnt<2>/FROM )
3020 
  );
3021 
  X_XOR2 frame_cnt_Madd__n0000_inst_sum_7 (
3022 
    .I0(\frame_cnt<2>/CYINIT ),
3023 
    .I1(\frame_cnt<2>/FROM ),
3024 
    .O(frame_cnt__n0000[2])
3025 
  );
3026 
  X_MUX2 frame_cnt_Madd__n0000_inst_cy_7_70 (
3027 
    .IA(\frame_cnt<2>/LOGIC_ZERO ),
3028 
    .IB(\frame_cnt<2>/CYINIT ),
3029 
    .SEL(\frame_cnt<2>/FROM ),
3030 
    .O(frame_cnt_Madd__n0000_inst_cy_7)
3031 
  );
3032 
  X_ZERO \frame_cnt<2>/LOGIC_ZERO_71  (
3033 
    .O(\frame_cnt<2>/LOGIC_ZERO )
3034 
  );
3035 
  X_OR2 \frame_cnt<2>/FFX/RSTOR  (
3036 
    .I0(\frame_cnt<2>/SRMUX_OUTPUTNOT ),
3037 
    .I1(GSR),
3038 
    .O(\frame_cnt<2>/FFX/RST )
3039 
  );
3040 
  X_FF frame_cnt_2 (
3041 
    .I(frame_cnt__n0000[2]),
3042 
    .CE(VCC),
3043 
    .CLK(\frame_cnt<2>/CKMUXNOT ),
3044 
    .SET(GND),
3045 
    .RST(\frame_cnt<2>/FFX/RST ),
3046 
    .O(frame_cnt[2])
3047 
  );
3048 
  X_BUF \frame_cnt<4>/CYINIT_72  (
3049 
    .I(\frame_cnt<2>/CYMUXG ),
3050 
    .O(\frame_cnt<4>/CYINIT )
3051 
  );
3052 
  X_INV \frame_cnt<4>/SRMUX  (
3053 
    .I(reset_IBUF),
3054 
    .O(\frame_cnt<4>/SRMUX_OUTPUTNOT )
3055 
  );
3056 
  X_XOR2 frame_cnt_Madd__n0000_inst_sum_10 (
3057 
    .I0(frame_cnt_Madd__n0000_inst_cy_9),
3058 
    .I1(\frame_cnt<4>/GROM ),
3059 
    .O(frame_cnt__n0000[5])
3060 
  );
3061 
  X_MUX2 frame_cnt_Madd__n0000_inst_cy_10 (
3062 
    .IA(\frame_cnt<4>/LOGIC_ZERO ),
3063 
    .IB(frame_cnt_Madd__n0000_inst_cy_9),
3064 
    .SEL(\frame_cnt<4>/GROM ),
3065 
    .O(\frame_cnt<4>/CYMUXG )
3066 
  );
3067 
  X_INV \frame_cnt<4>/CKINV  (
3068 
    .I(clk_in_BUFGP),
3069 
    .O(\frame_cnt<4>/CKMUXNOT )
3070 
  );
3071 
  defparam \frame_cnt<4>/G .INIT = 16'hF0F0;
3072 
  X_LUT4 \frame_cnt<4>/G  (
3073 
    .ADR0(VCC),
3074 
    .ADR1(VCC),
3075 
    .ADR2(frame_cnt[5]),
3076 
    .ADR3(VCC),
3077 
    .O(\frame_cnt<4>/GROM )
3078 
  );
3079 
  defparam \frame_cnt<4>/F .INIT = 16'hCCCC;
3080 
  X_LUT4 \frame_cnt<4>/F  (
3081 
    .ADR0(VCC),
3082 
    .ADR1(frame_cnt[4]),
3083 
    .ADR2(VCC),
3084 
    .ADR3(VCC),
3085 
    .O(\frame_cnt<4>/FROM )
3086 
  );
3087 
  X_XOR2 frame_cnt_Madd__n0000_inst_sum_9 (
3088 
    .I0(\frame_cnt<4>/CYINIT ),
3089 
    .I1(\frame_cnt<4>/FROM ),
3090 
    .O(frame_cnt__n0000[4])
3091 
  );
3092 
  X_MUX2 frame_cnt_Madd__n0000_inst_cy_9_73 (
3093 
    .IA(\frame_cnt<4>/LOGIC_ZERO ),
3094 
    .IB(\frame_cnt<4>/CYINIT ),
3095 
    .SEL(\frame_cnt<4>/FROM ),
3096 
    .O(frame_cnt_Madd__n0000_inst_cy_9)
3097 
  );
3098 
  X_ZERO \frame_cnt<4>/LOGIC_ZERO_74  (
3099 
    .O(\frame_cnt<4>/LOGIC_ZERO )
3100 
  );
3101 
  X_OR2 \frame_cnt<4>/FFX/RSTOR  (
3102 
    .I0(\frame_cnt<4>/SRMUX_OUTPUTNOT ),
3103 
    .I1(GSR),
3104 
    .O(\frame_cnt<4>/FFX/RST )
3105 
  );
3106 
  X_FF frame_cnt_4 (
3107 
    .I(frame_cnt__n0000[4]),
3108 
    .CE(VCC),
3109 
    .CLK(\frame_cnt<4>/CKMUXNOT ),
3110 
    .SET(GND),
3111 
    .RST(\frame_cnt<4>/FFX/RST ),
3112 
    .O(frame_cnt[4])
3113 
  );
3114 
  X_OR2 \frame_cnt<4>/FFY/RSTOR  (
3115 
    .I0(\frame_cnt<4>/SRMUX_OUTPUTNOT ),
3116 
    .I1(GSR),
3117 
    .O(\frame_cnt<4>/FFY/RST )
3118 
  );
3119 
  X_FF frame_cnt_5 (
3120 
    .I(frame_cnt__n0000[5]),
3121 
    .CE(VCC),
3122 
    .CLK(\frame_cnt<4>/CKMUXNOT ),
3123 
    .SET(GND),
3124 
    .RST(\frame_cnt<4>/FFY/RST ),
3125 
    .O(frame_cnt[5])
3126 
  );
3127 
  X_BUF \frame_cnt<6>/CYINIT_75  (
3128 
    .I(\frame_cnt<4>/CYMUXG ),
3129 
    .O(\frame_cnt<6>/CYINIT )
3130 
  );
3131 
  X_INV \frame_cnt<6>/SRMUX  (
3132 
    .I(reset_IBUF),
3133 
    .O(\frame_cnt<6>/SRMUX_OUTPUTNOT )
3134 
  );
3135 
  X_XOR2 frame_cnt_Madd__n0000_inst_sum_12 (
3136 
    .I0(frame_cnt_Madd__n0000_inst_cy_11),
3137 
    .I1(\frame_cnt<6>/GROM ),
3138 
    .O(frame_cnt__n0000[7])
3139 
  );
3140 
  X_MUX2 frame_cnt_Madd__n0000_inst_cy_12 (
3141 
    .IA(\frame_cnt<6>/LOGIC_ZERO ),
3142 
    .IB(frame_cnt_Madd__n0000_inst_cy_11),
3143 
    .SEL(\frame_cnt<6>/GROM ),
3144 
    .O(\frame_cnt<6>/CYMUXG )
3145 
  );
3146 
  X_INV \frame_cnt<6>/CKINV  (
3147 
    .I(clk_in_BUFGP),
3148 
    .O(\frame_cnt<6>/CKMUXNOT )
3149 
  );
3150 
  defparam \frame_cnt<6>/G .INIT = 16'hF0F0;
3151 
  X_LUT4 \frame_cnt<6>/G  (
3152 
    .ADR0(VCC),
3153 
    .ADR1(VCC),
3154 
    .ADR2(frame_cnt[7]),
3155 
    .ADR3(VCC),
3156 
    .O(\frame_cnt<6>/GROM )
3157 
  );
3158 
  defparam \frame_cnt<6>/F .INIT = 16'hCCCC;
3159 
  X_LUT4 \frame_cnt<6>/F  (
3160 
    .ADR0(VCC),
3161 
    .ADR1(frame_cnt[6]),
3162 
    .ADR2(VCC),
3163 
    .ADR3(VCC),
3164 
    .O(\frame_cnt<6>/FROM )
3165 
  );
3166 
  X_XOR2 frame_cnt_Madd__n0000_inst_sum_11 (
3167 
    .I0(\frame_cnt<6>/CYINIT ),
3168 
    .I1(\frame_cnt<6>/FROM ),
3169 
    .O(frame_cnt__n0000[6])
3170 
  );
3171 
  X_MUX2 frame_cnt_Madd__n0000_inst_cy_11_76 (
3172 
    .IA(\frame_cnt<6>/LOGIC_ZERO ),
3173 
    .IB(\frame_cnt<6>/CYINIT ),
3174 
    .SEL(\frame_cnt<6>/FROM ),
3175 
    .O(frame_cnt_Madd__n0000_inst_cy_11)
3176 
  );
3177 
  X_ZERO \frame_cnt<6>/LOGIC_ZERO_77  (
3178 
    .O(\frame_cnt<6>/LOGIC_ZERO )
3179 
  );
3180 
  X_OR2 \frame_cnt<6>/FFX/RSTOR  (
3181 
    .I0(\frame_cnt<6>/SRMUX_OUTPUTNOT ),
3182 
    .I1(GSR),
3183 
    .O(\frame_cnt<6>/FFX/RST )
3184 
  );
3185 
  X_FF frame_cnt_6 (
3186 
    .I(frame_cnt__n0000[6]),
3187 
    .CE(VCC),
3188 
    .CLK(\frame_cnt<6>/CKMUXNOT ),
3189 
    .SET(GND),
3190 
    .RST(\frame_cnt<6>/FFX/RST ),
3191 
    .O(frame_cnt[6])
3192 
  );
3193 
  X_OR2 \frame_cnt<6>/FFY/RSTOR  (
3194 
    .I0(\frame_cnt<6>/SRMUX_OUTPUTNOT ),
3195 
    .I1(GSR),
3196 
    .O(\frame_cnt<6>/FFY/RST )
3197 
  );
3198 
  X_FF frame_cnt_7 (
3199 
    .I(frame_cnt__n0000[7]),
3200 
    .CE(VCC),
3201 
    .CLK(\frame_cnt<6>/CKMUXNOT ),
3202 
    .SET(GND),
3203 
    .RST(\frame_cnt<6>/FFY/RST ),
3204 
    .O(frame_cnt[7])
3205 
  );
3206 
  X_BUF \frame_cnt<8>/CYINIT_78  (
3207 
    .I(\frame_cnt<6>/CYMUXG ),
3208 
    .O(\frame_cnt<8>/CYINIT )
3209 
  );
3210 
  X_INV \frame_cnt<8>/SRMUX  (
3211 
    .I(reset_IBUF),
3212 
    .O(\frame_cnt<8>/SRMUX_OUTPUTNOT )
3213 
  );
3214 
  X_INV \frame_cnt<8>/CKINV  (
3215 
    .I(clk_in_BUFGP),
3216 
    .O(\frame_cnt<8>/CKMUXNOT )
3217 
  );
3218 
  defparam \frame_cnt<8>_rt_79 .INIT = 16'hAAAA;
3219 
  X_LUT4 \frame_cnt<8>_rt_79  (
3220 
    .ADR0(frame_cnt[8]),
3221 
    .ADR1(VCC),
3222 
    .ADR2(VCC),
3223 
    .ADR3(VCC),
3224 
    .O(\frame_cnt<8>_rt )
3225 
  );
3226 
  X_XOR2 frame_cnt_Madd__n0000_inst_sum_13 (
3227 
    .I0(\frame_cnt<8>/CYINIT ),
3228 
    .I1(\frame_cnt<8>_rt ),
3229 
    .O(frame_cnt__n0000[8])
3230 
  );
3231 
  X_OR2 \frame_cnt<8>/FFX/RSTOR  (
3232 
    .I0(\frame_cnt<8>/SRMUX_OUTPUTNOT ),
3233 
    .I1(GSR),
3234 
    .O(\frame_cnt<8>/FFX/RST )
3235 
  );
3236 
  X_FF frame_cnt_8 (
3237 
    .I(frame_cnt__n0000[8]),
3238 
    .CE(VCC),
3239 
    .CLK(\frame_cnt<8>/CKMUXNOT ),
3240 
    .SET(GND),
3241 
    .RST(\frame_cnt<8>/FFX/RST ),
3242 
    .O(frame_cnt[8])
3243 
  );
3244 
  X_BUF \rx_buf_reg_0<1>/YUSED  (
3245 
    .I(\rx_buf_reg_0<1>/GROM ),
3246 
    .O(\_n00631/O )
3247 
  );
3248 
  defparam _n00631.INIT = 16'h0F00;
3249 
  X_LUT4 _n00631 (
3250 
    .ADR0(VCC),
3251 
    .ADR1(VCC),
3252 
    .ADR2(frame_delay_cnt_0_1_0),
3253 
    .ADR3(frame_delay_cnt_0_0_0),
3254 
    .O(\rx_buf_reg_0<1>/GROM )
3255 
  );
3256 
  X_BUF \rx_buf_reg_0<1>/FFY/RSTOR  (
3257 
    .I(GSR),
3258 
    .O(\rx_buf_reg_0<1>/FFY/RST )
3259 
  );
3260 
  X_FF rx_buf_reg_0_0 (
3261 
    .I(rx_shift_reg_0[0]),
3262 
    .CE(\_n00631/O ),
3263 
    .CLK(div_reg),
3264 
    .SET(GND),
3265 
    .RST(\rx_buf_reg_0<1>/FFY/RST ),
3266 
    .O(rx_buf_reg_0[0])
3267 
  );
3268 
  X_BUF \rx_buf_reg_0<1>/FFX/RSTOR  (
3269 
    .I(GSR),
3270 
    .O(\rx_buf_reg_0<1>/FFX/RST )
3271 
  );
3272 
  X_FF rx_buf_reg_0_1 (
3273 
    .I(rx_shift_reg_0[1]),
3274 
    .CE(\_n00631/O ),
3275 
    .CLK(div_reg),
3276 
    .SET(GND),
3277 
    .RST(\rx_buf_reg_0<1>/FFX/RST ),
3278 
    .O(rx_buf_reg_0[1])
3279 
  );
3280 
  X_BUF \rx_buf_reg_1<1>/YUSED  (
3281 
    .I(\rx_buf_reg_1<1>/GROM ),
3282 
    .O(\_n00621/O )
3283 
  );
3284 
  defparam _n00621.INIT = 16'h5500;
3285 
  X_LUT4 _n00621 (
3286 
    .ADR0(frame_delay_cnt_1_1_0),
3287 
    .ADR1(VCC),
3288 
    .ADR2(VCC),
3289 
    .ADR3(frame_delay_cnt_1_0_0),
3290 
    .O(\rx_buf_reg_1<1>/GROM )
3291 
  );
3292 
  X_BUF \rx_buf_reg_1<1>/FFY/RSTOR  (
3293 
    .I(GSR),
3294 
    .O(\rx_buf_reg_1<1>/FFY/RST )
3295 
  );
3296 
  X_FF rx_buf_reg_1_0 (
3297 
    .I(rx_shift_reg_1[0]),
3298 
    .CE(\_n00621/O ),
3299 
    .CLK(div_reg),
3300 
    .SET(GND),
3301 
    .RST(\rx_buf_reg_1<1>/FFY/RST ),
3302 
    .O(rx_buf_reg_1[0])
3303 
  );
3304 
  X_BUF \rx_buf_reg_1<1>/FFX/RSTOR  (
3305 
    .I(GSR),
3306 
    .O(\rx_buf_reg_1<1>/FFX/RST )
3307 
  );
3308 
  X_FF rx_buf_reg_1_1 (
3309 
    .I(rx_shift_reg_1[1]),
3310 
    .CE(\_n00621/O ),
3311 
    .CLK(div_reg),
3312 
    .SET(GND),
3313 
    .RST(\rx_buf_reg_1<1>/FFX/RST ),
3314 
    .O(rx_buf_reg_1[1])
3315 
  );
3316 
  X_BUF \rx_buf_reg_2<1>/YUSED  (
3317 
    .I(\rx_buf_reg_2<1>/GROM ),
3318 
    .O(\_n00611/O )
3319 
  );
3320 
  defparam _n00611.INIT = 16'h0C0C;
3321 
  X_LUT4 _n00611 (
3322 
    .ADR0(VCC),
3323 
    .ADR1(frame_delay_cnt_2_0_0),
3324 
    .ADR2(frame_delay_cnt_2_1_0),
3325 
    .ADR3(VCC),
3326 
    .O(\rx_buf_reg_2<1>/GROM )
3327 
  );
3328 
  X_BUF \rx_buf_reg_2<1>/FFX/RSTOR  (
3329 
    .I(GSR),
3330 
    .O(\rx_buf_reg_2<1>/FFX/RST )
3331 
  );
3332 
  X_FF rx_buf_reg_2_1 (
3333 
    .I(rx_shift_reg_2[1]),
3334 
    .CE(\_n00611/O ),
3335 
    .CLK(div_reg),
3336 
    .SET(GND),
3337 
    .RST(\rx_buf_reg_2<1>/FFX/RST ),
3338 
    .O(rx_buf_reg_2[1])
3339 
  );
3340 
  X_BUF \rx_buf_reg_2<1>/FFY/RSTOR  (
3341 
    .I(GSR),
3342 
    .O(\rx_buf_reg_2<1>/FFY/RST )
3343 
  );
3344 
  X_FF rx_buf_reg_2_0 (
3345 
    .I(rx_shift_reg_2[0]),
3346 
    .CE(\_n00611/O ),
3347 
    .CLK(div_reg),
3348 
    .SET(GND),
3349 
    .RST(\rx_buf_reg_2<1>/FFY/RST ),
3350 
    .O(rx_buf_reg_2[0])
3351 
  );
3352 
  X_BUF \rx_buf_reg_3<1>/YUSED  (
3353 
    .I(\rx_buf_reg_3<1>/GROM ),
3354 
    .O(\_n00601/O )
3355 
  );
3356 
  defparam _n00601.INIT = 16'h4444;
3357 
  X_LUT4 _n00601 (
3358 
    .ADR0(frame_delay_cnt_3_1_0),
3359 
    .ADR1(frame_delay_cnt_3_0_0),
3360 
    .ADR2(VCC),
3361 
    .ADR3(VCC),
3362 
    .O(\rx_buf_reg_3<1>/GROM )
3363 
  );
3364 
  X_BUF \rx_buf_reg_3<1>/FFX/RSTOR  (
3365 
    .I(GSR),
3366 
    .O(\rx_buf_reg_3<1>/FFX/RST )
3367 
  );
3368 
  X_FF rx_buf_reg_3_1 (
3369 
    .I(rx_shift_reg_3[1]),
3370 
    .CE(\_n00601/O ),
3371 
    .CLK(div_reg),
3372 
    .SET(GND),
3373 
    .RST(\rx_buf_reg_3<1>/FFX/RST ),
3374 
    .O(rx_buf_reg_3[1])
3375 
  );
3376 
  X_BUF \rx_buf_reg_3<1>/FFY/RSTOR  (
3377 
    .I(GSR),
3378 
    .O(\rx_buf_reg_3<1>/FFY/RST )
3379 
  );
3380 
  X_FF rx_buf_reg_3_0 (
3381 
    .I(rx_shift_reg_3[0]),
3382 
    .CE(\_n00601/O ),
3383 
    .CLK(div_reg),
3384 
    .SET(GND),
3385 
    .RST(\rx_buf_reg_3<1>/FFY/RST ),
3386 
    .O(rx_buf_reg_3[0])
3387 
  );
3388 
  X_BUF \rx_buf_reg_4<1>/YUSED  (
3389 
    .I(\rx_buf_reg_4<1>/GROM ),
3390 
    .O(\_n00591/O )
3391 
  );
3392 
  defparam _n00591.INIT = 16'h0F00;
3393 
  X_LUT4 _n00591 (
3394 
    .ADR0(VCC),
3395 
    .ADR1(VCC),
3396 
    .ADR2(frame_delay_cnt_4_1_0),
3397 
    .ADR3(frame_delay_cnt_4_0_0),
3398 
    .O(\rx_buf_reg_4<1>/GROM )
3399 
  );
3400 
  X_BUF \rx_buf_reg_4<1>/FFX/RSTOR  (
3401 
    .I(GSR),
3402 
    .O(\rx_buf_reg_4<1>/FFX/RST )
3403 
  );
3404 
  X_FF rx_buf_reg_4_1 (
3405 
    .I(rx_shift_reg_4[1]),
3406 
    .CE(\_n00591/O ),
3407 
    .CLK(div_reg),
3408 
    .SET(GND),
3409 
    .RST(\rx_buf_reg_4<1>/FFX/RST ),
3410 
    .O(rx_buf_reg_4[1])
3411 
  );
3412 
  X_BUF \rx_buf_reg_4<1>/FFY/RSTOR  (
3413 
    .I(GSR),
3414 
    .O(\rx_buf_reg_4<1>/FFY/RST )
3415 
  );
3416 
  X_FF rx_buf_reg_4_0 (
3417 
    .I(rx_shift_reg_4[0]),
3418 
    .CE(\_n00591/O ),
3419 
    .CLK(div_reg),
3420 
    .SET(GND),
3421 
    .RST(\rx_buf_reg_4<1>/FFY/RST ),
3422 
    .O(rx_buf_reg_4[0])
3423 
  );
3424 
  X_BUF \rx_buf_reg_5<1>/YUSED  (
3425 
    .I(\rx_buf_reg_5<1>/GROM ),
3426 
    .O(\_n00581/O )
3427 
  );
3428 
  defparam _n00581.INIT = 16'h0F00;
3429 
  X_LUT4 _n00581 (
3430 
    .ADR0(VCC),
3431 
    .ADR1(VCC),
3432 
    .ADR2(frame_delay_cnt_5_1_0),
3433 
    .ADR3(frame_delay_cnt_5_0_0),
3434 
    .O(\rx_buf_reg_5<1>/GROM )
3435 
  );
3436 
  X_BUF \rx_buf_reg_5<1>/FFY/RSTOR  (
3437 
    .I(GSR),
3438 
    .O(\rx_buf_reg_5<1>/FFY/RST )
3439 
  );
3440 
  X_FF rx_buf_reg_5_0 (
3441 
    .I(rx_shift_reg_5[0]),
3442 
    .CE(\_n00581/O ),
3443 
    .CLK(div_reg),
3444 
    .SET(GND),
3445 
    .RST(\rx_buf_reg_5<1>/FFY/RST ),
3446 
    .O(rx_buf_reg_5[0])
3447 
  );
3448 
  X_BUF \rx_buf_reg_5<1>/FFX/RSTOR  (
3449 
    .I(GSR),
3450 
    .O(\rx_buf_reg_5<1>/FFX/RST )
3451 
  );
3452 
  X_FF rx_buf_reg_5_1 (
3453 
    .I(rx_shift_reg_5[1]),
3454 
    .CE(\_n00581/O ),
3455 
    .CLK(div_reg),
3456 
    .SET(GND),
3457 
    .RST(\rx_buf_reg_5<1>/FFX/RST ),
3458 
    .O(rx_buf_reg_5[1])
3459 
  );
3460 
  X_BUF \rx_buf_reg_6<1>/YUSED  (
3461 
    .I(\rx_buf_reg_6<1>/GROM ),
3462 
    .O(\_n00571/O )
3463 
  );
3464 
  defparam _n00571.INIT = 16'h00F0;
3465 
  X_LUT4 _n00571 (
3466 
    .ADR0(VCC),
3467 
    .ADR1(VCC),
3468 
    .ADR2(frame_delay_cnt_6_0_0),
3469 
    .ADR3(frame_delay_cnt_6_1_0),
3470 
    .O(\rx_buf_reg_6<1>/GROM )
3471 
  );
3472 
  X_BUF \rx_buf_reg_6<1>/FFY/RSTOR  (
3473 
    .I(GSR),
3474 
    .O(\rx_buf_reg_6<1>/FFY/RST )
3475 
  );
3476 
  X_FF rx_buf_reg_6_0 (
3477 
    .I(rx_shift_reg_6[0]),
3478 
    .CE(\_n00571/O ),
3479 
    .CLK(div_reg),
3480 
    .SET(GND),
3481 
    .RST(\rx_buf_reg_6<1>/FFY/RST ),
3482 
    .O(rx_buf_reg_6[0])
3483 
  );
3484 
  X_BUF \rx_buf_reg_6<1>/FFX/RSTOR  (
3485 
    .I(GSR),
3486 
    .O(\rx_buf_reg_6<1>/FFX/RST )
3487 
  );
3488 
  X_FF rx_buf_reg_6_1 (
3489 
    .I(rx_shift_reg_6[1]),
3490 
    .CE(\_n00571/O ),
3491 
    .CLK(div_reg),
3492 
    .SET(GND),
3493 
    .RST(\rx_buf_reg_6<1>/FFX/RST ),
3494 
    .O(rx_buf_reg_6[1])
3495 
  );
3496 
  X_BUF \rx_buf_reg_7<1>/YUSED  (
3497 
    .I(\rx_buf_reg_7<1>/GROM ),
3498 
    .O(\_n00561/O )
3499 
  );
3500 
  defparam _n00561.INIT = 16'h0F00;
3501 
  X_LUT4 _n00561 (
3502 
    .ADR0(VCC),
3503 
    .ADR1(VCC),
3504 
    .ADR2(frame_delay_cnt_7_1_0),
3505 
    .ADR3(frame_delay_cnt_7_0_0),
3506 
    .O(\rx_buf_reg_7<1>/GROM )
3507 
  );
3508 
  X_BUF \rx_buf_reg_7<1>/FFY/RSTOR  (
3509 
    .I(GSR),
3510 
    .O(\rx_buf_reg_7<1>/FFY/RST )
3511 
  );
3512 
  X_FF rx_buf_reg_7_0 (
3513 
    .I(rx_shift_reg_7[0]),
3514 
    .CE(\_n00561/O ),
3515 
    .CLK(div_reg_2),
3516 
    .SET(GND),
3517 
    .RST(\rx_buf_reg_7<1>/FFY/RST ),
3518 
    .O(rx_buf_reg_7[0])
3519 
  );
3520 
  X_BUF \rx_buf_reg_7<1>/FFX/RSTOR  (
3521 
    .I(GSR),
3522 
    .O(\rx_buf_reg_7<1>/FFX/RST )
3523 
  );
3524 
  X_FF rx_buf_reg_7_1 (
3525 
    .I(rx_shift_reg_7[1]),
3526 
    .CE(\_n00561/O ),
3527 
    .CLK(div_reg_2),
3528 
    .SET(GND),
3529 
    .RST(\rx_buf_reg_7<1>/FFX/RST ),
3530 
    .O(rx_buf_reg_7[1])
3531 
  );
3532 
  X_BUF \tx_buf_reg_4<1>/YUSED  (
3533 
    .I(\tx_buf_reg_4<1>/GROM ),
3534 
    .O(\_n00311/O )
3535 
  );
3536 
  defparam _n00311.INIT = 16'h0400;
3537 
  X_LUT4 _n00311 (
3538 
    .ADR0(frame_cnt[3]),
3539 
    .ADR1(frame_cnt[2]),
3540 
    .ADR2(frame_cnt[0]),
3541 
    .ADR3(frame_cnt[1]),
3542 
    .O(\tx_buf_reg_4<1>/GROM )
3543 
  );
3544 
  X_BUF \tx_buf_reg_4<1>/FFY/RSTOR  (
3545 
    .I(GSR),
3546 
    .O(\tx_buf_reg_4<1>/FFY/RST )
3547 
  );
3548 
  X_FF tx_buf_reg_4_0 (
3549 
    .I(data_out_bus[0]),
3550 
    .CE(\_n00311/O ),
3551 
    .CLK(clk_in_BUFGP),
3552 
    .SET(GND),
3553 
    .RST(\tx_buf_reg_4<1>/FFY/RST ),
3554 
    .O(tx_buf_reg_4[0])
3555 
  );
3556 
  X_BUF \tx_buf_reg_4<1>/FFX/RSTOR  (
3557 
    .I(GSR),
3558 
    .O(\tx_buf_reg_4<1>/FFX/RST )
3559 
  );
3560 
  X_FF tx_buf_reg_4_1 (
3561 
    .I(data_out_bus[1]),
3562 
    .CE(\_n00311/O ),
3563 
    .CLK(clk_in_BUFGP),
3564 
    .SET(GND),
3565 
    .RST(\tx_buf_reg_4<1>/FFX/RST ),
3566 
    .O(tx_buf_reg_4[1])
3567 
  );
3568 
  X_BUF \tx_buf_reg_5<1>/YUSED  (
3569 
    .I(\tx_buf_reg_5<1>/GROM ),
3570 
    .O(\_n00321/O )
3571 
  );
3572 
  defparam _n00321.INIT = 16'h0080;
3573 
  X_LUT4 _n00321 (
3574 
    .ADR0(frame_cnt[1]),
3575 
    .ADR1(frame_cnt[0]),
3576 
    .ADR2(frame_cnt[2]),
3577 
    .ADR3(frame_cnt[3]),
3578 
    .O(\tx_buf_reg_5<1>/GROM )
3579 
  );
3580 
  X_BUF \tx_buf_reg_5<1>/FFY/RSTOR  (
3581 
    .I(GSR),
3582 
    .O(\tx_buf_reg_5<1>/FFY/RST )
3583 
  );
3584 
  X_FF tx_buf_reg_5_0 (
3585 
    .I(data_out_bus[0]),
3586 
    .CE(\_n00321/O ),
3587 
    .CLK(clk_in_BUFGP),
3588 
    .SET(GND),
3589 
    .RST(\tx_buf_reg_5<1>/FFY/RST ),
3590 
    .O(tx_buf_reg_5[0])
3591 
  );
3592 
  X_BUF \tx_buf_reg_5<1>/FFX/RSTOR  (
3593 
    .I(GSR),
3594 
    .O(\tx_buf_reg_5<1>/FFX/RST )
3595 
  );
3596 
  X_FF tx_buf_reg_5_1 (
3597 
    .I(data_out_bus[1]),
3598 
    .CE(\_n00321/O ),
3599 
    .CLK(clk_in_BUFGP),
3600 
    .SET(GND),
3601 
    .RST(\tx_buf_reg_5<1>/FFX/RST ),
3602 
    .O(tx_buf_reg_5[1])
3603 
  );
3604 
  defparam Mmux__n0019_I6_Result1.INIT = 16'hD8D8;
3605 
  X_LUT4 Mmux__n0019_I6_Result1 (
3606 
    .ADR0(Ker87891_1),
3607 
    .ADR1(tx_buf_reg_0[1]),
3608 
    .ADR2(tx_shift_reg_0[2]),
3609 
    .ADR3(VCC),
3610 
    .O(_n0019[1])
3611 
  );
3612 
  defparam Mmux__n0019_I5_Result1.INIT = 16'hAFA0;
3613 
  X_LUT4 Mmux__n0019_I5_Result1 (
3614 
    .ADR0(tx_buf_reg_0[2]),
3615 
    .ADR1(VCC),
3616 
    .ADR2(Ker87891_1),
3617 
    .ADR3(tx_shift_reg_0[3]),
3618 
    .O(_n0019[2])
3619 
  );
3620 
  X_BUF \tx_shift_reg_0<2>/FFY/RSTOR  (
3621 
    .I(GSR),
3622 
    .O(\tx_shift_reg_0<2>/FFY/RST )
3623 
  );
3624 
  X_FF tx_shift_reg_0_1 (
3625 
    .I(_n0019[1]),
3626 
    .CE(VCC),
3627 
    .CLK(div_reg_1),
3628 
    .SET(GND),
3629 
    .RST(\tx_shift_reg_0<2>/FFY/RST ),
3630 
    .O(tx_shift_reg_0[1])
3631 
  );
3632 
  X_BUF \tx_shift_reg_0<2>/FFX/RSTOR  (
3633 
    .I(GSR),
3634 
    .O(\tx_shift_reg_0<2>/FFX/RST )
3635 
  );
3636 
  X_FF tx_shift_reg_0_2 (
3637 
    .I(_n0019[2]),
3638 
    .CE(VCC),
3639 
    .CLK(div_reg_1),
3640 
    .SET(GND),
3641 
    .RST(\tx_shift_reg_0<2>/FFX/RST ),
3642 
    .O(tx_shift_reg_0[2])
3643 
  );
3644 
  defparam Mmux__n0019_I4_Result1.INIT = 16'hFA50;
3645 
  X_LUT4 Mmux__n0019_I4_Result1 (
3646 
    .ADR0(Ker87891_1),
3647 
    .ADR1(VCC),
3648 
    .ADR2(tx_shift_reg_0[4]),
3649 
    .ADR3(tx_buf_reg_0[3]),
3650 
    .O(_n0019[3])
3651 
  );
3652 
  defparam Mmux__n0019_I3_Result1.INIT = 16'hCFC0;
3653 
  X_LUT4 Mmux__n0019_I3_Result1 (
3654 
    .ADR0(VCC),
3655 
    .ADR1(tx_buf_reg_0[4]),
3656 
    .ADR2(Ker87891_1),
3657 
    .ADR3(tx_shift_reg_0[5]),
3658 
    .O(_n0019[4])
3659 
  );
3660 
  X_BUF \tx_shift_reg_0<4>/FFY/RSTOR  (
3661 
    .I(GSR),
3662 
    .O(\tx_shift_reg_0<4>/FFY/RST )
3663 
  );
3664 
  X_FF tx_shift_reg_0_3 (
3665 
    .I(_n0019[3]),
3666 
    .CE(VCC),
3667 
    .CLK(div_reg_1),
3668 
    .SET(GND),
3669 
    .RST(\tx_shift_reg_0<4>/FFY/RST ),
3670 
    .O(tx_shift_reg_0[3])
3671 
  );
3672 
  X_BUF \tx_shift_reg_0<4>/FFX/RSTOR  (
3673 
    .I(GSR),
3674 
    .O(\tx_shift_reg_0<4>/FFX/RST )
3675 
  );
3676 
  X_FF tx_shift_reg_0_4 (
3677 
    .I(_n0019[4]),
3678 
    .CE(VCC),
3679 
    .CLK(div_reg_1),
3680 
    .SET(GND),
3681 
    .RST(\tx_shift_reg_0<4>/FFX/RST ),
3682 
    .O(tx_shift_reg_0[4])
3683 
  );
3684 
  defparam Mmux__n0020_I6_Result1.INIT = 16'hAFA0;
3685 
  X_LUT4 Mmux__n0020_I6_Result1 (
3686 
    .ADR0(tx_buf_reg_1[1]),
3687 
    .ADR1(VCC),
3688 
    .ADR2(Ker87891_1),
3689 
    .ADR3(tx_shift_reg_1[2]),
3690 
    .O(_n0020[1])
3691 
  );
3692 
  defparam Mmux__n0020_I5_Result1.INIT = 16'hF3C0;
3693 
  X_LUT4 Mmux__n0020_I5_Result1 (
3694 
    .ADR0(VCC),
3695 
    .ADR1(Ker87891_1),
3696 
    .ADR2(tx_buf_reg_1[2]),
3697 
    .ADR3(tx_shift_reg_1[3]),
3698 
    .O(_n0020[2])
3699 
  );
3700 
  X_BUF \tx_shift_reg_1<2>/FFY/RSTOR  (
3701 
    .I(GSR),
3702 
    .O(\tx_shift_reg_1<2>/FFY/RST )
3703 
  );
3704 
  X_FF tx_shift_reg_1_1 (
3705 
    .I(_n0020[1]),
3706 
    .CE(VCC),
3707 
    .CLK(div_reg_1),
3708 
    .SET(GND),
3709 
    .RST(\tx_shift_reg_1<2>/FFY/RST ),
3710 
    .O(tx_shift_reg_1[1])
3711 
  );
3712 
  X_BUF \tx_shift_reg_1<2>/FFX/RSTOR  (
3713 
    .I(GSR),
3714 
    .O(\tx_shift_reg_1<2>/FFX/RST )
3715 
  );
3716 
  X_FF tx_shift_reg_1_2 (
3717 
    .I(_n0020[2]),
3718 
    .CE(VCC),
3719 
    .CLK(div_reg_1),
3720 
    .SET(GND),
3721 
    .RST(\tx_shift_reg_1<2>/FFX/RST ),
3722 
    .O(tx_shift_reg_1[2])
3723 
  );
3724 
  defparam Mmux__n0019_I2_Result1.INIT = 16'hFA50;
3725 
  X_LUT4 Mmux__n0019_I2_Result1 (
3726 
    .ADR0(N8791),
3727 
    .ADR1(VCC),
3728 
    .ADR2(tx_shift_reg_0[6]),
3729 
    .ADR3(tx_buf_reg_0[5]),
3730 
    .O(_n0019[5])
3731 
  );
3732 
  defparam Mmux__n0019_I1_Result1.INIT = 16'hE4E4;
3733 
  X_LUT4 Mmux__n0019_I1_Result1 (
3734 
    .ADR0(N8791),
3735 
    .ADR1(tx_shift_reg_0[7]),
3736 
    .ADR2(tx_buf_reg_0[6]),
3737 
    .ADR3(VCC),
3738 
    .O(_n0019[6])
3739 
  );
3740 
  X_BUF \tx_shift_reg_0<6>/FFY/RSTOR  (
3741 
    .I(GSR),
3742 
    .O(\tx_shift_reg_0<6>/FFY/RST )
3743 
  );
3744 
  X_FF tx_shift_reg_0_5 (
3745 
    .I(_n0019[5]),
3746 
    .CE(VCC),
3747 
    .CLK(div_reg_1),
3748 
    .SET(GND),
3749 
    .RST(\tx_shift_reg_0<6>/FFY/RST ),
3750 
    .O(tx_shift_reg_0[5])
3751 
  );
3752 
  X_BUF \tx_shift_reg_0<6>/FFX/RSTOR  (
3753 
    .I(GSR),
3754 
    .O(\tx_shift_reg_0<6>/FFX/RST )
3755 
  );
3756 
  X_FF tx_shift_reg_0_6 (
3757 
    .I(_n0019[6]),
3758 
    .CE(VCC),
3759 
    .CLK(div_reg_1),
3760 
    .SET(GND),
3761 
    .RST(\tx_shift_reg_0<6>/FFX/RST ),
3762 
    .O(tx_shift_reg_0[6])
3763 
  );
3764 
  X_BUF \tx_shift_reg_0<7>/XUSED  (
3765 
    .I(\tx_shift_reg_0<7>/FROM ),
3766 
    .O(N8791)
3767 
  );
3768 
  defparam Mmux__n0019_I0_Result1.INIT = 16'hF000;
3769 
  X_LUT4 Mmux__n0019_I0_Result1 (
3770 
    .ADR0(VCC),
3771 
    .ADR1(VCC),
3772 
    .ADR2(tx_buf_reg_0[7]),
3773 
    .ADR3(N8791),
3774 
    .O(_n0019[7])
3775 
  );
3776 
  defparam Ker87891.INIT = 16'h1000;
3777 
  X_LUT4 Ker87891 (
3778 
    .ADR0(frame_cnt[0]),
3779 
    .ADR1(frame_cnt[2]),
3780 
    .ADR2(frame_cnt[3]),
3781 
    .ADR3(frame_cnt_1_1),
3782 
    .O(\tx_shift_reg_0<7>/FROM )
3783 
  );
3784 
  X_BUF \tx_shift_reg_0<7>/FFY/RSTOR  (
3785 
    .I(GSR),
3786 
    .O(\tx_shift_reg_0<7>/FFY/RST )
3787 
  );
3788 
  X_FF tx_shift_reg_0_7 (
3789 
    .I(_n0019[7]),
3790 
    .CE(VCC),
3791 
    .CLK(div_reg_1),
3792 
    .SET(GND),
3793 
    .RST(\tx_shift_reg_0<7>/FFY/RST ),
3794 
    .O(tx_shift_reg_0[7])
3795 
  );
3796 
  defparam Mmux__n0020_I4_Result1.INIT = 16'hCCF0;
3797 
  X_LUT4 Mmux__n0020_I4_Result1 (
3798 
    .ADR0(VCC),
3799 
    .ADR1(tx_buf_reg_1[3]),
3800 
    .ADR2(tx_shift_reg_1[4]),
3801 
    .ADR3(Ker87891_1),
3802 
    .O(_n0020[3])
3803 
  );
3804 
  defparam Mmux__n0020_I3_Result1.INIT = 16'hAACC;
3805 
  X_LUT4 Mmux__n0020_I3_Result1 (
3806 
    .ADR0(tx_buf_reg_1[4]),
3807 
    .ADR1(tx_shift_reg_1[5]),
3808 
    .ADR2(VCC),
3809 
    .ADR3(Ker87891_1),
3810 
    .O(_n0020[4])
3811 
  );
3812 
  X_BUF \tx_shift_reg_1<4>/FFX/RSTOR  (
3813 
    .I(GSR),
3814 
    .O(\tx_shift_reg_1<4>/FFX/RST )
3815 
  );
3816 
  X_FF tx_shift_reg_1_4 (
3817 
    .I(_n0020[4]),
3818 
    .CE(VCC),
3819 
    .CLK(div_reg_1),
3820 
    .SET(GND),
3821 
    .RST(\tx_shift_reg_1<4>/FFX/RST ),
3822 
    .O(tx_shift_reg_1[4])
3823 
  );
3824 
  X_BUF \tx_shift_reg_1<4>/FFY/RSTOR  (
3825 
    .I(GSR),
3826 
    .O(\tx_shift_reg_1<4>/FFY/RST )
3827 
  );
3828 
  X_FF tx_shift_reg_1_3 (
3829 
    .I(_n0020[3]),
3830 
    .CE(VCC),
3831 
    .CLK(div_reg_1),
3832 
    .SET(GND),
3833 
    .RST(\tx_shift_reg_1<4>/FFY/RST ),
3834 
    .O(tx_shift_reg_1[3])
3835 
  );
3836 
  defparam Mmux__n0021_I6_Result1.INIT = 16'hFA50;
3837 
  X_LUT4 Mmux__n0021_I6_Result1 (
3838 
    .ADR0(Ker87891_1),
3839 
    .ADR1(VCC),
3840 
    .ADR2(tx_shift_reg_2[2]),
3841 
    .ADR3(tx_buf_reg_2[1]),
3842 
    .O(_n0021[1])
3843 
  );
3844 
  defparam Mmux__n0021_I5_Result1.INIT = 16'hD8D8;
3845 
  X_LUT4 Mmux__n0021_I5_Result1 (
3846 
    .ADR0(Ker87891_1),
3847 
    .ADR1(tx_buf_reg_2[2]),
3848 
    .ADR2(tx_shift_reg_2[3]),
3849 
    .ADR3(VCC),
3850 
    .O(_n0021[2])
3851 
  );
3852 
  defparam Mmux__n0020_I2_Result1.INIT = 16'hF5A0;
3853 
  X_LUT4 Mmux__n0020_I2_Result1 (
3854 
    .ADR0(Ker87891_1),
3855 
    .ADR1(VCC),
3856 
    .ADR2(tx_buf_reg_1[5]),
3857 
    .ADR3(tx_shift_reg_1[6]),
3858 
    .O(_n0020[5])
3859 
  );
3860 
  defparam Mmux__n0020_I1_Result1.INIT = 16'hDD88;
3861 
  X_LUT4 Mmux__n0020_I1_Result1 (
3862 
    .ADR0(Ker87891_1),
3863 
    .ADR1(tx_buf_reg_1[6]),
3864 
    .ADR2(VCC),
3865 
    .ADR3(tx_shift_reg_1[7]),
3866 
    .O(_n0020[6])
3867 
  );
3868 
  defparam Mmux__n0021_I4_Result1.INIT = 16'hFC0C;
3869 
  X_LUT4 Mmux__n0021_I4_Result1 (
3870 
    .ADR0(VCC),
3871 
    .ADR1(tx_shift_reg_2[4]),
3872 
    .ADR2(Ker87891_1),
3873 
    .ADR3(tx_buf_reg_2[3]),
3874 
    .O(_n0021[3])
3875 
  );
3876 
  defparam Mmux__n0021_I3_Result1.INIT = 16'hCFC0;
3877 
  X_LUT4 Mmux__n0021_I3_Result1 (
3878 
    .ADR0(VCC),
3879 
    .ADR1(tx_buf_reg_2[4]),
3880 
    .ADR2(Ker87891_1),
3881 
    .ADR3(tx_shift_reg_2[5]),
3882 
    .O(_n0021[4])
3883 
  );
3884 
  defparam Mmux__n0020_I0_Result1.INIT = 16'hAA00;
3885 
  X_LUT4 Mmux__n0020_I0_Result1 (
3886 
    .ADR0(tx_buf_reg_1[7]),
3887 
    .ADR1(VCC),
3888 
    .ADR2(VCC),
3889 
    .ADR3(Ker87891_1),
3890 
    .O(_n0020[7])
3891 
  );
3892 
  defparam Mmux__n0021_I0_Result1.INIT = 16'hF000;
3893 
  X_LUT4 Mmux__n0021_I0_Result1 (
3894 
    .ADR0(VCC),
3895 
    .ADR1(VCC),
3896 
    .ADR2(Ker87891_1),
3897 
    .ADR3(tx_buf_reg_2[7]),
3898 
    .O(_n0021[7])
3899 
  );
3900 
  defparam Mmux__n0021_I2_Result1.INIT = 16'hF0CC;
3901 
  X_LUT4 Mmux__n0021_I2_Result1 (
3902 
    .ADR0(VCC),
3903 
    .ADR1(tx_shift_reg_2[6]),
3904 
    .ADR2(tx_buf_reg_2[5]),
3905 
    .ADR3(Ker87891_1),
3906 
    .O(_n0021[5])
3907 
  );
3908 
  defparam Mmux__n0021_I1_Result1.INIT = 16'hEE44;
3909 
  X_LUT4 Mmux__n0021_I1_Result1 (
3910 
    .ADR0(Ker87891_1),
3911 
    .ADR1(tx_shift_reg_2[7]),
3912 
    .ADR2(VCC),
3913 
    .ADR3(tx_buf_reg_2[6]),
3914 
    .O(_n0021[6])
3915 
  );
3916 
  defparam Mmux__n0022_I6_Result1.INIT = 16'hF3C0;
3917 
  X_LUT4 Mmux__n0022_I6_Result1 (
3918 
    .ADR0(VCC),
3919 
    .ADR1(Ker87891_1),
3920 
    .ADR2(tx_buf_reg_3[1]),
3921 
    .ADR3(tx_shift_reg_3[2]),
3922 
    .O(_n0022[1])
3923 
  );
3924 
  defparam Mmux__n0022_I5_Result1.INIT = 16'hE2E2;
3925 
  X_LUT4 Mmux__n0022_I5_Result1 (
3926 
    .ADR0(tx_shift_reg_3[3]),
3927 
    .ADR1(Ker87891_1),
3928 
    .ADR2(tx_buf_reg_3[2]),
3929 
    .ADR3(VCC),
3930 
    .O(_n0022[2])
3931 
  );
3932 
  defparam Mmux__n0022_I4_Result1.INIT = 16'hFC30;
3933 
  X_LUT4 Mmux__n0022_I4_Result1 (
3934 
    .ADR0(VCC),
3935 
    .ADR1(Ker87891_1),
3936 
    .ADR2(tx_shift_reg_3[4]),
3937 
    .ADR3(tx_buf_reg_3[3]),
3938 
    .O(_n0022[3])
3939 
  );
3940 
  defparam Mmux__n0022_I3_Result1.INIT = 16'hAFA0;
3941 
  X_LUT4 Mmux__n0022_I3_Result1 (
3942 
    .ADR0(tx_buf_reg_3[4]),
3943 
    .ADR1(VCC),
3944 
    .ADR2(Ker87891_1),
3945 
    .ADR3(tx_shift_reg_3[5]),
3946 
    .O(_n0022[4])
3947 
  );
3948 
  defparam Mmux__n0022_I2_Result1.INIT = 16'hFC0C;
3949 
  X_LUT4 Mmux__n0022_I2_Result1 (
3950 
    .ADR0(VCC),
3951 
    .ADR1(tx_shift_reg_3[6]),
3952 
    .ADR2(Ker87891_1),
3953 
    .ADR3(tx_buf_reg_3[5]),
3954 
    .O(_n0022[5])
3955 
  );
3956 
  defparam Mmux__n0022_I1_Result1.INIT = 16'hFA50;
3957 
  X_LUT4 Mmux__n0022_I1_Result1 (
3958 
    .ADR0(Ker87891_1),
3959 
    .ADR1(VCC),
3960 
    .ADR2(tx_shift_reg_3[7]),
3961 
    .ADR3(tx_buf_reg_3[6]),
3962 
    .O(_n0022[6])
3963 
  );
3964 
  defparam Mmux__n0023_I6_Result1.INIT = 16'hDD88;
3965 
  X_LUT4 Mmux__n0023_I6_Result1 (
3966 
    .ADR0(Ker87891_1),
3967 
    .ADR1(tx_buf_reg_4[1]),
3968 
    .ADR2(VCC),
3969 
    .ADR3(tx_shift_reg_4[2]),
3970 
    .O(_n0023[1])
3971 
  );
3972 
  defparam Mmux__n0023_I5_Result1.INIT = 16'hF0CC;
3973 
  X_LUT4 Mmux__n0023_I5_Result1 (
3974 
    .ADR0(VCC),
3975 
    .ADR1(tx_shift_reg_4[3]),
3976 
    .ADR2(tx_buf_reg_4[2]),
3977 
    .ADR3(Ker87891_1),
3978 
    .O(_n0023[2])
3979 
  );
3980 
  defparam Mmux__n0023_I4_Result1.INIT = 16'hF5A0;
3981 
  X_LUT4 Mmux__n0023_I4_Result1 (
3982 
    .ADR0(Ker87891_1),
3983 
    .ADR1(VCC),
3984 
    .ADR2(tx_buf_reg_4[3]),
3985 
    .ADR3(tx_shift_reg_4[4]),
3986 
    .O(_n0023[3])
3987 
  );
3988 
  defparam Mmux__n0023_I3_Result1.INIT = 16'hCACA;
3989 
  X_LUT4 Mmux__n0023_I3_Result1 (
3990 
    .ADR0(tx_shift_reg_4[5]),
3991 
    .ADR1(tx_buf_reg_4[4]),
3992 
    .ADR2(Ker87891_1),
3993 
    .ADR3(VCC),
3994 
    .O(_n0023[4])
3995 
  );
3996 
  defparam Mmux__n0022_I0_Result1.INIT = 16'hC0C0;
3997 
  X_LUT4 Mmux__n0022_I0_Result1 (
3998 
    .ADR0(VCC),
3999 
    .ADR1(Ker87891_1),
4000 
    .ADR2(tx_buf_reg_3[7]),
4001 
    .ADR3(VCC),
4002 
    .O(_n0022[7])
4003 
  );
4004 
  defparam Mmux__n0023_I0_Result1.INIT = 16'hA0A0;
4005 
  X_LUT4 Mmux__n0023_I0_Result1 (
4006 
    .ADR0(Ker87891_1),
4007 
    .ADR1(VCC),
4008 
    .ADR2(tx_buf_reg_4[7]),
4009 
    .ADR3(VCC),
4010 
    .O(_n0023[7])
4011 
  );
4012 
  defparam Mmux__n0023_I2_Result1.INIT = 16'hFC0C;
4013 
  X_LUT4 Mmux__n0023_I2_Result1 (
4014 
    .ADR0(VCC),
4015 
    .ADR1(tx_shift_reg_4[6]),
4016 
    .ADR2(Ker87891_1),
4017 
    .ADR3(tx_buf_reg_4[5]),
4018 
    .O(_n0023[5])
4019 
  );
4020 
  defparam Mmux__n0023_I1_Result1.INIT = 16'hCFC0;
4021 
  X_LUT4 Mmux__n0023_I1_Result1 (
4022 
    .ADR0(VCC),
4023 
    .ADR1(tx_buf_reg_4[6]),
4024 
    .ADR2(Ker87891_1),
4025 
    .ADR3(tx_shift_reg_4[7]),
4026 
    .O(_n0023[6])
4027 
  );
4028 
  defparam Mmux__n0024_I6_Result1.INIT = 16'hFA50;
4029 
  X_LUT4 Mmux__n0024_I6_Result1 (
4030 
    .ADR0(Ker87891_1),
4031 
    .ADR1(VCC),
4032 
    .ADR2(tx_shift_reg_5[2]),
4033 
    .ADR3(tx_buf_reg_5[1]),
4034 
    .O(_n0024[1])
4035 
  );
4036 
  defparam Mmux__n0024_I5_Result1.INIT = 16'hBB88;
4037 
  X_LUT4 Mmux__n0024_I5_Result1 (
4038 
    .ADR0(tx_buf_reg_5[2]),
4039 
    .ADR1(Ker87891_1),
4040 
    .ADR2(VCC),
4041 
    .ADR3(tx_shift_reg_5[3]),
4042 
    .O(_n0024[2])
4043 
  );
4044 
  defparam Mmux__n0024_I4_Result1.INIT = 16'hCCF0;
4045 
  X_LUT4 Mmux__n0024_I4_Result1 (
4046 
    .ADR0(VCC),
4047 
    .ADR1(tx_buf_reg_5[3]),
4048 
    .ADR2(tx_shift_reg_5[4]),
4049 
    .ADR3(Ker87891_1),
4050 
    .O(_n0024[3])
4051 
  );
4052 
  defparam Mmux__n0024_I3_Result1.INIT = 16'hE4E4;
4053 
  X_LUT4 Mmux__n0024_I3_Result1 (
4054 
    .ADR0(Ker87891_1),
4055 
    .ADR1(tx_shift_reg_5[5]),
4056 
    .ADR2(tx_buf_reg_5[4]),
4057 
    .ADR3(VCC),
4058 
    .O(_n0024[4])
4059 
  );
4060 
  defparam Mmux__n0024_I2_Result1.INIT = 16'hF5A0;
4061 
  X_LUT4 Mmux__n0024_I2_Result1 (
4062 
    .ADR0(Ker87891_1),
4063 
    .ADR1(VCC),
4064 
    .ADR2(tx_buf_reg_5[5]),
4065 
    .ADR3(tx_shift_reg_5[6]),
4066 
    .O(_n0024[5])
4067 
  );
4068 
  defparam Mmux__n0024_I1_Result1.INIT = 16'hBB88;
4069 
  X_LUT4 Mmux__n0024_I1_Result1 (
4070 
    .ADR0(tx_buf_reg_5[6]),
4071 
    .ADR1(Ker87891_1),
4072 
    .ADR2(VCC),
4073 
    .ADR3(tx_shift_reg_5[7]),
4074 
    .O(_n0024[6])
4075 
  );
4076 
  defparam Mmux__n0025_I6_Result1.INIT = 16'hCCF0;
4077 
  X_LUT4 Mmux__n0025_I6_Result1 (
4078 
    .ADR0(VCC),
4079 
    .ADR1(tx_buf_reg_6[1]),
4080 
    .ADR2(tx_shift_reg_6[2]),
4081 
    .ADR3(Ker87891_1),
4082 
    .O(_n0025[1])
4083 
  );
4084 
  defparam Mmux__n0025_I5_Result1.INIT = 16'hF3C0;
4085 
  X_LUT4 Mmux__n0025_I5_Result1 (
4086 
    .ADR0(VCC),
4087 
    .ADR1(Ker87891_1),
4088 
    .ADR2(tx_buf_reg_6[2]),
4089 
    .ADR3(tx_shift_reg_6[3]),
4090 
    .O(_n0025[2])
4091 
  );
4092 
  defparam Mmux__n0025_I4_Result1.INIT = 16'hFA50;
4093 
  X_LUT4 Mmux__n0025_I4_Result1 (
4094 
    .ADR0(Ker87891_1),
4095 
    .ADR1(VCC),
4096 
    .ADR2(tx_shift_reg_6[4]),
4097 
    .ADR3(tx_buf_reg_6[3]),
4098 
    .O(_n0025[3])
4099 
  );
4100 
  defparam Mmux__n0025_I3_Result1.INIT = 16'hF5A0;
4101 
  X_LUT4 Mmux__n0025_I3_Result1 (
4102 
    .ADR0(Ker87891_1),
4103 
    .ADR1(VCC),
4104 
    .ADR2(tx_buf_reg_6[4]),
4105 
    .ADR3(tx_shift_reg_6[5]),
4106 
    .O(_n0025[4])
4107 
  );
4108 
  X_BUF \tx_shift_reg_6<4>/FFX/RSTOR  (
4109 
    .I(GSR),
4110 
    .O(\tx_shift_reg_6<4>/FFX/RST )
4111 
  );
4112 
  X_FF tx_shift_reg_6_4 (
4113 
    .I(_n0025[4]),
4114 
    .CE(VCC),
4115 
    .CLK(div_reg_1),
4116 
    .SET(GND),
4117 
    .RST(\tx_shift_reg_6<4>/FFX/RST ),
4118 
    .O(tx_shift_reg_6[4])
4119 
  );
4120 
  X_BUF \tx_shift_reg_6<4>/FFY/RSTOR  (
4121 
    .I(GSR),
4122 
    .O(\tx_shift_reg_6<4>/FFY/RST )
4123 
  );
4124 
  X_FF tx_shift_reg_6_3 (
4125 
    .I(_n0025[3]),
4126 
    .CE(VCC),
4127 
    .CLK(div_reg_1),
4128 
    .SET(GND),
4129 
    .RST(\tx_shift_reg_6<4>/FFY/RST ),
4130 
    .O(tx_shift_reg_6[3])
4131 
  );
4132 
  defparam Mmux__n0024_I0_Result1.INIT = 16'hC0C0;
4133 
  X_LUT4 Mmux__n0024_I0_Result1 (
4134 
    .ADR0(VCC),
4135 
    .ADR1(Ker87891_1),
4136 
    .ADR2(tx_buf_reg_5[7]),
4137 
    .ADR3(VCC),
4138 
    .O(_n0024[7])
4139 
  );
4140 
  defparam Mmux__n0025_I0_Result1.INIT = 16'hAA00;
4141 
  X_LUT4 Mmux__n0025_I0_Result1 (
4142 
    .ADR0(tx_buf_reg_6[7]),
4143 
    .ADR1(VCC),
4144 
    .ADR2(VCC),
4145 
    .ADR3(Ker87891_1),
4146 
    .O(_n0025[7])
4147 
  );
4148 
  defparam Mmux__n0025_I2_Result1.INIT = 16'hFC30;
4149 
  X_LUT4 Mmux__n0025_I2_Result1 (
4150 
    .ADR0(VCC),
4151 
    .ADR1(Ker87891_1),
4152 
    .ADR2(tx_shift_reg_6[6]),
4153 
    .ADR3(tx_buf_reg_6[5]),
4154 
    .O(_n0025[5])
4155 
  );
4156 
  defparam Mmux__n0025_I1_Result1.INIT = 16'hAACC;
4157 
  X_LUT4 Mmux__n0025_I1_Result1 (
4158 
    .ADR0(tx_buf_reg_6[6]),
4159 
    .ADR1(tx_shift_reg_6[7]),
4160 
    .ADR2(VCC),
4161 
    .ADR3(Ker87891_1),
4162 
    .O(_n0025[6])
4163 
  );
4164 
  X_BUF \tx_shift_reg_6<6>/FFY/RSTOR  (
4165 
    .I(GSR),
4166 
    .O(\tx_shift_reg_6<6>/FFY/RST )
4167 
  );
4168 
  X_FF tx_shift_reg_6_5 (
4169 
    .I(_n0025[5]),
4170 
    .CE(VCC),
4171 
    .CLK(div_reg_1),
4172 
    .SET(GND),
4173 
    .RST(\tx_shift_reg_6<6>/FFY/RST ),
4174 
    .O(tx_shift_reg_6[5])
4175 
  );
4176 
  X_BUF \tx_shift_reg_6<6>/FFX/RSTOR  (
4177 
    .I(GSR),
4178 
    .O(\tx_shift_reg_6<6>/FFX/RST )
4179 
  );
4180 
  X_FF tx_shift_reg_6_6 (
4181 
    .I(_n0025[6]),
4182 
    .CE(VCC),
4183 
    .CLK(div_reg_1),
4184 
    .SET(GND),
4185 
    .RST(\tx_shift_reg_6<6>/FFX/RST ),
4186 
    .O(tx_shift_reg_6[6])
4187 
  );
4188 
  defparam Mmux__n0026_I6_Result1.INIT = 16'hACAC;
4189 
  X_LUT4 Mmux__n0026_I6_Result1 (
4190 
    .ADR0(tx_buf_reg_7[1]),
4191 
    .ADR1(tx_shift_reg_7[2]),
4192 
    .ADR2(Ker87891_1),
4193 
    .ADR3(VCC),
4194 
    .O(_n0026[1])
4195 
  );
4196 
  defparam Mmux__n0026_I5_Result1.INIT = 16'hFC0C;
4197 
  X_LUT4 Mmux__n0026_I5_Result1 (
4198 
    .ADR0(VCC),
4199 
    .ADR1(tx_shift_reg_7[3]),
4200 
    .ADR2(Ker87891_1),
4201 
    .ADR3(tx_buf_reg_7[2]),
4202 
    .O(_n0026[2])
4203 
  );
4204 
  defparam Mmux__n0026_I4_Result1.INIT = 16'hB8B8;
4205 
  X_LUT4 Mmux__n0026_I4_Result1 (
4206 
    .ADR0(tx_buf_reg_7[3]),
4207 
    .ADR1(Ker87891_1),
4208 
    .ADR2(tx_shift_reg_7[4]),
4209 
    .ADR3(VCC),
4210 
    .O(_n0026[3])
4211 
  );
4212 
  defparam Mmux__n0026_I3_Result1.INIT = 16'hFA50;
4213 
  X_LUT4 Mmux__n0026_I3_Result1 (
4214 
    .ADR0(Ker87891_1),
4215 
    .ADR1(VCC),
4216 
    .ADR2(tx_shift_reg_7[5]),
4217 
    .ADR3(tx_buf_reg_7[4]),
4218 
    .O(_n0026[4])
4219 
  );
4220 
  X_BUF \tx_shift_reg_7<4>/FFY/RSTOR  (
4221 
    .I(GSR),
4222 
    .O(\tx_shift_reg_7<4>/FFY/RST )
4223 
  );
4224 
  X_FF tx_shift_reg_7_3 (
4225 
    .I(_n0026[3]),
4226 
    .CE(VCC),
4227 
    .CLK(div_reg_1),
4228 
    .SET(GND),
4229 
    .RST(\tx_shift_reg_7<4>/FFY/RST ),
4230 
    .O(tx_shift_reg_7[3])
4231 
  );
4232 
  X_BUF \tx_shift_reg_7<4>/FFX/RSTOR  (
4233 
    .I(GSR),
4234 
    .O(\tx_shift_reg_7<4>/FFX/RST )
4235 
  );
4236 
  X_FF tx_shift_reg_7_4 (
4237 
    .I(_n0026[4]),
4238 
    .CE(VCC),
4239 
    .CLK(div_reg_1),
4240 
    .SET(GND),
4241 
    .RST(\tx_shift_reg_7<4>/FFX/RST ),
4242 
    .O(tx_shift_reg_7[4])
4243 
  );
4244 
  defparam Mmux__n0026_I2_Result1.INIT = 16'hAAF0;
4245 
  X_LUT4 Mmux__n0026_I2_Result1 (
4246 
    .ADR0(tx_buf_reg_7[5]),
4247 
    .ADR1(VCC),
4248 
    .ADR2(tx_shift_reg_7[6]),
4249 
    .ADR3(Ker87891_1),
4250 
    .O(_n0026[5])
4251 
  );
4252 
  defparam Mmux__n0026_I1_Result1.INIT = 16'hBB88;
4253 
  X_LUT4 Mmux__n0026_I1_Result1 (
4254 
    .ADR0(tx_buf_reg_7[6]),
4255 
    .ADR1(Ker87891_1),
4256 
    .ADR2(VCC),
4257 
    .ADR3(tx_shift_reg_7[7]),
4258 
    .O(_n0026[6])
4259 
  );
4260 
  X_BUF \tx_shift_reg_7<7>/XUSED  (
4261 
    .I(\tx_shift_reg_7<7>/FROM ),
4262 
    .O(Ker87891_1)
4263 
  );
4264 
  defparam Mmux__n0026_I0_Result1.INIT = 16'hF000;
4265 
  X_LUT4 Mmux__n0026_I0_Result1 (
4266 
    .ADR0(VCC),
4267 
    .ADR1(VCC),
4268 
    .ADR2(tx_buf_reg_7[7]),
4269 
    .ADR3(Ker87891_1),
4270 
    .O(_n0026[7])
4271 
  );
4272 
  defparam Ker87891_1_80.INIT = 16'h0008;
4273 
  X_LUT4 Ker87891_1_80 (
4274 
    .ADR0(frame_cnt_1_1),
4275 
    .ADR1(frame_cnt[3]),
4276 
    .ADR2(frame_cnt[2]),
4277 
    .ADR3(frame_cnt[0]),
4278 
    .O(\tx_shift_reg_7<7>/FROM )
4279 
  );
4280 
  defparam Mmux__n0046_I1_Result1.INIT = 16'hCCF0;
4281 
  X_LUT4 Mmux__n0046_I1_Result1 (
4282 
    .ADR0(VCC),
4283 
    .ADR1(ctrl_out_reg[0]),
4284 
    .ADR2(_n0246[2]),
4285 
    .ADR3(N8682),
4286 
    .O(_n0046[0])
4287 
  );
4288 
  defparam Mmux__n0051_I8_Result1.INIT = 16'hAEA2;
4289 
  X_LUT4 Mmux__n0051_I8_Result1 (
4290 
    .ADR0(ctrl_out_reg[0]),
4291 
    .ADR1(mpi_cs_IBUF),
4292 
    .ADR2(mpi_addr_8_IBUF),
4293 
    .ADR3(mpi_mem_bus_out[0]),
4294 
    .O(\ctrl_out_reg<0>/FROM )
4295 
  );
4296 
  X_BUF \ctrl_out_reg<1>/XUSED  (
4297 
    .I(\ctrl_out_reg<1>/FROM ),
4298 
    .O(N8682)
4299 
  );
4300 
  defparam Mmux__n0046_I0_Result1.INIT = 16'hF0AA;
4301 
  X_LUT4 Mmux__n0046_I0_Result1 (
4302 
    .ADR0(_n0246[3]),
4303 
    .ADR1(VCC),
4304 
    .ADR2(ctrl_out_reg[1]),
4305 
    .ADR3(N8682),
4306 
    .O(_n0046[1])
4307 
  );
4308 
  defparam Ker86801.INIT = 16'hCFFF;
4309 
  X_LUT4 Ker86801 (
4310 
    .ADR0(VCC),
4311 
    .ADR1(mpi_addr_3_IBUF),
4312 
    .ADR2(mpi_cs_IBUF),
4313 
    .ADR3(mpi_addr_8_IBUF),
4314 
    .O(\ctrl_out_reg<1>/FROM )
4315 
  );
4316 
  X_INV \frame_delay_cnt_0_0_0/CKINV  (
4317 
    .I(div_reg),
4318 
    .O(\frame_delay_cnt_0_0_0/CKMUXNOT )
4319 
  );
4320 
  X_BUF \frame_delay_cnt_0_0_0/XUSED  (
4321 
    .I(\frame_delay_cnt_0_0_0/FROM ),
4322 
    .O(frame_delay_cnt_0_0_0__n0000)
4323 
  );
4324 
  defparam frame_delay_cnt_0_Mmux__n0001_I1_Result1.INIT = 16'h03CF;
4325 
  X_LUT4 frame_delay_cnt_0_Mmux__n0001_I1_Result1 (
4326 
    .ADR0(VCC),
4327 
    .ADR1(N8791),
4328 
    .ADR2(frame_delay_cnt_0_0_0),
4329 
    .ADR3(frame_delay_buf_0[0]),
4330 
    .O(frame_delay_cnt_0__n0001[0])
4331 
  );
4332 
  defparam frame_delay_cnt_0_0__n00001.INIT = 16'hCC00;
4333 
  X_LUT4 frame_delay_cnt_0_0__n00001 (
4334 
    .ADR0(VCC),
4335 
    .ADR1(N8791),
4336 
    .ADR2(VCC),
4337 
    .ADR3(frame_delay_buf_0[0]),
4338 
    .O(\frame_delay_cnt_0_0_0/FROM )
4339 
  );
4340 
  X_INV \frame_delay_cnt_0_1_0/CKINV  (
4341 
    .I(div_reg),
4342 
    .O(\frame_delay_cnt_0_1_0/CKMUXNOT )
4343 
  );
4344 
  X_BUF \frame_delay_cnt_0_1_0/XUSED  (
4345 
    .I(\frame_delay_cnt_0_1_0/FROM ),
4346 
    .O(N8676)
4347 
  );
4348 
  defparam frame_delay_cnt_0_Mmux__n0001_I0_Result1.INIT = 16'hED21;
4349 
  X_LUT4 frame_delay_cnt_0_Mmux__n0001_I0_Result1 (
4350 
    .ADR0(frame_delay_cnt_0_1_0),
4351 
    .ADR1(N8791),
4352 
    .ADR2(frame_delay_cnt_0_0_0),
4353 
    .ADR3(N8676),
4354 
    .O(frame_delay_cnt_0__n0001[1])
4355 
  );
4356 
  defparam Ker86741.INIT = 16'h0FF0;
4357 
  X_LUT4 Ker86741 (
4358 
    .ADR0(VCC),
4359 
    .ADR1(VCC),
4360 
    .ADR2(frame_delay_buf_0[1]),
4361 
    .ADR3(frame_delay_buf_0[0]),
4362 
    .O(\frame_delay_cnt_0_1_0/FROM )
4363 
  );
4364 
  X_INV \frame_delay_cnt_1_0_0/CKINV  (
4365 
    .I(div_reg),
4366 
    .O(\frame_delay_cnt_1_0_0/CKMUXNOT )
4367 
  );
4368 
  X_BUF \frame_delay_cnt_1_0_0/XUSED  (
4369 
    .I(\frame_delay_cnt_1_0_0/FROM ),
4370 
    .O(frame_delay_cnt_1_0_0__n0000)
4371 
  );
4372 
  defparam frame_delay_cnt_1_Mmux__n0001_I1_Result1.INIT = 16'h2277;
4373 
  X_LUT4 frame_delay_cnt_1_Mmux__n0001_I1_Result1 (
4374 
    .ADR0(N8791),
4375 
    .ADR1(frame_delay_buf_1[0]),
4376 
    .ADR2(VCC),
4377 
    .ADR3(frame_delay_cnt_1_0_0),
4378 
    .O(frame_delay_cnt_1__n0001[0])
4379 
  );
4380 
  defparam frame_delay_cnt_1_0__n00001.INIT = 16'h8888;
4381 
  X_LUT4 frame_delay_cnt_1_0__n00001 (
4382 
    .ADR0(N8791),
4383 
    .ADR1(frame_delay_buf_1[0]),
4384 
    .ADR2(VCC),
4385 
    .ADR3(VCC),
4386 
    .O(\frame_delay_cnt_1_0_0/FROM )
4387 
  );
4388 
  X_INV \frame_delay_cnt_1_1_0/CKINV  (
4389 
    .I(div_reg),
4390 
    .O(\frame_delay_cnt_1_1_0/CKMUXNOT )
4391 
  );
4392 
  X_BUF \frame_delay_cnt_1_1_0/XUSED  (
4393 
    .I(\frame_delay_cnt_1_1_0/FROM ),
4394 
    .O(N8670)
4395 
  );
4396 
  defparam frame_delay_cnt_1_Mmux__n0001_I0_Result1.INIT = 16'hF909;
4397 
  X_LUT4 frame_delay_cnt_1_Mmux__n0001_I0_Result1 (
4398 
    .ADR0(frame_delay_cnt_1_1_0),
4399 
    .ADR1(frame_delay_cnt_1_0_0),
4400 
    .ADR2(N8791),
4401 
    .ADR3(N8670),
4402 
    .O(frame_delay_cnt_1__n0001[1])
4403 
  );
4404 
  defparam Ker86681.INIT = 16'h5A5A;
4405 
  X_LUT4 Ker86681 (
4406 
    .ADR0(frame_delay_buf_1[0]),
4407 
    .ADR1(VCC),
4408 
    .ADR2(frame_delay_buf_1[1]),
4409 
    .ADR3(VCC),
4410 
    .O(\frame_delay_cnt_1_1_0/FROM )
4411 
  );
4412 
  X_INV \frame_delay_cnt_2_0_0/CKINV  (
4413 
    .I(div_reg),
4414 
    .O(\frame_delay_cnt_2_0_0/CKMUXNOT )
4415 
  );
4416 
  X_BUF \frame_delay_cnt_2_0_0/XUSED  (
4417 
    .I(\frame_delay_cnt_2_0_0/FROM ),
4418 
    .O(frame_delay_cnt_2_0_0__n0000)
4419 
  );
4420 
  defparam frame_delay_cnt_2_Mmux__n0001_I1_Result1.INIT = 16'h0A5F;
4421 
  X_LUT4 frame_delay_cnt_2_Mmux__n0001_I1_Result1 (
4422 
    .ADR0(N8791),
4423 
    .ADR1(VCC),
4424 
    .ADR2(frame_delay_buf_2[0]),
4425 
    .ADR3(frame_delay_cnt_2_0_0),
4426 
    .O(frame_delay_cnt_2__n0001[0])
4427 
  );
4428 
  defparam frame_delay_cnt_2_0__n00001.INIT = 16'hA0A0;
4429 
  X_LUT4 frame_delay_cnt_2_0__n00001 (
4430 
    .ADR0(N8791),
4431 
    .ADR1(VCC),
4432 
    .ADR2(frame_delay_buf_2[0]),
4433 
    .ADR3(VCC),
4434 
    .O(\frame_delay_cnt_2_0_0/FROM )
4435 
  );
4436 
  X_INV \frame_delay_cnt_2_1_0/CKINV  (
4437 
    .I(div_reg),
4438 
    .O(\frame_delay_cnt_2_1_0/CKMUXNOT )
4439 
  );
4440 
  X_BUF \frame_delay_cnt_2_1_0/XUSED  (
4441 
    .I(\frame_delay_cnt_2_1_0/FROM ),
4442 
    .O(N8664)
4443 
  );
4444 
  defparam frame_delay_cnt_2_Mmux__n0001_I0_Result1.INIT = 16'hED21;
4445 
  X_LUT4 frame_delay_cnt_2_Mmux__n0001_I0_Result1 (
4446 
    .ADR0(frame_delay_cnt_2_1_0),
4447 
    .ADR1(N8791),
4448 
    .ADR2(frame_delay_cnt_2_0_0),
4449 
    .ADR3(N8664),
4450 
    .O(frame_delay_cnt_2__n0001[1])
4451 
  );
4452 
  defparam Ker86621.INIT = 16'h6666;
4453 
  X_LUT4 Ker86621 (
4454 
    .ADR0(frame_delay_buf_2[1]),
4455 
    .ADR1(frame_delay_buf_2[0]),
4456 
    .ADR2(VCC),
4457 
    .ADR3(VCC),
4458 
    .O(\frame_delay_cnt_2_1_0/FROM )
4459 
  );
4460 
  X_INV \frame_delay_cnt_3_0_0/CKINV  (
4461 
    .I(div_reg),
4462 
    .O(\frame_delay_cnt_3_0_0/CKMUXNOT )
4463 
  );
4464 
  X_BUF \frame_delay_cnt_3_0_0/XUSED  (
4465 
    .I(\frame_delay_cnt_3_0_0/FROM ),
4466 
    .O(frame_delay_cnt_3_0_0__n0000)
4467 
  );
4468 
  defparam frame_delay_cnt_3_Mmux__n0001_I1_Result1.INIT = 16'h303F;
4469 
  X_LUT4 frame_delay_cnt_3_Mmux__n0001_I1_Result1 (
4470 
    .ADR0(VCC),
4471 
    .ADR1(frame_delay_buf_3[0]),
4472 
    .ADR2(N8791),
4473 
    .ADR3(frame_delay_cnt_3_0_0),
4474 
    .O(frame_delay_cnt_3__n0001[0])
4475 
  );
4476 
  defparam frame_delay_cnt_3_0__n00001.INIT = 16'hC0C0;
4477 
  X_LUT4 frame_delay_cnt_3_0__n00001 (
4478 
    .ADR0(VCC),
4479 
    .ADR1(frame_delay_buf_3[0]),
4480 
    .ADR2(N8791),
4481 
    .ADR3(VCC),
4482 
    .O(\frame_delay_cnt_3_0_0/FROM )
4483 
  );
4484 
  X_INV \frame_delay_cnt_3_1_0/CKINV  (
4485 
    .I(div_reg),
4486 
    .O(\frame_delay_cnt_3_1_0/CKMUXNOT )
4487 
  );
4488 
  X_BUF \frame_delay_cnt_3_1_0/XUSED  (
4489 
    .I(\frame_delay_cnt_3_1_0/FROM ),
4490 
    .O(N8658)
4491 
  );
4492 
  defparam frame_delay_cnt_3_Mmux__n0001_I0_Result1.INIT = 16'hEB41;
4493 
  X_LUT4 frame_delay_cnt_3_Mmux__n0001_I0_Result1 (
4494 
    .ADR0(N8791),
4495 
    .ADR1(frame_delay_cnt_3_1_0),
4496 
    .ADR2(frame_delay_cnt_3_0_0),
4497 
    .ADR3(N8658),
4498 
    .O(frame_delay_cnt_3__n0001[1])
4499 
  );
4500 
  defparam Ker86561.INIT = 16'h0FF0;
4501 
  X_LUT4 Ker86561 (
4502 
    .ADR0(VCC),
4503 
    .ADR1(VCC),
4504 
    .ADR2(frame_delay_buf_3[0]),
4505 
    .ADR3(frame_delay_buf_3[1]),
4506 
    .O(\frame_delay_cnt_3_1_0/FROM )
4507 
  );
4508 
  X_INV \frame_delay_cnt_4_0_0/CKINV  (
4509 
    .I(div_reg),
4510 
    .O(\frame_delay_cnt_4_0_0/CKMUXNOT )
4511 
  );
4512 
  X_BUF \frame_delay_cnt_4_0_0/XUSED  (
4513 
    .I(\frame_delay_cnt_4_0_0/FROM ),
4514 
    .O(frame_delay_cnt_4_0_0__n0000)
4515 
  );
4516 
  defparam frame_delay_cnt_4_Mmux__n0001_I1_Result1.INIT = 16'h5353;
4517 
  X_LUT4 frame_delay_cnt_4_Mmux__n0001_I1_Result1 (
4518 
    .ADR0(frame_delay_buf_4[0]),
4519 
    .ADR1(frame_delay_cnt_4_0_0),
4520 
    .ADR2(N8791),
4521 
    .ADR3(VCC),
4522 
    .O(frame_delay_cnt_4__n0001[0])
4523 
  );
4524 
  defparam frame_delay_cnt_4_0__n00001.INIT = 16'hF000;
4525 
  X_LUT4 frame_delay_cnt_4_0__n00001 (
4526 
    .ADR0(VCC),
4527 
    .ADR1(VCC),
4528 
    .ADR2(N8791),
4529 
    .ADR3(frame_delay_buf_4[0]),
4530 
    .O(\frame_delay_cnt_4_0_0/FROM )
4531 
  );
4532 
  X_INV \frame_delay_cnt_4_1_0/CKINV  (
4533 
    .I(div_reg),
4534 
    .O(\frame_delay_cnt_4_1_0/CKMUXNOT )
4535 
  );
4536 
  X_BUF \frame_delay_cnt_4_1_0/XUSED  (
4537 
    .I(\frame_delay_cnt_4_1_0/FROM ),
4538 
    .O(N8652)
4539 
  );
4540 
  defparam frame_delay_cnt_4_Mmux__n0001_I0_Result1.INIT = 16'hEB41;
4541 
  X_LUT4 frame_delay_cnt_4_Mmux__n0001_I0_Result1 (
4542 
    .ADR0(N8791),
4543 
    .ADR1(frame_delay_cnt_4_1_0),
4544 
    .ADR2(frame_delay_cnt_4_0_0),
4545 
    .ADR3(N8652),
4546 
    .O(frame_delay_cnt_4__n0001[1])
4547 
  );
4548 
  defparam Ker86501.INIT = 16'h33CC;
4549 
  X_LUT4 Ker86501 (
4550 
    .ADR0(VCC),
4551 
    .ADR1(frame_delay_buf_4[0]),
4552 
    .ADR2(VCC),
4553 
    .ADR3(frame_delay_buf_4[1]),
4554 
    .O(\frame_delay_cnt_4_1_0/FROM )
4555 
  );
4556 
  X_INV \frame_delay_cnt_5_0_0/CKINV  (
4557 
    .I(div_reg),
4558 
    .O(\frame_delay_cnt_5_0_0/CKMUXNOT )
4559 
  );
4560 
  X_BUF \frame_delay_cnt_5_0_0/XUSED  (
4561 
    .I(\frame_delay_cnt_5_0_0/FROM ),
4562 
    .O(frame_delay_cnt_5_0_0__n0000)
4563 
  );
4564 
  defparam frame_delay_cnt_5_Mmux__n0001_I1_Result1.INIT = 16'h0C3F;
4565 
  X_LUT4 frame_delay_cnt_5_Mmux__n0001_I1_Result1 (
4566 
    .ADR0(VCC),
4567 
    .ADR1(N8791),
4568 
    .ADR2(frame_delay_buf_5[0]),
4569 
    .ADR3(frame_delay_cnt_5_0_0),
4570 
    .O(frame_delay_cnt_5__n0001[0])
4571 
  );
4572 
  defparam frame_delay_cnt_5_0__n00001.INIT = 16'hCC00;
4573 
  X_LUT4 frame_delay_cnt_5_0__n00001 (
4574 
    .ADR0(VCC),
4575 
    .ADR1(frame_delay_buf_5[0]),
4576 
    .ADR2(VCC),
4577 
    .ADR3(N8791),
4578 
    .O(\frame_delay_cnt_5_0_0/FROM )
4579 
  );
4580 
  X_INV \frame_delay_cnt_5_1_0/CKINV  (
4581 
    .I(div_reg),
4582 
    .O(\frame_delay_cnt_5_1_0/CKMUXNOT )
4583 
  );
4584 
  X_BUF \frame_delay_cnt_5_1_0/XUSED  (
4585 
    .I(\frame_delay_cnt_5_1_0/FROM ),
4586 
    .O(N8646)
4587 
  );
4588 
  defparam frame_delay_cnt_5_Mmux__n0001_I0_Result1.INIT = 16'hEB41;
4589 
  X_LUT4 frame_delay_cnt_5_Mmux__n0001_I0_Result1 (
4590 
    .ADR0(N8791),
4591 
    .ADR1(frame_delay_cnt_5_0_0),
4592 
    .ADR2(frame_delay_cnt_5_1_0),
4593 
    .ADR3(N8646),
4594 
    .O(frame_delay_cnt_5__n0001[1])
4595 
  );
4596 
  defparam Ker86441.INIT = 16'h0FF0;
4597 
  X_LUT4 Ker86441 (
4598 
    .ADR0(VCC),
4599 
    .ADR1(VCC),
4600 
    .ADR2(frame_delay_buf_5[1]),
4601 
    .ADR3(frame_delay_buf_5[0]),
4602 
    .O(\frame_delay_cnt_5_1_0/FROM )
4603 
  );
4604 
  X_OR2 \frame_delay_cnt_5_1_0/FFY/RSTOR  (
4605 
    .I0(frame_delay_cnt_5_0_1__n0000),
4606 
    .I1(GSR),
4607 
    .O(\frame_delay_cnt_5_1_0/FFY/RST )
4608 
  );
4609 
  X_BUF \frame_delay_cnt_5_1_0/FFY/SETOR  (
4610 
    .I(\frame_delay_cnt_5_0_1__n0001/FROM ),
4611 
    .O(\frame_delay_cnt_5_1_0/FFY/SET )
4612 
  );
4613 
  X_FF frame_delay_cnt_5_1_0_81 (
4614 
    .I(frame_delay_cnt_5__n0001[1]),
4615 
    .CE(_n0231),
4616 
    .CLK(\frame_delay_cnt_5_1_0/CKMUXNOT ),
4617 
    .SET(\frame_delay_cnt_5_1_0/FFY/SET ),
4618 
    .RST(\frame_delay_cnt_5_1_0/FFY/RST ),
4619 
    .O(frame_delay_cnt_5_1_0)
4620 
  );
4621 
  X_INV \mem_page_sel/SRMUX  (
4622 
    .I(reset_IBUF),
4623 
    .O(\mem_page_sel/SRMUX_OUTPUTNOT )
4624 
  );
4625 
  X_BUF \mem_page_sel/YUSED  (
4626 
    .I(\mem_page_sel/GROM ),
4627 
    .O(cd_mem_addr[8])
4628 
  );
4629 
  X_BUF \mem_page_sel/XUSED  (
4630 
    .I(\mem_page_sel/FROM ),
4631 
    .O(GLOBAL_LOGIC0_0)
4632 
  );
4633 
  defparam _n02341.INIT = 16'h00FF;
4634 
  X_LUT4 _n02341 (
4635 
    .ADR0(VCC),
4636 
    .ADR1(VCC),
4637 
    .ADR2(VCC),
4638 
    .ADR3(mem_page_sel),
4639 
    .O(\mem_page_sel/GROM )
4640 
  );
4641 
  defparam \mem_page_sel/F .INIT = 16'h0000;
4642 
  X_LUT4 \mem_page_sel/F  (
4643 
    .ADR0(VCC),
4644 
    .ADR1(VCC),
4645 
    .ADR2(VCC),
4646 
    .ADR3(VCC),
4647 
    .O(\mem_page_sel/FROM )
4648 
  );
4649 
  X_INV \frame_delay_cnt_6_0_0/CKINV  (
4650 
    .I(div_reg),
4651 
    .O(\frame_delay_cnt_6_0_0/CKMUXNOT )
4652 
  );
4653 
  X_BUF \frame_delay_cnt_6_0_0/XUSED  (
4654 
    .I(\frame_delay_cnt_6_0_0/FROM ),
4655 
    .O(frame_delay_cnt_6_0_0__n0000)
4656 
  );
4657 
  defparam frame_delay_cnt_6_Mmux__n0001_I1_Result1.INIT = 16'h505F;
4658 
  X_LUT4 frame_delay_cnt_6_Mmux__n0001_I1_Result1 (
4659 
    .ADR0(frame_delay_buf_6[0]),
4660 
    .ADR1(VCC),
4661 
    .ADR2(N8791),
4662 
    .ADR3(frame_delay_cnt_6_0_0),
4663 
    .O(frame_delay_cnt_6__n0001[0])
4664 
  );
4665 
  defparam frame_delay_cnt_6_0__n00001.INIT = 16'hA0A0;
4666 
  X_LUT4 frame_delay_cnt_6_0__n00001 (
4667 
    .ADR0(frame_delay_buf_6[0]),
4668 
    .ADR1(VCC),
4669 
    .ADR2(N8791),
4670 
    .ADR3(VCC),
4671 
    .O(\frame_delay_cnt_6_0_0/FROM )
4672 
  );
4673 
  X_INV \frame_delay_cnt_6_1_0/CKINV  (
4674 
    .I(div_reg),
4675 
    .O(\frame_delay_cnt_6_1_0/CKMUXNOT )
4676 
  );
4677 
  X_BUF \frame_delay_cnt_6_1_0/XUSED  (
4678 
    .I(\frame_delay_cnt_6_1_0/FROM ),
4679 
    .O(N8640)
4680 
  );
4681 
  defparam frame_delay_cnt_6_Mmux__n0001_I0_Result1.INIT = 16'hF909;
4682 
  X_LUT4 frame_delay_cnt_6_Mmux__n0001_I0_Result1 (
4683 
    .ADR0(frame_delay_cnt_6_0_0),
4684 
    .ADR1(frame_delay_cnt_6_1_0),
4685 
    .ADR2(N8791),
4686 
    .ADR3(N8640),
4687 
    .O(frame_delay_cnt_6__n0001[1])
4688 
  );
4689 
  defparam Ker86381.INIT = 16'h55AA;
4690 
  X_LUT4 Ker86381 (
4691 
    .ADR0(frame_delay_buf_6[1]),
4692 
    .ADR1(VCC),
4693 
    .ADR2(VCC),
4694 
    .ADR3(frame_delay_buf_6[0]),
4695 
    .O(\frame_delay_cnt_6_1_0/FROM )
4696 
  );
4697 
  X_OR2 \frame_delay_cnt_6_1_0/FFY/RSTOR  (
4698 
    .I0(frame_delay_cnt_6_0_1__n0000),
4699 
    .I1(GSR),
4700 
    .O(\frame_delay_cnt_6_1_0/FFY/RST )
4701 
  );
4702 
  X_BUF \frame_delay_cnt_6_1_0/FFY/SETOR  (
4703 
    .I(\frame_delay_cnt_7_0_1__n0001/GROM ),
4704 
    .O(\frame_delay_cnt_6_1_0/FFY/SET )
4705 
  );
4706 
  X_FF frame_delay_cnt_6_1_0_82 (
4707 
    .I(frame_delay_cnt_6__n0001[1]),
4708 
    .CE(_n0232),
4709 
    .CLK(\frame_delay_cnt_6_1_0/CKMUXNOT ),
4710 
    .SET(\frame_delay_cnt_6_1_0/FFY/SET ),
4711 
    .RST(\frame_delay_cnt_6_1_0/FFY/RST ),
4712 
    .O(frame_delay_cnt_6_1_0)
4713 
  );
4714 
  X_INV \frame_delay_cnt_7_0_0/CKINV  (
4715 
    .I(div_reg),
4716 
    .O(\frame_delay_cnt_7_0_0/CKMUXNOT )
4717 
  );
4718 
  X_BUF \frame_delay_cnt_7_0_0/XUSED  (
4719 
    .I(\frame_delay_cnt_7_0_0/FROM ),
4720 
    .O(frame_delay_cnt_7_0_0__n0000)
4721 
  );
4722 
  defparam frame_delay_cnt_7_Mmux__n0001_I1_Result1.INIT = 16'h03CF;
4723 
  X_LUT4 frame_delay_cnt_7_Mmux__n0001_I1_Result1 (
4724 
    .ADR0(VCC),
4725 
    .ADR1(N8791),
4726 
    .ADR2(frame_delay_cnt_7_0_0),
4727 
    .ADR3(frame_delay_buf_7[0]),
4728 
    .O(frame_delay_cnt_7__n0001[0])
4729 
  );
4730 
  defparam frame_delay_cnt_7_0__n00001.INIT = 16'hCC00;
4731 
  X_LUT4 frame_delay_cnt_7_0__n00001 (
4732 
    .ADR0(VCC),
4733 
    .ADR1(N8791),
4734 
    .ADR2(VCC),
4735 
    .ADR3(frame_delay_buf_7[0]),
4736 
    .O(\frame_delay_cnt_7_0_0/FROM )
4737 
  );
4738 
  X_INV \frame_delay_cnt_7_1_0/CKINV  (
4739 
    .I(div_reg),
4740 
    .O(\frame_delay_cnt_7_1_0/CKMUXNOT )
4741 
  );
4742 
  X_BUF \frame_delay_cnt_7_1_0/XUSED  (
4743 
    .I(\frame_delay_cnt_7_1_0/FROM ),
4744 
    .O(N8634)
4745 
  );
4746 
  defparam frame_delay_cnt_7_Mmux__n0001_I0_Result1.INIT = 16'hEB41;
4747 
  X_LUT4 frame_delay_cnt_7_Mmux__n0001_I0_Result1 (
4748 
    .ADR0(N8791),
4749 
    .ADR1(frame_delay_cnt_7_0_0),
4750 
    .ADR2(frame_delay_cnt_7_1_0),
4751 
    .ADR3(N8634),
4752 
    .O(frame_delay_cnt_7__n0001[1])
4753 
  );
4754 
  defparam Ker86321.INIT = 16'h5A5A;
4755 
  X_LUT4 Ker86321 (
4756 
    .ADR0(frame_delay_buf_7[0]),
4757 
    .ADR1(VCC),
4758 
    .ADR2(frame_delay_buf_7[1]),
4759 
    .ADR3(VCC),
4760 
    .O(\frame_delay_cnt_7_1_0/FROM )
4761 
  );
4762 
  X_BUF \N8954/YUSED  (
4763 
    .I(\N8954/GROM ),
4764 
    .O(frame_sync_OBUF)
4765 
  );
4766 
  X_BUF \N8954/XUSED  (
4767 
    .I(\N8954/FROM ),
4768 
    .O(N8954)
4769 
  );
4770 
  defparam Ker8737.INIT = 16'h0100;
4771 
  X_LUT4 Ker8737 (
4772 
    .ADR0(frame_cnt[8]),
4773 
    .ADR1(frame_cnt[6]),
4774 
    .ADR2(frame_cnt[7]),
4775 
    .ADR3(N8954),
4776 
    .O(\N8954/GROM )
4777 
  );
4778 
  defparam Ker8737_SW0.INIT = 16'h1100;
4779 
  X_LUT4 Ker8737_SW0 (
4780 
    .ADR0(frame_cnt[4]),
4781 
    .ADR1(frame_cnt[5]),
4782 
    .ADR2(VCC),
4783 
    .ADR3(N8791),
4784 
    .O(\N8954/FROM )
4785 
  );
4786 
  X_BUF \N8728/YUSED  (
4787 
    .I(\N8728/GROM ),
4788 
    .O(_n0038)
4789 
  );
4790 
  X_BUF \N8728/XUSED  (
4791 
    .I(\N8728/FROM ),
4792 
    .O(N8728)
4793 
  );
4794 
  defparam _n00381.INIT = 16'h0100;
4795 
  X_LUT4 _n00381 (
4796 
    .ADR0(mpi_addr_2_IBUF),
4797 
    .ADR1(mpi_addr_1_IBUF),
4798 
    .ADR2(mpi_addr_0_IBUF),
4799 
    .ADR3(N8728),
4800 
    .O(\N8728/GROM )
4801 
  );
4802 
  defparam Ker87261.INIT = 16'h0400;
4803 
  X_LUT4 Ker87261 (
4804 
    .ADR0(mpi_rw_IBUF),
4805 
    .ADR1(mpi_cs_IBUF),
4806 
    .ADR2(mpi_addr_3_IBUF),
4807 
    .ADR3(mpi_addr_8_IBUF),
4808 
    .O(\N8728/FROM )
4809 
  );
4810 
  X_BUF \_n0028/YUSED  (
4811 
    .I(\_n0028/GROM ),
4812 
    .O(_n0030)
4813 
  );
4814 
  X_BUF \_n0028/XUSED  (
4815 
    .I(\_n0028/FROM ),
4816 
    .O(_n0028)
4817 
  );
4818 
  defparam _n00301.INIT = 16'h0020;
4819 
  X_LUT4 _n00301 (
4820 
    .ADR0(frame_cnt[2]),
4821 
    .ADR1(frame_cnt[3]),
4822 
    .ADR2(frame_cnt[0]),
4823 
    .ADR3(frame_cnt[1]),
4824 
    .O(\_n0028/GROM )
4825 
  );
4826 
  defparam _n00281.INIT = 16'h0400;
4827 
  X_LUT4 _n00281 (
4828 
    .ADR0(frame_cnt[2]),
4829 
    .ADR1(frame_cnt[0]),
4830 
    .ADR2(frame_cnt[3]),
4831 
    .ADR3(frame_cnt[1]),
4832 
    .O(\_n0028/FROM )
4833 
  );
4834 
  X_BUF \_n0039/YUSED  (
4835 
    .I(\_n0039/GROM ),
4836 
    .O(_n0040)
4837 
  );
4838 
  X_BUF \_n0039/XUSED  (
4839 
    .I(\_n0039/FROM ),
4840 
    .O(_n0039)
4841 
  );
4842 
  defparam _n00401.INIT = 16'h0008;
4843 
  X_LUT4 _n00401 (
4844 
    .ADR0(mpi_addr_1_IBUF),
4845 
    .ADR1(N8728),
4846 
    .ADR2(mpi_addr_0_IBUF),
4847 
    .ADR3(mpi_addr_2_IBUF),
4848 
    .O(\_n0039/GROM )
4849 
  );
4850 
  defparam _n00391.INIT = 16'h0200;
4851 
  X_LUT4 _n00391 (
4852 
    .ADR0(mpi_addr_0_IBUF),
4853 
    .ADR1(mpi_addr_1_IBUF),
4854 
    .ADR2(mpi_addr_2_IBUF),
4855 
    .ADR3(N8728),
4856 
    .O(\_n0039/FROM )
4857 
  );
4858 
  X_BUF \_n0029/YUSED  (
4859 
    .I(\_n0029/GROM ),
4860 
    .O(_n0033)
4861 
  );
4862 
  X_BUF \_n0029/XUSED  (
4863 
    .I(\_n0029/FROM ),
4864 
    .O(_n0029)
4865 
  );
4866 
  defparam _n00331.INIT = 16'h0010;
4867 
  X_LUT4 _n00331 (
4868 
    .ADR0(frame_cnt[1]),
4869 
    .ADR1(frame_cnt[0]),
4870 
    .ADR2(frame_cnt[3]),
4871 
    .ADR3(frame_cnt[2]),
4872 
    .O(\_n0029/GROM )
4873 
  );
4874 
  defparam _n00291.INIT = 16'h0100;
4875 
  X_LUT4 _n00291 (
4876 
    .ADR0(frame_cnt[1]),
4877 
    .ADR1(frame_cnt[0]),
4878 
    .ADR2(frame_cnt[3]),
4879 
    .ADR3(frame_cnt[2]),
4880 
    .O(\_n0029/FROM )
4881 
  );
4882 
  X_BUF \_n0042/YUSED  (
4883 
    .I(\_n0042/GROM ),
4884 
    .O(_n0041)
4885 
  );
4886 
  X_BUF \_n0042/XUSED  (
4887 
    .I(\_n0042/FROM ),
4888 
    .O(_n0042)
4889 
  );
4890 
  defparam _n00411.INIT = 16'h4000;
4891 
  X_LUT4 _n00411 (
4892 
    .ADR0(mpi_addr_2_IBUF),
4893 
    .ADR1(mpi_addr_1_IBUF),
4894 
    .ADR2(N8728),
4895 
    .ADR3(mpi_addr_0_IBUF),
4896 
    .O(\_n0042/GROM )
4897 
  );
4898 
  defparam _n00421.INIT = 16'h0008;
4899 
  X_LUT4 _n00421 (
4900 
    .ADR0(mpi_addr_2_IBUF),
4901 
    .ADR1(N8728),
4902 
    .ADR2(mpi_addr_0_IBUF),
4903 
    .ADR3(mpi_addr_1_IBUF),
4904 
    .O(\_n0042/FROM )
4905 
  );
4906 
  X_BUF \_n0027/YUSED  (
4907 
    .I(\_n0027/GROM ),
4908 
    .O(_n0034)
4909 
  );
4910 
  X_BUF \_n0027/XUSED  (
4911 
    .I(\_n0027/FROM ),
4912 
    .O(_n0027)
4913 
  );
4914 
  defparam _n00341.INIT = 16'h0200;
4915 
  X_LUT4 _n00341 (
4916 
    .ADR0(frame_cnt[0]),
4917 
    .ADR1(frame_cnt[1]),
4918 
    .ADR2(frame_cnt[2]),
4919 
    .ADR3(frame_cnt[3]),
4920 
    .O(\_n0027/GROM )
4921 
  );
4922 
  defparam _n00271.INIT = 16'h0002;
4923 
  X_LUT4 _n00271 (
4924 
    .ADR0(frame_cnt[1]),
4925 
    .ADR1(frame_cnt[0]),
4926 
    .ADR2(frame_cnt[2]),
4927 
    .ADR3(frame_cnt[3]),
4928 
    .O(\_n0027/FROM )
4929 
  );
4930 
  X_BUF \_n0044/YUSED  (
4931 
    .I(\_n0044/GROM ),
4932 
    .O(_n0043)
4933 
  );
4934 
  X_BUF \_n0044/XUSED  (
4935 
    .I(\_n0044/FROM ),
4936 
    .O(_n0044)
4937 
  );
4938 
  defparam _n00431.INIT = 16'h0800;
4939 
  X_LUT4 _n00431 (
4940 
    .ADR0(mpi_addr_2_IBUF),
4941 
    .ADR1(N8728),
4942 
    .ADR2(mpi_addr_1_IBUF),
4943 
    .ADR3(mpi_addr_0_IBUF),
4944 
    .O(\_n0044/GROM )
4945 
  );
4946 
  defparam _n00441.INIT = 16'h0080;
4947 
  X_LUT4 _n00441 (
4948 
    .ADR0(N8728),
4949 
    .ADR1(mpi_addr_2_IBUF),
4950 
    .ADR2(mpi_addr_1_IBUF),
4951 
    .ADR3(mpi_addr_0_IBUF),
4952 
    .O(\_n0044/FROM )
4953 
  );
4954 
  X_BUF \_n0045/YUSED  (
4955 
    .I(\_n0045/GROM ),
4956 
    .O(_n0045)
4957 
  );
4958 
  defparam _n00451.INIT = 16'h8000;
4959 
  X_LUT4 _n00451 (
4960 
    .ADR0(N8728),
4961 
    .ADR1(mpi_addr_0_IBUF),
4962 
    .ADR2(mpi_addr_1_IBUF),
4963 
    .ADR3(mpi_addr_2_IBUF),
4964 
    .O(\_n0045/GROM )
4965 
  );
4966 
  X_BUF \_COND_1<2>/YUSED  (
4967 
    .I(\_COND_1<2>/GROM ),
4968 
    .O(_n0054)
4969 
  );
4970 
  X_BUF \_COND_1<2>/XUSED  (
4971 
    .I(\_COND_1<2>/FROM ),
4972 
    .O(_COND_1[2])
4973 
  );
4974 
  defparam _n00541.INIT = 16'h11EE;
4975 
  X_LUT4 _n00541 (
4976 
    .ADR0(frame_cnt[2]),
4977 
    .ADR1(frame_cnt_1_1),
4978 
    .ADR2(VCC),
4979 
    .ADR3(frame_cnt[3]),
4980 
    .O(\_COND_1<2>/GROM )
4981 
  );
4982 
  defparam \Madd__n0076_Mxor_Result<1>_Result1 .INIT = 16'hC3C3;
4983 
  X_LUT4 \Madd__n0076_Mxor_Result<1>_Result1  (
4984 
    .ADR0(VCC),
4985 
    .ADR1(frame_cnt_1_1),
4986 
    .ADR2(frame_cnt[2]),
4987 
    .ADR3(VCC),
4988 
    .O(\_COND_1<2>/FROM )
4989 
  );
4990 
  X_BUF \_n0230/YUSED  (
4991 
    .I(\_n0230/GROM ),
4992 
    .O(_n0230)
4993 
  );
4994 
  defparam _n02301.INIT = 16'hEEEE;
4995 
  X_LUT4 _n02301 (
4996 
    .ADR0(frame_delay_cnt_4_1_0),
4997 
    .ADR1(frame_delay_cnt_4_0_0),
4998 
    .ADR2(VCC),
4999 
    .ADR3(VCC),
5000 
    .O(\_n0230/GROM )
5001 
  );
5002 
  X_BUF \_n0231/YUSED  (
5003 
    .I(\_n0231/GROM ),
5004 
    .O(_n0231)
5005 
  );
5006 
  defparam _n02311.INIT = 16'hFFF0;
5007 
  X_LUT4 _n02311 (
5008 
    .ADR0(VCC),
5009 
    .ADR1(VCC),
5010 
    .ADR2(frame_delay_cnt_5_1_0),
5011 
    .ADR3(frame_delay_cnt_5_0_0),
5012 
    .O(\_n0231/GROM )
5013 
  );
5014 
  X_BUF \_n0232/YUSED  (
5015 
    .I(\_n0232/GROM ),
5016 
    .O(_n0232)
5017 
  );
5018 
  defparam _n02321.INIT = 16'hFFCC;
5019 
  X_LUT4 _n02321 (
5020 
    .ADR0(VCC),
5021 
    .ADR1(frame_delay_cnt_6_1_0),
5022 
    .ADR2(VCC),
5023 
    .ADR3(frame_delay_cnt_6_0_0),
5024 
    .O(\_n0232/GROM )
5025 
  );
5026 
  X_BUF \_n0225/YUSED  (
5027 
    .I(\_n0225/GROM ),
5028 
    .O(_n0225)
5029 
  );
5030 
  defparam _n02251.INIT = 16'hFAFA;
5031 
  X_LUT4 _n02251 (
5032 
    .ADR0(frame_delay_cnt_0_0_0),
5033 
    .ADR1(VCC),
5034 
    .ADR2(frame_delay_cnt_0_1_0),
5035 
    .ADR3(VCC),
5036 
    .O(\_n0225/GROM )
5037 
  );
5038 
  X_BUF \_n0233/YUSED  (
5039 
    .I(\_n0233/GROM ),
5040 
    .O(_n0233)
5041 
  );
5042 
  defparam _n02331.INIT = 16'hFFF0;
5043 
  X_LUT4 _n02331 (
5044 
    .ADR0(VCC),
5045 
    .ADR1(VCC),
5046 
    .ADR2(frame_delay_cnt_7_1_0),
5047 
    .ADR3(frame_delay_cnt_7_0_0),
5048 
    .O(\_n0233/GROM )
5049 
  );
5050 
  X_BUF \_n0227/YUSED  (
5051 
    .I(\_n0227/GROM ),
5052 
    .O(_n0227)
5053 
  );
5054 
  defparam _n02271.INIT = 16'hFFCC;
5055 
  X_LUT4 _n02271 (
5056 
    .ADR0(VCC),
5057 
    .ADR1(frame_delay_cnt_1_1_0),
5058 
    .ADR2(VCC),
5059 
    .ADR3(frame_delay_cnt_1_0_0),
5060 
    .O(\_n0227/GROM )
5061 
  );
5062 
  X_BUF \_n0228/YUSED  (
5063 
    .I(\_n0228/GROM ),
5064 
    .O(_n0228)
5065 
  );
5066 
  defparam _n02281.INIT = 16'hEEEE;
5067 
  X_LUT4 _n02281 (
5068 
    .ADR0(frame_delay_cnt_2_0_0),
5069 
    .ADR1(frame_delay_cnt_2_1_0),
5070 
    .ADR2(VCC),
5071 
    .ADR3(VCC),
5072 
    .O(\_n0228/GROM )
5073 
  );
5074 
  X_BUF \_n0229/YUSED  (
5075 
    .I(\_n0229/GROM ),
5076 
    .O(_n0229)
5077 
  );
5078 
  defparam _n02291.INIT = 16'hFCFC;
5079 
  X_LUT4 _n02291 (
5080 
    .ADR0(VCC),
5081 
    .ADR1(frame_delay_cnt_3_0_0),
5082 
    .ADR2(frame_delay_cnt_3_1_0),
5083 
    .ADR3(VCC),
5084 
    .O(\_n0229/GROM )
5085 
  );
5086 
  X_INV \div_reg/SRMUX  (
5087 
    .I(reset_IBUF),
5088 
    .O(\div_reg/SRMUX_OUTPUTNOT )
5089 
  );
5090 
  X_INV \div_reg/BYMUX  (
5091 
    .I(div_reg),
5092 
    .O(\div_reg/BYMUXNOT )
5093 
  );
5094 
  X_INV \rx_shift_reg_0<1>/CKINV  (
5095 
    .I(div_reg_2),
5096 
    .O(\rx_shift_reg_0<1>/CKMUXNOT )
5097 
  );
5098 
  X_INV \rx_shift_reg_0<3>/CKINV  (
5099 
    .I(div_reg_2),
5100 
    .O(\rx_shift_reg_0<3>/CKMUXNOT )
5101 
  );
5102 
  X_INV \rx_shift_reg_0<5>/CKINV  (
5103 
    .I(div_reg_2),
5104 
    .O(\rx_shift_reg_0<5>/CKMUXNOT )
5105 
  );
5106 
  X_INV \rx_shift_reg_1<1>/CKINV  (
5107 
    .I(div_reg_2),
5108 
    .O(\rx_shift_reg_1<1>/CKMUXNOT )
5109 
  );
5110 
  X_INV \rx_shift_reg_1<3>/CKINV  (
5111 
    .I(div_reg_2),
5112 
    .O(\rx_shift_reg_1<3>/CKMUXNOT )
5113 
  );
5114 
  X_INV \rx_shift_reg_0<6>/CKINV  (
5115 
    .I(div_reg_2),
5116 
    .O(\rx_shift_reg_0<6>/CKMUXNOT )
5117 
  );
5118 
  X_INV \rx_shift_reg_1<5>/CKINV  (
5119 
    .I(div_reg_2),
5120 
    .O(\rx_shift_reg_1<5>/CKMUXNOT )
5121 
  );
5122 
  X_INV \rx_shift_reg_2<1>/CKINV  (
5123 
    .I(div_reg_2),
5124 
    .O(\rx_shift_reg_2<1>/CKMUXNOT )
5125 
  );
5126 
  X_INV \rx_shift_reg_1<6>/CKINV  (
5127 
    .I(div_reg_2),
5128 
    .O(\rx_shift_reg_1<6>/CKMUXNOT )
5129 
  );
5130 
  X_INV \rx_shift_reg_2<3>/CKINV  (
5131 
    .I(div_reg_2),
5132 
    .O(\rx_shift_reg_2<3>/CKMUXNOT )
5133 
  );
5134 
  X_INV \rx_shift_reg_2<5>/CKINV  (
5135 
    .I(div_reg_2),
5136 
    .O(\rx_shift_reg_2<5>/CKMUXNOT )
5137 
  );
5138 
  X_INV \rx_shift_reg_3<1>/CKINV  (
5139 
    .I(div_reg_2),
5140 
    .O(\rx_shift_reg_3<1>/CKMUXNOT )
5141 
  );
5142 
  X_INV \rx_shift_reg_2<6>/CKINV  (
5143 
    .I(div_reg_2),
5144 
    .O(\rx_shift_reg_2<6>/CKMUXNOT )
5145 
  );
5146 
  X_INV \rx_shift_reg_3<3>/CKINV  (
5147 
    .I(div_reg_2),
5148 
    .O(\rx_shift_reg_3<3>/CKMUXNOT )
5149 
  );
5150 
  X_BUF \rx_shift_reg_3<3>/FFY/RSTOR  (
5151 
    .I(GSR),
5152 
    .O(\rx_shift_reg_3<3>/FFY/RST )
5153 
  );
5154 
  X_FF rx_shift_reg_3_2 (
5155 
    .I(rx_shift_reg_3[3]),
5156 
    .CE(VCC),
5157 
    .CLK(\rx_shift_reg_3<3>/CKMUXNOT ),
5158 
    .SET(GND),
5159 
    .RST(\rx_shift_reg_3<3>/FFY/RST ),
5160 
    .O(rx_shift_reg_3[2])
5161 
  );
5162 
  X_BUF \rx_shift_reg_3<3>/FFX/RSTOR  (
5163 
    .I(GSR),
5164 
    .O(\rx_shift_reg_3<3>/FFX/RST )
5165 
  );
5166 
  X_FF rx_shift_reg_3_3 (
5167 
    .I(rx_shift_reg_3[4]),
5168 
    .CE(VCC),
5169 
    .CLK(\rx_shift_reg_3<3>/CKMUXNOT ),
5170 
    .SET(GND),
5171 
    .RST(\rx_shift_reg_3<3>/FFX/RST ),
5172 
    .O(rx_shift_reg_3[3])
5173 
  );
5174 
  X_INV \rx_shift_reg_3<5>/CKINV  (
5175 
    .I(div_reg_2),
5176 
    .O(\rx_shift_reg_3<5>/CKMUXNOT )
5177 
  );
5178 
  X_INV \rx_shift_reg_4<1>/CKINV  (
5179 
    .I(div_reg_2),
5180 
    .O(\rx_shift_reg_4<1>/CKMUXNOT )
5181 
  );
5182 
  X_INV \rx_shift_reg_3<6>/CKINV  (
5183 
    .I(div_reg_2),
5184 
    .O(\rx_shift_reg_3<6>/CKMUXNOT )
5185 
  );
5186 
  X_BUF \rx_shift_reg_3<6>/FFY/RSTOR  (
5187 
    .I(GSR),
5188 
    .O(\rx_shift_reg_3<6>/FFY/RST )
5189 
  );
5190 
  X_FF rx_shift_reg_3_6 (
5191 
    .I(rx_shift_reg_3[7]),
5192 
    .CE(VCC),
5193 
    .CLK(\rx_shift_reg_3<6>/CKMUXNOT ),
5194 
    .SET(GND),
5195 
    .RST(\rx_shift_reg_3<6>/FFY/RST ),
5196 
    .O(rx_shift_reg_3[6])
5197 
  );
5198 
  X_INV \rx_shift_reg_4<3>/CKINV  (
5199 
    .I(div_reg_2),
5200 
    .O(\rx_shift_reg_4<3>/CKMUXNOT )
5201 
  );
5202 
  X_INV \rx_shift_reg_4<5>/CKINV  (
5203 
    .I(div_reg_2),
5204 
    .O(\rx_shift_reg_4<5>/CKMUXNOT )
5205 
  );
5206 
  X_BUF \rx_shift_reg_4<5>/FFX/RSTOR  (
5207 
    .I(GSR),
5208 
    .O(\rx_shift_reg_4<5>/FFX/RST )
5209 
  );
5210 
  X_FF rx_shift_reg_4_5 (
5211 
    .I(rx_shift_reg_4[6]),
5212 
    .CE(VCC),
5213 
    .CLK(\rx_shift_reg_4<5>/CKMUXNOT ),
5214 
    .SET(GND),
5215 
    .RST(\rx_shift_reg_4<5>/FFX/RST ),
5216 
    .O(rx_shift_reg_4[5])
5217 
  );
5218 
  X_BUF \rx_shift_reg_4<5>/FFY/RSTOR  (
5219 
    .I(GSR),
5220 
    .O(\rx_shift_reg_4<5>/FFY/RST )
5221 
  );
5222 
  X_FF rx_shift_reg_4_4 (
5223 
    .I(rx_shift_reg_4[5]),
5224 
    .CE(VCC),
5225 
    .CLK(\rx_shift_reg_4<5>/CKMUXNOT ),
5226 
    .SET(GND),
5227 
    .RST(\rx_shift_reg_4<5>/FFY/RST ),
5228 
    .O(rx_shift_reg_4[4])
5229 
  );
5230 
  X_INV \rx_shift_reg_5<1>/CKINV  (
5231 
    .I(div_reg_2),
5232 
    .O(\rx_shift_reg_5<1>/CKMUXNOT )
5233 
  );
5234 
  X_INV \rx_shift_reg_4<6>/CKINV  (
5235 
    .I(div_reg_2),
5236 
    .O(\rx_shift_reg_4<6>/CKMUXNOT )
5237 
  );
5238 
  X_INV \rx_shift_reg_5<3>/CKINV  (
5239 
    .I(div_reg_2),
5240 
    .O(\rx_shift_reg_5<3>/CKMUXNOT )
5241 
  );
5242 
  X_INV \rx_shift_reg_5<5>/CKINV  (
5243 
    .I(div_reg_2),
5244 
    .O(\rx_shift_reg_5<5>/CKMUXNOT )
5245 
  );
5246 
  X_INV \rx_shift_reg_6<1>/CKINV  (
5247 
    .I(div_reg_2),
5248 
    .O(\rx_shift_reg_6<1>/CKMUXNOT )
5249 
  );
5250 
  X_INV \rx_shift_reg_5<6>/CKINV  (
5251 
    .I(div_reg_2),
5252 
    .O(\rx_shift_reg_5<6>/CKMUXNOT )
5253 
  );
5254 
  X_INV \rx_shift_reg_6<3>/CKINV  (
5255 
    .I(div_reg_2),
5256 
    .O(\rx_shift_reg_6<3>/CKMUXNOT )
5257 
  );
5258 
  X_INV \rx_shift_reg_7<1>/CKINV  (
5259 
    .I(div_reg_2),
5260 
    .O(\rx_shift_reg_7<1>/CKMUXNOT )
5261 
  );
5262 
  X_INV \rx_shift_reg_6<5>/CKINV  (
5263 
    .I(div_reg_2),
5264 
    .O(\rx_shift_reg_6<5>/CKMUXNOT )
5265 
  );
5266 
  X_INV \rx_shift_reg_6<6>/CKINV  (
5267 
    .I(div_reg_2),
5268 
    .O(\rx_shift_reg_6<6>/CKMUXNOT )
5269 
  );
5270 
  X_INV \rx_shift_reg_7<3>/CKINV  (
5271 
    .I(div_reg_2),
5272 
    .O(\rx_shift_reg_7<3>/CKMUXNOT )
5273 
  );
5274 
  X_INV \rx_shift_reg_7<5>/CKINV  (
5275 
    .I(div_reg_1),
5276 
    .O(\rx_shift_reg_7<5>/CKMUXNOT )
5277 
  );
5278 
  X_INV \rx_shift_reg_7<6>/CKINV  (
5279 
    .I(div_reg_1),
5280 
    .O(\rx_shift_reg_7<6>/CKMUXNOT )
5281 
  );
5282 
  X_BUF \ram_en/XUSED  (
5283 
    .I(\ram_en/FROM ),
5284 
    .O(ram_en)
5285 
  );
5286 
  defparam Mmux__n0051_I2_Result1.INIT = 16'h4040;
5287 
  X_LUT4 Mmux__n0051_I2_Result1 (
5288 
    .ADR0(mpi_addr_8_IBUF),
5289 
    .ADR1(mpi_mem_bus_out[6]),
5290 
    .ADR2(mpi_cs_IBUF),
5291 
    .ADR3(VCC),
5292 
    .O(\ram_en/GROM )
5293 
  );
5294 
  defparam ram_en1.INIT = 16'h0C0C;
5295 
  X_LUT4 ram_en1 (
5296 
    .ADR0(VCC),
5297 
    .ADR1(mpi_cs_IBUF),
5298 
    .ADR2(mpi_addr_8_IBUF),
5299 
    .ADR3(VCC),
5300 
    .O(\ram_en/FROM )
5301 
  );
5302 
  defparam Mmux__n0051_I6_Result1.INIT = 16'h4040;
5303 
  X_LUT4 Mmux__n0051_I6_Result1 (
5304 
    .ADR0(mpi_addr_8_IBUF),
5305 
    .ADR1(mpi_mem_bus_out[2]),
5306 
    .ADR2(mpi_cs_IBUF),
5307 
    .ADR3(VCC),
5308 
    .O(\mpi_data_out_5_OBUFT/GROM )
5309 
  );
5310 
  defparam Mmux__n0051_I3_Result1.INIT = 16'h2020;
5311 
  X_LUT4 Mmux__n0051_I3_Result1 (
5312 
    .ADR0(mpi_mem_bus_out[5]),
5313 
    .ADR1(mpi_addr_8_IBUF),
5314 
    .ADR2(mpi_cs_IBUF),
5315 
    .ADR3(VCC),
5316 
    .O(\mpi_data_out_5_OBUFT/FROM )
5317 
  );
5318 
  defparam Mmux__n0020_I7_Result1.INIT = 16'hAFA0;
5319 
  X_LUT4 Mmux__n0020_I7_Result1 (
5320 
    .ADR0(tx_buf_reg_1[0]),
5321 
    .ADR1(VCC),
5322 
    .ADR2(Ker87891_1),
5323 
    .ADR3(tx_shift_reg_1[1]),
5324 
    .O(\_n0019<0>/GROM )
5325 
  );
5326 
  defparam Mmux__n0019_I7_Result1.INIT = 16'hFC0C;
5327 
  X_LUT4 Mmux__n0019_I7_Result1 (
5328 
    .ADR0(VCC),
5329 
    .ADR1(tx_shift_reg_0[1]),
5330 
    .ADR2(Ker87891_1),
5331 
    .ADR3(tx_buf_reg_0[0]),
5332 
    .O(\_n0019<0>/FROM )
5333 
  );
5334 
  defparam Mmux__n0021_I7_Result1.INIT = 16'hBB88;
5335 
  X_LUT4 Mmux__n0021_I7_Result1 (
5336 
    .ADR0(tx_buf_reg_2[0]),
5337 
    .ADR1(Ker87891_1),
5338 
    .ADR2(VCC),
5339 
    .ADR3(tx_shift_reg_2[1]),
5340 
    .O(\_n0022<0>/GROM )
5341 
  );
5342 
  defparam Mmux__n0022_I7_Result1.INIT = 16'hCCAA;
5343 
  X_LUT4 Mmux__n0022_I7_Result1 (
5344 
    .ADR0(tx_shift_reg_3[1]),
5345 
    .ADR1(tx_buf_reg_3[0]),
5346 
    .ADR2(VCC),
5347 
    .ADR3(Ker87891_1),
5348 
    .O(\_n0022<0>/FROM )
5349 
  );
5350 
  defparam Mmux__n0023_I7_Result1.INIT = 16'hFA50;
5351 
  X_LUT4 Mmux__n0023_I7_Result1 (
5352 
    .ADR0(Ker87891_1),
5353 
    .ADR1(VCC),
5354 
    .ADR2(tx_shift_reg_4[1]),
5355 
    .ADR3(tx_buf_reg_4[0]),
5356 
    .O(\_n0024<0>/GROM )
5357 
  );
5358 
  defparam Mmux__n0024_I7_Result1.INIT = 16'hFA50;
5359 
  X_LUT4 Mmux__n0024_I7_Result1 (
5360 
    .ADR0(Ker87891_1),
5361 
    .ADR1(VCC),
5362 
    .ADR2(tx_shift_reg_5[1]),
5363 
    .ADR3(tx_buf_reg_5[0]),
5364 
    .O(\_n0024<0>/FROM )
5365 
  );
5366 
  defparam Mmux__n0025_I7_Result1.INIT = 16'hAACC;
5367 
  X_LUT4 Mmux__n0025_I7_Result1 (
5368 
    .ADR0(tx_buf_reg_6[0]),
5369 
    .ADR1(tx_shift_reg_6[1]),
5370 
    .ADR2(VCC),
5371 
    .ADR3(Ker87891_1),
5372 
    .O(\_n0026<0>/GROM )
5373 
  );
5374 
  defparam Mmux__n0026_I7_Result1.INIT = 16'hF5A0;
5375 
  X_LUT4 Mmux__n0026_I7_Result1 (
5376 
    .ADR0(Ker87891_1),
5377 
    .ADR1(VCC),
5378 
    .ADR2(tx_buf_reg_7[0]),
5379 
    .ADR3(tx_shift_reg_7[1]),
5380 
    .O(\_n0026<0>/FROM )
5381 
  );
5382 
  defparam Mmux__n0051_I7_Result1.INIT = 16'hEF40;
5383 
  X_LUT4 Mmux__n0051_I7_Result1 (
5384 
    .ADR0(mpi_addr_8_IBUF),
5385 
    .ADR1(mpi_mem_bus_out[1]),
5386 
    .ADR2(mpi_cs_IBUF),
5387 
    .ADR3(ctrl_out_reg[1]),
5388 
    .O(\mpi_data_out_4_OBUFT/GROM )
5389 
  );
5390 
  defparam Mmux__n0051_I4_Result1.INIT = 16'h00C0;
5391 
  X_LUT4 Mmux__n0051_I4_Result1 (
5392 
    .ADR0(VCC),
5393 
    .ADR1(mpi_mem_bus_out[4]),
5394 
    .ADR2(mpi_cs_IBUF),
5395 
    .ADR3(mpi_addr_8_IBUF),
5396 
    .O(\mpi_data_out_4_OBUFT/FROM )
5397 
  );
5398 
  X_INV \div_reg_2/SRMUX  (
5399 
    .I(reset_IBUF),
5400 
    .O(\div_reg_2/SRMUX_OUTPUTNOT )
5401 
  );
5402 
  X_INV \div_reg_2/BYMUX  (
5403 
    .I(div_reg),
5404 
    .O(\div_reg_2/BYMUXNOT )
5405 
  );
5406 
  X_INV \div_reg_2/BXMUX  (
5407 
    .I(div_reg),
5408 
    .O(\div_reg_2/BXMUXNOT )
5409 
  );
5410 
  X_BUF \frame_delay_cnt_0_0_1__n0000/XUSED  (
5411 
    .I(\frame_delay_cnt_0_0_1__n0000/FROM ),
5412 
    .O(frame_delay_cnt_0_0_1__n0000)
5413 
  );
5414 
  defparam frame_delay_cnt_0_0__n00011.INIT = 16'h5050;
5415 
  X_LUT4 frame_delay_cnt_0_0__n00011 (
5416 
    .ADR0(frame_delay_buf_0[0]),
5417 
    .ADR1(VCC),
5418 
    .ADR2(N8791),
5419 
    .ADR3(VCC),
5420 
    .O(\frame_delay_cnt_0_0_1__n0000/GROM )
5421 
  );
5422 
  defparam frame_delay_cnt_0_1__n00001.INIT = 16'hA050;
5423 
  X_LUT4 frame_delay_cnt_0_1__n00001 (
5424 
    .ADR0(frame_delay_buf_0[0]),
5425 
    .ADR1(VCC),
5426 
    .ADR2(N8791),
5427 
    .ADR3(frame_delay_buf_0[1]),
5428 
    .O(\frame_delay_cnt_0_0_1__n0000/FROM )
5429 
  );
5430 
  X_BUF \frame_delay_cnt_1_0_1__n0000/XUSED  (
5431 
    .I(\frame_delay_cnt_1_0_1__n0000/FROM ),
5432 
    .O(frame_delay_cnt_1_0_1__n0000)
5433 
  );
5434 
  defparam frame_delay_cnt_1_0__n00011.INIT = 16'h3300;
5435 
  X_LUT4 frame_delay_cnt_1_0__n00011 (
5436 
    .ADR0(VCC),
5437 
    .ADR1(frame_delay_buf_1[0]),
5438 
    .ADR2(VCC),
5439 
    .ADR3(N8791),
5440 
    .O(\frame_delay_cnt_1_0_1__n0000/GROM )
5441 
  );
5442 
  defparam frame_delay_cnt_1_1__n00001.INIT = 16'h9900;
5443 
  X_LUT4 frame_delay_cnt_1_1__n00001 (
5444 
    .ADR0(frame_delay_buf_1[0]),
5445 
    .ADR1(frame_delay_buf_1[1]),
5446 
    .ADR2(VCC),
5447 
    .ADR3(N8791),
5448 
    .O(\frame_delay_cnt_1_0_1__n0000/FROM )
5449 
  );
5450 
  X_BUF \d_mem_addr<0>/YUSED  (
5451 
    .I(\d_mem_addr<0>/GROM ),
5452 
    .O(d_mem_addr[0])
5453 
  );
5454 
  defparam Madd_d_mem_low_addr__n00041.INIT = 16'h0F0F;
5455 
  X_LUT4 Madd_d_mem_low_addr__n00041 (
5456 
    .ADR0(VCC),
5457 
    .ADR1(VCC),
5458 
    .ADR2(frame_cnt_1_1),
5459 
    .ADR3(VCC),
5460 
    .O(\d_mem_addr<0>/GROM )
5461 
  );
5462 
  X_BUF \frame_delay_cnt_2_0_1__n0000/XUSED  (
5463 
    .I(\frame_delay_cnt_2_0_1__n0000/FROM ),
5464 
    .O(frame_delay_cnt_2_0_1__n0000)
5465 
  );
5466 
  defparam frame_delay_cnt_2_0__n00011.INIT = 16'h3030;
5467 
  X_LUT4 frame_delay_cnt_2_0__n00011 (
5468 
    .ADR0(VCC),
5469 
    .ADR1(frame_delay_buf_2[0]),
5470 
    .ADR2(N8791),
5471 
    .ADR3(VCC),
5472 
    .O(\frame_delay_cnt_2_0_1__n0000/GROM )
5473 
  );
5474 
  defparam frame_delay_cnt_2_1__n00001.INIT = 16'h8282;
5475 
  X_LUT4 frame_delay_cnt_2_1__n00001 (
5476 
    .ADR0(N8791),
5477 
    .ADR1(frame_delay_buf_2[1]),
5478 
    .ADR2(frame_delay_buf_2[0]),
5479 
    .ADR3(VCC),
5480 
    .O(\frame_delay_cnt_2_0_1__n0000/FROM )
5481 
  );
5482 
  X_BUF \rx_buf_reg_2<5>/FFY/RSTOR  (
5483 
    .I(GSR),
5484 
    .O(\rx_buf_reg_2<5>/FFY/RST )
5485 
  );
5486 
  X_FF rx_buf_reg_2_4 (
5487 
    .I(rx_shift_reg_2[4]),
5488 
    .CE(\_n00611/O ),
5489 
    .CLK(div_reg),
5490 
    .SET(GND),
5491 
    .RST(\rx_buf_reg_2<5>/FFY/RST ),
5492 
    .O(rx_buf_reg_2[4])
5493 
  );
5494 
  X_BUF \rx_buf_reg_2<5>/FFX/RSTOR  (
5495 
    .I(GSR),
5496 
    .O(\rx_buf_reg_2<5>/FFX/RST )
5497 
  );
5498 
  X_FF rx_buf_reg_2_5 (
5499 
    .I(rx_shift_reg_2[5]),
5500 
    .CE(\_n00611/O ),
5501 
    .CLK(div_reg),
5502 
    .SET(GND),
5503 
    .RST(\rx_buf_reg_2<5>/FFX/RST ),
5504 
    .O(rx_buf_reg_2[5])
5505 
  );
5506 
  X_BUF \rx_buf_reg_3<3>/FFY/RSTOR  (
5507 
    .I(GSR),
5508 
    .O(\rx_buf_reg_3<3>/FFY/RST )
5509 
  );
5510 
  X_FF rx_buf_reg_3_2 (
5511 
    .I(rx_shift_reg_3[2]),
5512 
    .CE(\_n00601/O ),
5513 
    .CLK(div_reg),
5514 
    .SET(GND),
5515 
    .RST(\rx_buf_reg_3<3>/FFY/RST ),
5516 
    .O(rx_buf_reg_3[2])
5517 
  );
5518 
  X_BUF \rx_buf_reg_3<3>/FFX/RSTOR  (
5519 
    .I(GSR),
5520 
    .O(\rx_buf_reg_3<3>/FFX/RST )
5521 
  );
5522 
  X_FF rx_buf_reg_3_3 (
5523 
    .I(rx_shift_reg_3[3]),
5524 
    .CE(\_n00601/O ),
5525 
    .CLK(div_reg),
5526 
    .SET(GND),
5527 
    .RST(\rx_buf_reg_3<3>/FFX/RST ),
5528 
    .O(rx_buf_reg_3[3])
5529 
  );
5530 
  X_BUF \rx_buf_reg_3<7>/FFX/RSTOR  (
5531 
    .I(GSR),
5532 
    .O(\rx_buf_reg_3<7>/FFX/RST )
5533 
  );
5534 
  X_FF rx_buf_reg_3_7 (
5535 
    .I(rx_shift_reg_3[7]),
5536 
    .CE(\_n00601/O ),
5537 
    .CLK(div_reg),
5538 
    .SET(GND),
5539 
    .RST(\rx_buf_reg_3<7>/FFX/RST ),
5540 
    .O(rx_buf_reg_3[7])
5541 
  );
5542 
  X_BUF \rx_buf_reg_4<5>/FFX/RSTOR  (
5543 
    .I(GSR),
5544 
    .O(\rx_buf_reg_4<5>/FFX/RST )
5545 
  );
5546 
  X_FF rx_buf_reg_4_5 (
5547 
    .I(rx_shift_reg_4[5]),
5548 
    .CE(\_n00591/O ),
5549 
    .CLK(div_reg),
5550 
    .SET(GND),
5551 
    .RST(\rx_buf_reg_4<5>/FFX/RST ),
5552 
    .O(rx_buf_reg_4[5])
5553 
  );
5554 
  X_BUF \frame_delay_cnt_3_0_1__n0000/XUSED  (
5555 
    .I(\frame_delay_cnt_3_0_1__n0000/FROM ),
5556 
    .O(frame_delay_cnt_3_0_1__n0000)
5557 
  );
5558 
  defparam frame_delay_cnt_3_0__n00011.INIT = 16'h3300;
5559 
  X_LUT4 frame_delay_cnt_3_0__n00011 (
5560 
    .ADR0(VCC),
5561 
    .ADR1(frame_delay_buf_3[0]),
5562 
    .ADR2(VCC),
5563 
    .ADR3(N8791),
5564 
    .O(\frame_delay_cnt_3_0_1__n0000/GROM )
5565 
  );
5566 
  defparam frame_delay_cnt_3_1__n00001.INIT = 16'hC300;
5567 
  X_LUT4 frame_delay_cnt_3_1__n00001 (
5568 
    .ADR0(VCC),
5569 
    .ADR1(frame_delay_buf_3[0]),
5570 
    .ADR2(frame_delay_buf_3[1]),
5571 
    .ADR3(N8791),
5572 
    .O(\frame_delay_cnt_3_0_1__n0000/FROM )
5573 
  );
5574 
  X_BUF \frame_delay_cnt_4_0_1__n0000/XUSED  (
5575 
    .I(\frame_delay_cnt_4_0_1__n0000/FROM ),
5576 
    .O(frame_delay_cnt_4_0_1__n0000)
5577 
  );
5578 
  defparam frame_delay_cnt_4_0__n00011.INIT = 16'h5050;
5579 
  X_LUT4 frame_delay_cnt_4_0__n00011 (
5580 
    .ADR0(frame_delay_buf_4[0]),
5581 
    .ADR1(VCC),
5582 
    .ADR2(N8791),
5583 
    .ADR3(VCC),
5584 
    .O(\frame_delay_cnt_4_0_1__n0000/GROM )
5585 
  );
5586 
  defparam frame_delay_cnt_4_1__n00001.INIT = 16'hA050;
5587 
  X_LUT4 frame_delay_cnt_4_1__n00001 (
5588 
    .ADR0(frame_delay_buf_4[1]),
5589 
    .ADR1(VCC),
5590 
    .ADR2(N8791),
5591 
    .ADR3(frame_delay_buf_4[0]),
5592 
    .O(\frame_delay_cnt_4_0_1__n0000/FROM )
5593 
  );
5594 
  X_BUF \frame_delay_cnt_5_0_1__n0000/XUSED  (
5595 
    .I(\frame_delay_cnt_5_0_1__n0000/FROM ),
5596 
    .O(frame_delay_cnt_5_0_1__n0000)
5597 
  );
5598 
  defparam frame_delay_cnt_5_0__n00011.INIT = 16'h3030;
5599 
  X_LUT4 frame_delay_cnt_5_0__n00011 (
5600 
    .ADR0(VCC),
5601 
    .ADR1(frame_delay_buf_5[0]),
5602 
    .ADR2(N8791),
5603 
    .ADR3(VCC),
5604 
    .O(\frame_delay_cnt_5_0_1__n0000/GROM )
5605 
  );
5606 
  defparam frame_delay_cnt_5_1__n00001.INIT = 16'h9090;
5607 
  X_LUT4 frame_delay_cnt_5_1__n00001 (
5608 
    .ADR0(frame_delay_buf_5[0]),
5609 
    .ADR1(frame_delay_buf_5[1]),
5610 
    .ADR2(N8791),
5611 
    .ADR3(VCC),
5612 
    .O(\frame_delay_cnt_5_0_1__n0000/FROM )
5613 
  );
5614 
  X_BUF \frame_delay_cnt_6_0_1__n0000/XUSED  (
5615 
    .I(\frame_delay_cnt_6_0_1__n0000/FROM ),
5616 
    .O(frame_delay_cnt_6_0_1__n0000)
5617 
  );
5618 
  defparam frame_delay_cnt_6_0__n00011.INIT = 16'h4444;
5619 
  X_LUT4 frame_delay_cnt_6_0__n00011 (
5620 
    .ADR0(frame_delay_buf_6[0]),
5621 
    .ADR1(N8791),
5622 
    .ADR2(VCC),
5623 
    .ADR3(VCC),
5624 
    .O(\frame_delay_cnt_6_0_1__n0000/GROM )
5625 
  );
5626 
  defparam frame_delay_cnt_6_1__n00001.INIT = 16'hA00A;
5627 
  X_LUT4 frame_delay_cnt_6_1__n00001 (
5628 
    .ADR0(N8791),
5629 
    .ADR1(VCC),
5630 
    .ADR2(frame_delay_buf_6[1]),
5631 
    .ADR3(frame_delay_buf_6[0]),
5632 
    .O(\frame_delay_cnt_6_0_1__n0000/FROM )
5633 
  );
5634 
  X_BUF \frame_delay_cnt_7_0_1__n0000/XUSED  (
5635 
    .I(\frame_delay_cnt_7_0_1__n0000/FROM ),
5636 
    .O(frame_delay_cnt_7_0_1__n0000)
5637 
  );
5638 
  defparam frame_delay_cnt_7_0__n00011.INIT = 16'h3030;
5639 
  X_LUT4 frame_delay_cnt_7_0__n00011 (
5640 
    .ADR0(VCC),
5641 
    .ADR1(frame_delay_buf_7[0]),
5642 
    .ADR2(N8791),
5643 
    .ADR3(VCC),
5644 
    .O(\frame_delay_cnt_7_0_1__n0000/GROM )
5645 
  );
5646 
  defparam frame_delay_cnt_7_1__n00001.INIT = 16'hA500;
5647 
  X_LUT4 frame_delay_cnt_7_1__n00001 (
5648 
    .ADR0(frame_delay_buf_7[0]),
5649 
    .ADR1(VCC),
5650 
    .ADR2(frame_delay_buf_7[1]),
5651 
    .ADR3(N8791),
5652 
    .O(\frame_delay_cnt_7_0_1__n0000/FROM )
5653 
  );
5654 
  defparam Mmux__n0051_I0_Result1.INIT = 16'h3000;
5655 
  X_LUT4 Mmux__n0051_I0_Result1 (
5656 
    .ADR0(VCC),
5657 
    .ADR1(mpi_addr_8_IBUF),
5658 
    .ADR2(mpi_mem_bus_out[8]),
5659 
    .ADR3(mpi_cs_IBUF),
5660 
    .O(\mpi_data_out_3_OBUFT/GROM )
5661 
  );
5662 
  defparam Mmux__n0051_I5_Result1.INIT = 16'h3000;
5663 
  X_LUT4 Mmux__n0051_I5_Result1 (
5664 
    .ADR0(VCC),
5665 
    .ADR1(mpi_addr_8_IBUF),
5666 
    .ADR2(mpi_cs_IBUF),
5667 
    .ADR3(mpi_mem_bus_out[3]),
5668 
    .O(\mpi_data_out_3_OBUFT/FROM )
5669 
  );
5670 
  X_INV \frame_cnt_1_1/SRMUX  (
5671 
    .I(reset_IBUF),
5672 
    .O(\frame_cnt_1_1/SRMUX_OUTPUTNOT )
5673 
  );
5674 
  X_INV \frame_cnt_1_1/CKINV  (
5675 
    .I(clk_in_BUFGP),
5676 
    .O(\frame_cnt_1_1/CKMUXNOT )
5677 
  );
5678 
  X_BUF \frame_cnt_1_1/XUSED  (
5679 
    .I(\frame_cnt_1_1/FROM ),
5680 
    .O(GLOBAL_LOGIC0_1)
5681 
  );
5682 
  defparam \frame_cnt_1_1/F .INIT = 16'h0000;
5683 
  X_LUT4 \frame_cnt_1_1/F  (
5684 
    .ADR0(VCC),
5685 
    .ADR1(VCC),
5686 
    .ADR2(VCC),
5687 
    .ADR3(VCC),
5688 
    .O(\frame_cnt_1_1/FROM )
5689 
  );
5690 
  defparam frame_delay_cnt_0_1__n00011.INIT = 16'h4848;
5691 
  X_LUT4 frame_delay_cnt_0_1__n00011 (
5692 
    .ADR0(frame_delay_buf_0[0]),
5693 
    .ADR1(N8791),
5694 
    .ADR2(frame_delay_buf_0[1]),
5695 
    .ADR3(VCC),
5696 
    .O(\frame_delay_cnt_1_0_1__n0001/GROM )
5697 
  );
5698 
  defparam frame_delay_cnt_1_1__n00011.INIT = 16'h4488;
5699 
  X_LUT4 frame_delay_cnt_1_1__n00011 (
5700 
    .ADR0(frame_delay_buf_1[1]),
5701 
    .ADR1(N8791),
5702 
    .ADR2(VCC),
5703 
    .ADR3(frame_delay_buf_1[0]),
5704 
    .O(\frame_delay_cnt_1_0_1__n0001/FROM )
5705 
  );
5706 
  X_BUF \tx_buf_reg_2<7>/FFY/RSTOR  (
5707 
    .I(GSR),
5708 
    .O(\tx_buf_reg_2<7>/FFY/RST )
5709 
  );
5710 
  X_FF tx_buf_reg_2_6 (
5711 
    .I(data_out_bus[6]),
5712 
    .CE(_n0029),
5713 
    .CLK(clk_in_BUFGP),
5714 
    .SET(GND),
5715 
    .RST(\tx_buf_reg_2<7>/FFY/RST ),
5716 
    .O(tx_buf_reg_2[6])
5717 
  );
5718 
  X_BUF \tx_buf_reg_3<5>/FFY/RSTOR  (
5719 
    .I(GSR),
5720 
    .O(\tx_buf_reg_3<5>/FFY/RST )
5721 
  );
5722 
  X_FF tx_buf_reg_3_4 (
5723 
    .I(data_out_bus[4]),
5724 
    .CE(_n0030),
5725 
    .CLK(clk_in_BUFGP),
5726 
    .SET(GND),
5727 
    .RST(\tx_buf_reg_3<5>/FFY/RST ),
5728 
    .O(tx_buf_reg_3[4])
5729 
  );
5730 
  defparam frame_delay_cnt_2_1__n00011.INIT = 16'h0CC0;
5731 
  X_LUT4 frame_delay_cnt_2_1__n00011 (
5732 
    .ADR0(VCC),
5733 
    .ADR1(N8791),
5734 
    .ADR2(frame_delay_buf_2[0]),
5735 
    .ADR3(frame_delay_buf_2[1]),
5736 
    .O(\frame_delay_cnt_3_0_1__n0001/GROM )
5737 
  );
5738 
  defparam frame_delay_cnt_3_1__n00011.INIT = 16'h50A0;
5739 
  X_LUT4 frame_delay_cnt_3_1__n00011 (
5740 
    .ADR0(frame_delay_buf_3[0]),
5741 
    .ADR1(VCC),
5742 
    .ADR2(N8791),
5743 
    .ADR3(frame_delay_buf_3[1]),
5744 
    .O(\frame_delay_cnt_3_0_1__n0001/FROM )
5745 
  );
5746 
  X_SFF c_mem_addr_cnt_2 (
5747 
    .I(c_mem_addr_cnt__n0000[2]),
5748 
    .CE(N8791),
5749 
    .CLK(div_reg),
5750 
    .SET(GND),
5751 
    .RST(GSR),
5752 
    .SSET(GND),
5753 
    .SRST(frame_sync_OBUF),
5754 
    .O(c_mem_addr_cnt[2])
5755 
  );
5756 
  defparam frame_delay_cnt_4_1__n00011.INIT = 16'h6600;
5757 
  X_LUT4 frame_delay_cnt_4_1__n00011 (
5758 
    .ADR0(frame_delay_buf_4[1]),
5759 
    .ADR1(frame_delay_buf_4[0]),
5760 
    .ADR2(VCC),
5761 
    .ADR3(N8791),
5762 
    .O(\frame_delay_cnt_5_0_1__n0001/GROM )
5763 
  );
5764 
  defparam frame_delay_cnt_5_1__n00011.INIT = 16'h5A00;
5765 
  X_LUT4 frame_delay_cnt_5_1__n00011 (
5766 
    .ADR0(frame_delay_buf_5[0]),
5767 
    .ADR1(VCC),
5768 
    .ADR2(frame_delay_buf_5[1]),
5769 
    .ADR3(N8791),
5770 
    .O(\frame_delay_cnt_5_0_1__n0001/FROM )
5771 
  );
5772 
  X_OR2 \frame_cnt<2>/FFY/RSTOR  (
5773 
    .I0(\frame_cnt<2>/SRMUX_OUTPUTNOT ),
5774 
    .I1(GSR),
5775 
    .O(\frame_cnt<2>/FFY/RST )
5776 
  );
5777 
  X_FF frame_cnt_3 (
5778 
    .I(frame_cnt__n0000[3]),
5779 
    .CE(VCC),
5780 
    .CLK(\frame_cnt<2>/CKMUXNOT ),
5781 
    .SET(GND),
5782 
    .RST(\frame_cnt<2>/FFY/RST ),
5783 
    .O(frame_cnt[3])
5784 
  );
5785 
  defparam frame_delay_cnt_6_1__n00011.INIT = 16'h2288;
5786 
  X_LUT4 frame_delay_cnt_6_1__n00011 (
5787 
    .ADR0(N8791),
5788 
    .ADR1(frame_delay_buf_6[0]),
5789 
    .ADR2(VCC),
5790 
    .ADR3(frame_delay_buf_6[1]),
5791 
    .O(\frame_delay_cnt_7_0_1__n0001/GROM )
5792 
  );
5793 
  defparam frame_delay_cnt_7_1__n00011.INIT = 16'h4488;
5794 
  X_LUT4 frame_delay_cnt_7_1__n00011 (
5795 
    .ADR0(frame_delay_buf_7[0]),
5796 
    .ADR1(N8791),
5797 
    .ADR2(VCC),
5798 
    .ADR3(frame_delay_buf_7[1]),
5799 
    .O(\frame_delay_cnt_7_0_1__n0001/FROM )
5800 
  );
5801 
  defparam Mmux__n0051_I1_Result1.INIT = 16'h0088;
5802 
  X_LUT4 Mmux__n0051_I1_Result1 (
5803 
    .ADR0(mpi_mem_bus_out[7]),
5804 
    .ADR1(mpi_cs_IBUF),
5805 
    .ADR2(VCC),
5806 
    .ADR3(mpi_addr_8_IBUF),
5807 
    .O(\mpi_data_out_7_OBUFT/GROM )
5808 
  );
5809 
  X_BUF \tx_shift_reg_1<6>/FFY/RSTOR  (
5810 
    .I(GSR),
5811 
    .O(\tx_shift_reg_1<6>/FFY/RST )
5812 
  );
5813 
  X_FF tx_shift_reg_1_5 (
5814 
    .I(_n0020[5]),
5815 
    .CE(VCC),
5816 
    .CLK(div_reg_1),
5817 
    .SET(GND),
5818 
    .RST(\tx_shift_reg_1<6>/FFY/RST ),
5819 
    .O(tx_shift_reg_1[5])
5820 
  );
5821 
  X_BUF \tx_shift_reg_2<4>/FFX/RSTOR  (
5822 
    .I(GSR),
5823 
    .O(\tx_shift_reg_2<4>/FFX/RST )
5824 
  );
5825 
  X_FF tx_shift_reg_2_4 (
5826 
    .I(_n0021[4]),
5827 
    .CE(VCC),
5828 
    .CLK(div_reg_1),
5829 
    .SET(GND),
5830 
    .RST(\tx_shift_reg_2<4>/FFX/RST ),
5831 
    .O(tx_shift_reg_2[4])
5832 
  );
5833 
  X_BUF \tx_shift_reg_2<7>/FFX/RSTOR  (
5834 
    .I(GSR),
5835 
    .O(\tx_shift_reg_2<7>/FFX/RST )
5836 
  );
5837 
  X_FF tx_shift_reg_2_7 (
5838 
    .I(_n0021[7]),
5839 
    .CE(VCC),
5840 
    .CLK(div_reg_1),
5841 
    .SET(GND),
5842 
    .RST(\tx_shift_reg_2<7>/FFX/RST ),
5843 
    .O(tx_shift_reg_2[7])
5844 
  );
5845 
  X_BUF \tx_shift_reg_2<2>/FFY/RSTOR  (
5846 
    .I(GSR),
5847 
    .O(\tx_shift_reg_2<2>/FFY/RST )
5848 
  );
5849 
  X_FF tx_shift_reg_2_1 (
5850 
    .I(_n0021[1]),
5851 
    .CE(VCC),
5852 
    .CLK(div_reg_1),
5853 
    .SET(GND),
5854 
    .RST(\tx_shift_reg_2<2>/FFY/RST ),
5855 
    .O(tx_shift_reg_2[1])
5856 
  );
5857 
  X_BUF \tx_shift_reg_2<2>/FFX/RSTOR  (
5858 
    .I(GSR),
5859 
    .O(\tx_shift_reg_2<2>/FFX/RST )
5860 
  );
5861 
  X_FF tx_shift_reg_2_2 (
5862 
    .I(_n0021[2]),
5863 
    .CE(VCC),
5864 
    .CLK(div_reg_1),
5865 
    .SET(GND),
5866 
    .RST(\tx_shift_reg_2<2>/FFX/RST ),
5867 
    .O(tx_shift_reg_2[2])
5868 
  );
5869 
  X_BUF \tx_shift_reg_1<6>/FFX/RSTOR  (
5870 
    .I(GSR),
5871 
    .O(\tx_shift_reg_1<6>/FFX/RST )
5872 
  );
5873 
  X_FF tx_shift_reg_1_6 (
5874 
    .I(_n0020[6]),
5875 
    .CE(VCC),
5876 
    .CLK(div_reg_1),
5877 
    .SET(GND),
5878 
    .RST(\tx_shift_reg_1<6>/FFX/RST ),
5879 
    .O(tx_shift_reg_1[6])
5880 
  );
5881 
  X_BUF \tx_shift_reg_3<6>/FFY/RSTOR  (
5882 
    .I(GSR),
5883 
    .O(\tx_shift_reg_3<6>/FFY/RST )
5884 
  );
5885 
  X_FF tx_shift_reg_3_5 (
5886 
    .I(_n0022[5]),
5887 
    .CE(VCC),
5888 
    .CLK(div_reg_1),
5889 
    .SET(GND),
5890 
    .RST(\tx_shift_reg_3<6>/FFY/RST ),
5891 
    .O(tx_shift_reg_3[5])
5892 
  );
5893 
  X_BUF \tx_shift_reg_2<4>/FFY/RSTOR  (
5894 
    .I(GSR),
5895 
    .O(\tx_shift_reg_2<4>/FFY/RST )
5896 
  );
5897 
  X_FF tx_shift_reg_2_3 (
5898 
    .I(_n0021[3]),
5899 
    .CE(VCC),
5900 
    .CLK(div_reg_1),
5901 
    .SET(GND),
5902 
    .RST(\tx_shift_reg_2<4>/FFY/RST ),
5903 
    .O(tx_shift_reg_2[3])
5904 
  );
5905 
  X_BUF \tx_shift_reg_2<7>/FFY/RSTOR  (
5906 
    .I(GSR),
5907 
    .O(\tx_shift_reg_2<7>/FFY/RST )
5908 
  );
5909 
  X_FF tx_shift_reg_1_7 (
5910 
    .I(_n0020[7]),
5911 
    .CE(VCC),
5912 
    .CLK(div_reg_1),
5913 
    .SET(GND),
5914 
    .RST(\tx_shift_reg_2<7>/FFY/RST ),
5915 
    .O(tx_shift_reg_1[7])
5916 
  );
5917 
  X_BUF \tx_shift_reg_2<6>/FFY/RSTOR  (
5918 
    .I(GSR),
5919 
    .O(\tx_shift_reg_2<6>/FFY/RST )
5920 
  );
5921 
  X_FF tx_shift_reg_2_5 (
5922 
    .I(_n0021[5]),
5923 
    .CE(VCC),
5924 
    .CLK(div_reg_1),
5925 
    .SET(GND),
5926 
    .RST(\tx_shift_reg_2<6>/FFY/RST ),
5927 
    .O(tx_shift_reg_2[5])
5928 
  );
5929 
  X_BUF \tx_shift_reg_2<6>/FFX/RSTOR  (
5930 
    .I(GSR),
5931 
    .O(\tx_shift_reg_2<6>/FFX/RST )
5932 
  );
5933 
  X_FF tx_shift_reg_2_6 (
5934 
    .I(_n0021[6]),
5935 
    .CE(VCC),
5936 
    .CLK(div_reg_1),
5937 
    .SET(GND),
5938 
    .RST(\tx_shift_reg_2<6>/FFX/RST ),
5939 
    .O(tx_shift_reg_2[6])
5940 
  );
5941 
  X_BUF \tx_shift_reg_3<2>/FFY/RSTOR  (
5942 
    .I(GSR),
5943 
    .O(\tx_shift_reg_3<2>/FFY/RST )
5944 
  );
5945 
  X_FF tx_shift_reg_3_1 (
5946 
    .I(_n0022[1]),
5947 
    .CE(VCC),
5948 
    .CLK(div_reg_1),
5949 
    .SET(GND),
5950 
    .RST(\tx_shift_reg_3<2>/FFY/RST ),
5951 
    .O(tx_shift_reg_3[1])
5952 
  );
5953 
  X_BUF \tx_shift_reg_3<2>/FFX/RSTOR  (
5954 
    .I(GSR),
5955 
    .O(\tx_shift_reg_3<2>/FFX/RST )
5956 
  );
5957 
  X_FF tx_shift_reg_3_2 (
5958 
    .I(_n0022[2]),
5959 
    .CE(VCC),
5960 
    .CLK(div_reg_1),
5961 
    .SET(GND),
5962 
    .RST(\tx_shift_reg_3<2>/FFX/RST ),
5963 
    .O(tx_shift_reg_3[2])
5964 
  );
5965 
  X_BUF \tx_shift_reg_4<7>/FFY/RSTOR  (
5966 
    .I(GSR),
5967 
    .O(\tx_shift_reg_4<7>/FFY/RST )
5968 
  );
5969 
  X_FF tx_shift_reg_3_7 (
5970 
    .I(_n0022[7]),
5971 
    .CE(VCC),
5972 
    .CLK(div_reg_1),
5973 
    .SET(GND),
5974 
    .RST(\tx_shift_reg_4<7>/FFY/RST ),
5975 
    .O(tx_shift_reg_3[7])
5976 
  );
5977 
  X_BUF \tx_shift_reg_5<2>/FFY/RSTOR  (
5978 
    .I(GSR),
5979 
    .O(\tx_shift_reg_5<2>/FFY/RST )
5980 
  );
5981 
  X_FF tx_shift_reg_5_1 (
5982 
    .I(_n0024[1]),
5983 
    .CE(VCC),
5984 
    .CLK(div_reg_1),
5985 
    .SET(GND),
5986 
    .RST(\tx_shift_reg_5<2>/FFY/RST ),
5987 
    .O(tx_shift_reg_5[1])
5988 
  );
5989 
  X_BUF \tx_shift_reg_3<4>/FFX/RSTOR  (
5990 
    .I(GSR),
5991 
    .O(\tx_shift_reg_3<4>/FFX/RST )
5992 
  );
5993 
  X_FF tx_shift_reg_3_4 (
5994 
    .I(_n0022[4]),
5995 
    .CE(VCC),
5996 
    .CLK(div_reg_1),
5997 
    .SET(GND),
5998 
    .RST(\tx_shift_reg_3<4>/FFX/RST ),
5999 
    .O(tx_shift_reg_3[4])
6000 
  );
6001 
  X_BUF \tx_shift_reg_3<4>/FFY/RSTOR  (
6002 
    .I(GSR),
6003 
    .O(\tx_shift_reg_3<4>/FFY/RST )
6004 
  );
6005 
  X_FF tx_shift_reg_3_3 (
6006 
    .I(_n0022[3]),
6007 
    .CE(VCC),
6008 
    .CLK(div_reg_1),
6009 
    .SET(GND),
6010 
    .RST(\tx_shift_reg_3<4>/FFY/RST ),
6011 
    .O(tx_shift_reg_3[3])
6012 
  );
6013 
  X_BUF \tx_shift_reg_4<2>/FFY/RSTOR  (
6014 
    .I(GSR),
6015 
    .O(\tx_shift_reg_4<2>/FFY/RST )
6016 
  );
6017 
  X_FF tx_shift_reg_4_1 (
6018 
    .I(_n0023[1]),
6019 
    .CE(VCC),
6020 
    .CLK(div_reg_1),
6021 
    .SET(GND),
6022 
    .RST(\tx_shift_reg_4<2>/FFY/RST ),
6023 
    .O(tx_shift_reg_4[1])
6024 
  );
6025 
  X_BUF \rx_buf_reg_3<7>/FFY/RSTOR  (
6026 
    .I(GSR),
6027 
    .O(\rx_buf_reg_3<7>/FFY/RST )
6028 
  );
6029 
  X_FF rx_buf_reg_3_6 (
6030 
    .I(rx_shift_reg_3[6]),
6031 
    .CE(\_n00601/O ),
6032 
    .CLK(div_reg),
6033 
    .SET(GND),
6034 
    .RST(\rx_buf_reg_3<7>/FFY/RST ),
6035 
    .O(rx_buf_reg_3[6])
6036 
  );
6037 
  X_BUF \tx_shift_reg_3<6>/FFX/RSTOR  (
6038 
    .I(GSR),
6039 
    .O(\tx_shift_reg_3<6>/FFX/RST )
6040 
  );
6041 
  X_FF tx_shift_reg_3_6 (
6042 
    .I(_n0022[6]),
6043 
    .CE(VCC),
6044 
    .CLK(div_reg_1),
6045 
    .SET(GND),
6046 
    .RST(\tx_shift_reg_3<6>/FFX/RST ),
6047 
    .O(tx_shift_reg_3[6])
6048 
  );
6049 
  X_BUF \tx_shift_reg_4<6>/FFY/RSTOR  (
6050 
    .I(GSR),
6051 
    .O(\tx_shift_reg_4<6>/FFY/RST )
6052 
  );
6053 
  X_FF tx_shift_reg_4_5 (
6054 
    .I(_n0023[5]),
6055 
    .CE(VCC),
6056 
    .CLK(div_reg_1),
6057 
    .SET(GND),
6058 
    .RST(\tx_shift_reg_4<6>/FFY/RST ),
6059 
    .O(tx_shift_reg_4[5])
6060 
  );
6061 
  X_BUF \tx_shift_reg_4<2>/FFX/RSTOR  (
6062 
    .I(GSR),
6063 
    .O(\tx_shift_reg_4<2>/FFX/RST )
6064 
  );
6065 
  X_FF tx_shift_reg_4_2 (
6066 
    .I(_n0023[2]),
6067 
    .CE(VCC),
6068 
    .CLK(div_reg_1),
6069 
    .SET(GND),
6070 
    .RST(\tx_shift_reg_4<2>/FFX/RST ),
6071 
    .O(tx_shift_reg_4[2])
6072 
  );
6073 
  X_BUF \tx_shift_reg_4<4>/FFY/RSTOR  (
6074 
    .I(GSR),
6075 
    .O(\tx_shift_reg_4<4>/FFY/RST )
6076 
  );
6077 
  X_FF tx_shift_reg_4_3 (
6078 
    .I(_n0023[3]),
6079 
    .CE(VCC),
6080 
    .CLK(div_reg_1),
6081 
    .SET(GND),
6082 
    .RST(\tx_shift_reg_4<4>/FFY/RST ),
6083 
    .O(tx_shift_reg_4[3])
6084 
  );
6085 
  X_BUF \tx_shift_reg_4<4>/FFX/RSTOR  (
6086 
    .I(GSR),
6087 
    .O(\tx_shift_reg_4<4>/FFX/RST )
6088 
  );
6089 
  X_FF tx_shift_reg_4_4 (
6090 
    .I(_n0023[4]),
6091 
    .CE(VCC),
6092 
    .CLK(div_reg_1),
6093 
    .SET(GND),
6094 
    .RST(\tx_shift_reg_4<4>/FFX/RST ),
6095 
    .O(tx_shift_reg_4[4])
6096 
  );
6097 
  X_BUF \tx_shift_reg_5<6>/FFY/RSTOR  (
6098 
    .I(GSR),
6099 
    .O(\tx_shift_reg_5<6>/FFY/RST )
6100 
  );
6101 
  X_FF tx_shift_reg_5_5 (
6102 
    .I(_n0024[5]),
6103 
    .CE(VCC),
6104 
    .CLK(div_reg_1),
6105 
    .SET(GND),
6106 
    .RST(\tx_shift_reg_5<6>/FFY/RST ),
6107 
    .O(tx_shift_reg_5[5])
6108 
  );
6109 
  X_BUF \tx_shift_reg_4<7>/FFX/RSTOR  (
6110 
    .I(GSR),
6111 
    .O(\tx_shift_reg_4<7>/FFX/RST )
6112 
  );
6113 
  X_FF tx_shift_reg_4_7 (
6114 
    .I(_n0023[7]),
6115 
    .CE(VCC),
6116 
    .CLK(div_reg_1),
6117 
    .SET(GND),
6118 
    .RST(\tx_shift_reg_4<7>/FFX/RST ),
6119 
    .O(tx_shift_reg_4[7])
6120 
  );
6121 
  X_BUF \tx_shift_reg_4<6>/FFX/RSTOR  (
6122 
    .I(GSR),
6123 
    .O(\tx_shift_reg_4<6>/FFX/RST )
6124 
  );
6125 
  X_FF tx_shift_reg_4_6 (
6126 
    .I(_n0023[6]),
6127 
    .CE(VCC),
6128 
    .CLK(div_reg_1),
6129 
    .SET(GND),
6130 
    .RST(\tx_shift_reg_4<6>/FFX/RST ),
6131 
    .O(tx_shift_reg_4[6])
6132 
  );
6133 
  X_BUF \tx_shift_reg_5<2>/FFX/RSTOR  (
6134 
    .I(GSR),
6135 
    .O(\tx_shift_reg_5<2>/FFX/RST )
6136 
  );
6137 
  X_FF tx_shift_reg_5_2 (
6138 
    .I(_n0024[2]),
6139 
    .CE(VCC),
6140 
    .CLK(div_reg_1),
6141 
    .SET(GND),
6142 
    .RST(\tx_shift_reg_5<2>/FFX/RST ),
6143 
    .O(tx_shift_reg_5[2])
6144 
  );
6145 
  X_BUF \tx_shift_reg_7<2>/FFY/RSTOR  (
6146 
    .I(GSR),
6147 
    .O(\tx_shift_reg_7<2>/FFY/RST )
6148 
  );
6149 
  X_FF tx_shift_reg_7_1 (
6150 
    .I(_n0026[1]),
6151 
    .CE(VCC),
6152 
    .CLK(div_reg_1),
6153 
    .SET(GND),
6154 
    .RST(\tx_shift_reg_7<2>/FFY/RST ),
6155 
    .O(tx_shift_reg_7[1])
6156 
  );
6157 
  X_BUF \tx_shift_reg_7<6>/FFY/RSTOR  (
6158 
    .I(GSR),
6159 
    .O(\tx_shift_reg_7<6>/FFY/RST )
6160 
  );
6161 
  X_FF tx_shift_reg_7_5 (
6162 
    .I(_n0026[5]),
6163 
    .CE(VCC),
6164 
    .CLK(div_reg_1),
6165 
    .SET(GND),
6166 
    .RST(\tx_shift_reg_7<6>/FFY/RST ),
6167 
    .O(tx_shift_reg_7[5])
6168 
  );
6169 
  X_BUF \tx_shift_reg_5<4>/FFX/RSTOR  (
6170 
    .I(GSR),
6171 
    .O(\tx_shift_reg_5<4>/FFX/RST )
6172 
  );
6173 
  X_FF tx_shift_reg_5_4 (
6174 
    .I(_n0024[4]),
6175 
    .CE(VCC),
6176 
    .CLK(div_reg_1),
6177 
    .SET(GND),
6178 
    .RST(\tx_shift_reg_5<4>/FFX/RST ),
6179 
    .O(tx_shift_reg_5[4])
6180 
  );
6181 
  X_BUF \tx_shift_reg_5<4>/FFY/RSTOR  (
6182 
    .I(GSR),
6183 
    .O(\tx_shift_reg_5<4>/FFY/RST )
6184 
  );
6185 
  X_FF tx_shift_reg_5_3 (
6186 
    .I(_n0024[3]),
6187 
    .CE(VCC),
6188 
    .CLK(div_reg_1),
6189 
    .SET(GND),
6190 
    .RST(\tx_shift_reg_5<4>/FFY/RST ),
6191 
    .O(tx_shift_reg_5[3])
6192 
  );
6193 
  X_BUF \tx_shift_reg_6<2>/FFY/RSTOR  (
6194 
    .I(GSR),
6195 
    .O(\tx_shift_reg_6<2>/FFY/RST )
6196 
  );
6197 
  X_FF tx_shift_reg_6_1 (
6198 
    .I(_n0025[1]),
6199 
    .CE(VCC),
6200 
    .CLK(div_reg_1),
6201 
    .SET(GND),
6202 
    .RST(\tx_shift_reg_6<2>/FFY/RST ),
6203 
    .O(tx_shift_reg_6[1])
6204 
  );
6205 
  X_BUF \tx_shift_reg_5<6>/FFX/RSTOR  (
6206 
    .I(GSR),
6207 
    .O(\tx_shift_reg_5<6>/FFX/RST )
6208 
  );
6209 
  X_FF tx_shift_reg_5_6 (
6210 
    .I(_n0024[6]),
6211 
    .CE(VCC),
6212 
    .CLK(div_reg_1),
6213 
    .SET(GND),
6214 
    .RST(\tx_shift_reg_5<6>/FFX/RST ),
6215 
    .O(tx_shift_reg_5[6])
6216 
  );
6217 
  X_BUF \tx_shift_reg_6<7>/FFY/RSTOR  (
6218 
    .I(GSR),
6219 
    .O(\tx_shift_reg_6<7>/FFY/RST )
6220 
  );
6221 
  X_FF tx_shift_reg_5_7 (
6222 
    .I(_n0024[7]),
6223 
    .CE(VCC),
6224 
    .CLK(div_reg_1),
6225 
    .SET(GND),
6226 
    .RST(\tx_shift_reg_6<7>/FFY/RST ),
6227 
    .O(tx_shift_reg_5[7])
6228 
  );
6229 
  X_BUF \tx_buf_reg_4<3>/FFX/RSTOR  (
6230 
    .I(GSR),
6231 
    .O(\tx_buf_reg_4<3>/FFX/RST )
6232 
  );
6233 
  X_FF tx_buf_reg_4_3 (
6234 
    .I(data_out_bus[3]),
6235 
    .CE(\_n00311/O ),
6236 
    .CLK(clk_in_BUFGP),
6237 
    .SET(GND),
6238 
    .RST(\tx_buf_reg_4<3>/FFX/RST ),
6239 
    .O(tx_buf_reg_4[3])
6240 
  );
6241 
  X_BUF \tx_shift_reg_6<2>/FFX/RSTOR  (
6242 
    .I(GSR),
6243 
    .O(\tx_shift_reg_6<2>/FFX/RST )
6244 
  );
6245 
  X_FF tx_shift_reg_6_2 (
6246 
    .I(_n0025[2]),
6247 
    .CE(VCC),
6248 
    .CLK(div_reg_1),
6249 
    .SET(GND),
6250 
    .RST(\tx_shift_reg_6<2>/FFX/RST ),
6251 
    .O(tx_shift_reg_6[2])
6252 
  );
6253 
  X_BUF \tx_shift_reg_6<7>/FFX/RSTOR  (
6254 
    .I(GSR),
6255 
    .O(\tx_shift_reg_6<7>/FFX/RST )
6256 
  );
6257 
  X_FF tx_shift_reg_6_7 (
6258 
    .I(_n0025[7]),
6259 
    .CE(VCC),
6260 
    .CLK(div_reg_1),
6261 
    .SET(GND),
6262 
    .RST(\tx_shift_reg_6<7>/FFX/RST ),
6263 
    .O(tx_shift_reg_6[7])
6264 
  );
6265 
  X_OR2 \frame_delay_cnt_7_1_0/FFY/RSTOR  (
6266 
    .I0(frame_delay_cnt_7_0_1__n0000),
6267 
    .I1(GSR),
6268 
    .O(\frame_delay_cnt_7_1_0/FFY/RST )
6269 
  );
6270 
  X_BUF \frame_delay_cnt_7_1_0/FFY/SETOR  (
6271 
    .I(\frame_delay_cnt_7_0_1__n0001/FROM ),
6272 
    .O(\frame_delay_cnt_7_1_0/FFY/SET )
6273 
  );
6274 
  X_FF frame_delay_cnt_7_1_0_83 (
6275 
    .I(frame_delay_cnt_7__n0001[1]),
6276 
    .CE(_n0233),
6277 
    .CLK(\frame_delay_cnt_7_1_0/CKMUXNOT ),
6278 
    .SET(\frame_delay_cnt_7_1_0/FFY/SET ),
6279 
    .RST(\frame_delay_cnt_7_1_0/FFY/RST ),
6280 
    .O(frame_delay_cnt_7_1_0)
6281 
  );
6282 
  X_BUF \tx_shift_reg_7<6>/FFX/RSTOR  (
6283 
    .I(GSR),
6284 
    .O(\tx_shift_reg_7<6>/FFX/RST )
6285 
  );
6286 
  X_FF tx_shift_reg_7_6 (
6287 
    .I(_n0026[6]),
6288 
    .CE(VCC),
6289 
    .CLK(div_reg_1),
6290 
    .SET(GND),
6291 
    .RST(\tx_shift_reg_7<6>/FFX/RST ),
6292 
    .O(tx_shift_reg_7[6])
6293 
  );
6294 
  X_BUF \tx_shift_reg_7<2>/FFX/RSTOR  (
6295 
    .I(GSR),
6296 
    .O(\tx_shift_reg_7<2>/FFX/RST )
6297 
  );
6298 
  X_FF tx_shift_reg_7_2 (
6299 
    .I(_n0026[2]),
6300 
    .CE(VCC),
6301 
    .CLK(div_reg_1),
6302 
    .SET(GND),
6303 
    .RST(\tx_shift_reg_7<2>/FFX/RST ),
6304 
    .O(tx_shift_reg_7[2])
6305 
  );
6306 
  X_OR2 \mem_page_sel/FFY/RSTOR  (
6307 
    .I0(\mem_page_sel/SRMUX_OUTPUTNOT ),
6308 
    .I1(GSR),
6309 
    .O(\mem_page_sel/FFY/RST )
6310 
  );
6311 
  X_FF mem_page_sel_84 (
6312 
    .I(\mem_page_sel/GROM ),
6313 
    .CE(frame_sync_OBUF),
6314 
    .CLK(div_reg),
6315 
    .SET(GND),
6316 
    .RST(\mem_page_sel/FFY/RST ),
6317 
    .O(mem_page_sel)
6318 
  );
6319 
  X_BUF \tx_buf_reg_2<7>/FFX/RSTOR  (
6320 
    .I(GSR),
6321 
    .O(\tx_buf_reg_2<7>/FFX/RST )
6322 
  );
6323 
  X_FF tx_buf_reg_2_7 (
6324 
    .I(data_out_bus[7]),
6325 
    .CE(_n0029),
6326 
    .CLK(clk_in_BUFGP),
6327 
    .SET(GND),
6328 
    .RST(\tx_buf_reg_2<7>/FFX/RST ),
6329 
    .O(tx_buf_reg_2[7])
6330 
  );
6331 
  X_BUF \rx_shift_reg_4<6>/FFY/RSTOR  (
6332 
    .I(GSR),
6333 
    .O(\rx_shift_reg_4<6>/FFY/RST )
6334 
  );
6335 
  X_FF rx_shift_reg_4_6 (
6336 
    .I(rx_shift_reg_4[7]),
6337 
    .CE(VCC),
6338 
    .CLK(\rx_shift_reg_4<6>/CKMUXNOT ),
6339 
    .SET(GND),
6340 
    .RST(\rx_shift_reg_4<6>/FFY/RST ),
6341 
    .O(rx_shift_reg_4[6])
6342 
  );
6343 
  X_BUF \ctrl_out_reg<1>/FFY/RSTOR  (
6344 
    .I(GSR),
6345 
    .O(\ctrl_out_reg<1>/FFY/RST )
6346 
  );
6347 
  X_FF ctrl_out_reg_1 (
6348 
    .I(_n0046[1]),
6349 
    .CE(VCC),
6350 
    .CLK(mpi_clk_BUFGP),
6351 
    .SET(GND),
6352 
    .RST(\ctrl_out_reg<1>/FFY/RST ),
6353 
    .O(ctrl_out_reg[1])
6354 
  );
6355 
  X_BUF \rx_shift_reg_5<5>/FFX/RSTOR  (
6356 
    .I(GSR),
6357 
    .O(\rx_shift_reg_5<5>/FFX/RST )
6358 
  );
6359 
  X_FF rx_shift_reg_5_5 (
6360 
    .I(rx_shift_reg_5[6]),
6361 
    .CE(VCC),
6362 
    .CLK(\rx_shift_reg_5<5>/CKMUXNOT ),
6363 
    .SET(GND),
6364 
    .RST(\rx_shift_reg_5<5>/FFX/RST ),
6365 
    .O(rx_shift_reg_5[5])
6366 
  );
6367 
  X_BUF \tx_shift_reg_7<7>/FFY/RSTOR  (
6368 
    .I(GSR),
6369 
    .O(\tx_shift_reg_7<7>/FFY/RST )
6370 
  );
6371 
  X_FF tx_shift_reg_7_7 (
6372 
    .I(_n0026[7]),
6373 
    .CE(VCC),
6374 
    .CLK(div_reg_1),
6375 
    .SET(GND),
6376 
    .RST(\tx_shift_reg_7<7>/FFY/RST ),
6377 
    .O(tx_shift_reg_7[7])
6378 
  );
6379 
  X_BUF \ctrl_out_reg<0>/FFY/RSTOR  (
6380 
    .I(GSR),
6381 
    .O(\ctrl_out_reg<0>/FFY/RST )
6382 
  );
6383 
  X_FF ctrl_out_reg_0 (
6384 
    .I(_n0046[0]),
6385 
    .CE(VCC),
6386 
    .CLK(mpi_clk_BUFGP),
6387 
    .SET(GND),
6388 
    .RST(\ctrl_out_reg<0>/FFY/RST ),
6389 
    .O(ctrl_out_reg[0])
6390 
  );
6391 
  X_OR2 \frame_delay_cnt_0_0_0/FFY/RSTOR  (
6392 
    .I0(frame_delay_cnt_0_0_0__n0000),
6393 
    .I1(GSR),
6394 
    .O(\frame_delay_cnt_0_0_0/FFY/RST )
6395 
  );
6396 
  X_BUF \frame_delay_cnt_0_0_0/FFY/SETOR  (
6397 
    .I(\frame_delay_cnt_0_0_1__n0000/GROM ),
6398 
    .O(\frame_delay_cnt_0_0_0/FFY/SET )
6399 
  );
6400 
  X_FF frame_delay_cnt_0_0_0_85 (
6401 
    .I(frame_delay_cnt_0__n0001[0]),
6402 
    .CE(_n0225),
6403 
    .CLK(\frame_delay_cnt_0_0_0/CKMUXNOT ),
6404 
    .SET(\frame_delay_cnt_0_0_0/FFY/SET ),
6405 
    .RST(\frame_delay_cnt_0_0_0/FFY/RST ),
6406 
    .O(frame_delay_cnt_0_0_0)
6407 
  );
6408 
  X_OR2 \frame_delay_cnt_0_1_0/FFY/RSTOR  (
6409 
    .I0(frame_delay_cnt_0_0_1__n0000),
6410 
    .I1(GSR),
6411 
    .O(\frame_delay_cnt_0_1_0/FFY/RST )
6412 
  );
6413 
  X_BUF \frame_delay_cnt_0_1_0/FFY/SETOR  (
6414 
    .I(\frame_delay_cnt_1_0_1__n0001/GROM ),
6415 
    .O(\frame_delay_cnt_0_1_0/FFY/SET )
6416 
  );
6417 
  X_FF frame_delay_cnt_0_1_0_86 (
6418 
    .I(frame_delay_cnt_0__n0001[1]),
6419 
    .CE(_n0225),
6420 
    .CLK(\frame_delay_cnt_0_1_0/CKMUXNOT ),
6421 
    .SET(\frame_delay_cnt_0_1_0/FFY/SET ),
6422 
    .RST(\frame_delay_cnt_0_1_0/FFY/RST ),
6423 
    .O(frame_delay_cnt_0_1_0)
6424 
  );
6425 
  X_OR2 \frame_delay_cnt_1_0_0/FFY/RSTOR  (
6426 
    .I0(frame_delay_cnt_1_0_0__n0000),
6427 
    .I1(GSR),
6428 
    .O(\frame_delay_cnt_1_0_0/FFY/RST )
6429 
  );
6430 
  X_BUF \frame_delay_cnt_1_0_0/FFY/SETOR  (
6431 
    .I(\frame_delay_cnt_1_0_1__n0000/GROM ),
6432 
    .O(\frame_delay_cnt_1_0_0/FFY/SET )
6433 
  );
6434 
  X_FF frame_delay_cnt_1_0_0_87 (
6435 
    .I(frame_delay_cnt_1__n0001[0]),
6436 
    .CE(_n0227),
6437 
    .CLK(\frame_delay_cnt_1_0_0/CKMUXNOT ),
6438 
    .SET(\frame_delay_cnt_1_0_0/FFY/SET ),
6439 
    .RST(\frame_delay_cnt_1_0_0/FFY/RST ),
6440 
    .O(frame_delay_cnt_1_0_0)
6441 
  );
6442 
  X_BUF \rx_buf_reg_4<5>/FFY/RSTOR  (
6443 
    .I(GSR),
6444 
    .O(\rx_buf_reg_4<5>/FFY/RST )
6445 
  );
6446 
  X_FF rx_buf_reg_4_4 (
6447 
    .I(rx_shift_reg_4[4]),
6448 
    .CE(\_n00591/O ),
6449 
    .CLK(div_reg),
6450 
    .SET(GND),
6451 
    .RST(\rx_buf_reg_4<5>/FFY/RST ),
6452 
    .O(rx_buf_reg_4[4])
6453 
  );
6454 
  X_OR2 \frame_delay_cnt_6_0_0/FFY/RSTOR  (
6455 
    .I0(frame_delay_cnt_6_0_0__n0000),
6456 
    .I1(GSR),
6457 
    .O(\frame_delay_cnt_6_0_0/FFY/RST )
6458 
  );
6459 
  X_BUF \frame_delay_cnt_6_0_0/FFY/SETOR  (
6460 
    .I(\frame_delay_cnt_6_0_1__n0000/GROM ),
6461 
    .O(\frame_delay_cnt_6_0_0/FFY/SET )
6462 
  );
6463 
  X_FF frame_delay_cnt_6_0_0_88 (
6464 
    .I(frame_delay_cnt_6__n0001[0]),
6465 
    .CE(_n0232),
6466 
    .CLK(\frame_delay_cnt_6_0_0/CKMUXNOT ),
6467 
    .SET(\frame_delay_cnt_6_0_0/FFY/SET ),
6468 
    .RST(\frame_delay_cnt_6_0_0/FFY/RST ),
6469 
    .O(frame_delay_cnt_6_0_0)
6470 
  );
6471 
  X_OR2 \frame_delay_cnt_1_1_0/FFY/RSTOR  (
6472 
    .I0(frame_delay_cnt_1_0_1__n0000),
6473 
    .I1(GSR),
6474 
    .O(\frame_delay_cnt_1_1_0/FFY/RST )
6475 
  );
6476 
  X_BUF \frame_delay_cnt_1_1_0/FFY/SETOR  (
6477 
    .I(\frame_delay_cnt_1_0_1__n0001/FROM ),
6478 
    .O(\frame_delay_cnt_1_1_0/FFY/SET )
6479 
  );
6480 
  X_FF frame_delay_cnt_1_1_0_89 (
6481 
    .I(frame_delay_cnt_1__n0001[1]),
6482 
    .CE(_n0227),
6483 
    .CLK(\frame_delay_cnt_1_1_0/CKMUXNOT ),
6484 
    .SET(\frame_delay_cnt_1_1_0/FFY/SET ),
6485 
    .RST(\frame_delay_cnt_1_1_0/FFY/RST ),
6486 
    .O(frame_delay_cnt_1_1_0)
6487 
  );
6488 
  X_OR2 \frame_delay_cnt_2_0_0/FFY/RSTOR  (
6489 
    .I0(frame_delay_cnt_2_0_0__n0000),
6490 
    .I1(GSR),
6491 
    .O(\frame_delay_cnt_2_0_0/FFY/RST )
6492 
  );
6493 
  X_BUF \frame_delay_cnt_2_0_0/FFY/SETOR  (
6494 
    .I(\frame_delay_cnt_2_0_1__n0000/GROM ),
6495 
    .O(\frame_delay_cnt_2_0_0/FFY/SET )
6496 
  );
6497 
  X_FF frame_delay_cnt_2_0_0_90 (
6498 
    .I(frame_delay_cnt_2__n0001[0]),
6499 
    .CE(_n0228),
6500 
    .CLK(\frame_delay_cnt_2_0_0/CKMUXNOT ),
6501 
    .SET(\frame_delay_cnt_2_0_0/FFY/SET ),
6502 
    .RST(\frame_delay_cnt_2_0_0/FFY/RST ),
6503 
    .O(frame_delay_cnt_2_0_0)
6504 
  );
6505 
  X_OR2 \frame_delay_cnt_2_1_0/FFY/RSTOR  (
6506 
    .I0(frame_delay_cnt_2_0_1__n0000),
6507 
    .I1(GSR),
6508 
    .O(\frame_delay_cnt_2_1_0/FFY/RST )
6509 
  );
6510 
  X_BUF \frame_delay_cnt_2_1_0/FFY/SETOR  (
6511 
    .I(\frame_delay_cnt_3_0_1__n0001/GROM ),
6512 
    .O(\frame_delay_cnt_2_1_0/FFY/SET )
6513 
  );
6514 
  X_FF frame_delay_cnt_2_1_0_91 (
6515 
    .I(frame_delay_cnt_2__n0001[1]),
6516 
    .CE(_n0228),
6517 
    .CLK(\frame_delay_cnt_2_1_0/CKMUXNOT ),
6518 
    .SET(\frame_delay_cnt_2_1_0/FFY/SET ),
6519 
    .RST(\frame_delay_cnt_2_1_0/FFY/RST ),
6520 
    .O(frame_delay_cnt_2_1_0)
6521 
  );
6522 
  X_OR2 \frame_delay_cnt_3_0_0/FFY/RSTOR  (
6523 
    .I0(frame_delay_cnt_3_0_0__n0000),
6524 
    .I1(GSR),
6525 
    .O(\frame_delay_cnt_3_0_0/FFY/RST )
6526 
  );
6527 
  X_BUF \frame_delay_cnt_3_0_0/FFY/SETOR  (
6528 
    .I(\frame_delay_cnt_3_0_1__n0000/GROM ),
6529 
    .O(\frame_delay_cnt_3_0_0/FFY/SET )
6530 
  );
6531 
  X_FF frame_delay_cnt_3_0_0_92 (
6532 
    .I(frame_delay_cnt_3__n0001[0]),
6533 
    .CE(_n0229),
6534 
    .CLK(\frame_delay_cnt_3_0_0/CKMUXNOT ),
6535 
    .SET(\frame_delay_cnt_3_0_0/FFY/SET ),
6536 
    .RST(\frame_delay_cnt_3_0_0/FFY/RST ),
6537 
    .O(frame_delay_cnt_3_0_0)
6538 
  );
6539 
  X_OR2 \frame_delay_cnt_3_1_0/FFY/RSTOR  (
6540 
    .I0(frame_delay_cnt_3_0_1__n0000),
6541 
    .I1(GSR),
6542 
    .O(\frame_delay_cnt_3_1_0/FFY/RST )
6543 
  );
6544 
  X_BUF \frame_delay_cnt_3_1_0/FFY/SETOR  (
6545 
    .I(\frame_delay_cnt_3_0_1__n0001/FROM ),
6546 
    .O(\frame_delay_cnt_3_1_0/FFY/SET )
6547 
  );
6548 
  X_FF frame_delay_cnt_3_1_0_93 (
6549 
    .I(frame_delay_cnt_3__n0001[1]),
6550 
    .CE(_n0229),
6551 
    .CLK(\frame_delay_cnt_3_1_0/CKMUXNOT ),
6552 
    .SET(\frame_delay_cnt_3_1_0/FFY/SET ),
6553 
    .RST(\frame_delay_cnt_3_1_0/FFY/RST ),
6554 
    .O(frame_delay_cnt_3_1_0)
6555 
  );
6556 
  X_OR2 \frame_delay_cnt_4_0_0/FFY/RSTOR  (
6557 
    .I0(frame_delay_cnt_4_0_0__n0000),
6558 
    .I1(GSR),
6559 
    .O(\frame_delay_cnt_4_0_0/FFY/RST )
6560 
  );
6561 
  X_BUF \frame_delay_cnt_4_0_0/FFY/SETOR  (
6562 
    .I(\frame_delay_cnt_4_0_1__n0000/GROM ),
6563 
    .O(\frame_delay_cnt_4_0_0/FFY/SET )
6564 
  );
6565 
  X_FF frame_delay_cnt_4_0_0_94 (
6566 
    .I(frame_delay_cnt_4__n0001[0]),
6567 
    .CE(_n0230),
6568 
    .CLK(\frame_delay_cnt_4_0_0/CKMUXNOT ),
6569 
    .SET(\frame_delay_cnt_4_0_0/FFY/SET ),
6570 
    .RST(\frame_delay_cnt_4_0_0/FFY/RST ),
6571 
    .O(frame_delay_cnt_4_0_0)
6572 
  );
6573 
  X_OR2 \frame_delay_cnt_4_1_0/FFY/RSTOR  (
6574 
    .I0(frame_delay_cnt_4_0_1__n0000),
6575 
    .I1(GSR),
6576 
    .O(\frame_delay_cnt_4_1_0/FFY/RST )
6577 
  );
6578 
  X_BUF \frame_delay_cnt_4_1_0/FFY/SETOR  (
6579 
    .I(\frame_delay_cnt_5_0_1__n0001/GROM ),
6580 
    .O(\frame_delay_cnt_4_1_0/FFY/SET )
6581 
  );
6582 
  X_FF frame_delay_cnt_4_1_0_95 (
6583 
    .I(frame_delay_cnt_4__n0001[1]),
6584 
    .CE(_n0230),
6585 
    .CLK(\frame_delay_cnt_4_1_0/CKMUXNOT ),
6586 
    .SET(\frame_delay_cnt_4_1_0/FFY/SET ),
6587 
    .RST(\frame_delay_cnt_4_1_0/FFY/RST ),
6588 
    .O(frame_delay_cnt_4_1_0)
6589 
  );
6590 
  X_BUF \rx_shift_reg_3<5>/FFX/RSTOR  (
6591 
    .I(GSR),
6592 
    .O(\rx_shift_reg_3<5>/FFX/RST )
6593 
  );
6594 
  X_FF rx_shift_reg_3_5 (
6595 
    .I(rx_shift_reg_3[6]),
6596 
    .CE(VCC),
6597 
    .CLK(\rx_shift_reg_3<5>/CKMUXNOT ),
6598 
    .SET(GND),
6599 
    .RST(\rx_shift_reg_3<5>/FFX/RST ),
6600 
    .O(rx_shift_reg_3[5])
6601 
  );
6602 
  X_BUF \rx_shift_reg_5<5>/FFY/RSTOR  (
6603 
    .I(GSR),
6604 
    .O(\rx_shift_reg_5<5>/FFY/RST )
6605 
  );
6606 
  X_FF rx_shift_reg_5_4 (
6607 
    .I(rx_shift_reg_5[5]),
6608 
    .CE(VCC),
6609 
    .CLK(\rx_shift_reg_5<5>/CKMUXNOT ),
6610 
    .SET(GND),
6611 
    .RST(\rx_shift_reg_5<5>/FFY/RST ),
6612 
    .O(rx_shift_reg_5[4])
6613 
  );
6614 
  X_OR2 \frame_delay_cnt_5_0_0/FFY/RSTOR  (
6615 
    .I0(frame_delay_cnt_5_0_0__n0000),
6616 
    .I1(GSR),
6617 
    .O(\frame_delay_cnt_5_0_0/FFY/RST )
6618 
  );
6619 
  X_BUF \frame_delay_cnt_5_0_0/FFY/SETOR  (
6620 
    .I(\frame_delay_cnt_5_0_1__n0000/GROM ),
6621 
    .O(\frame_delay_cnt_5_0_0/FFY/SET )
6622 
  );
6623 
  X_FF frame_delay_cnt_5_0_0_96 (
6624 
    .I(frame_delay_cnt_5__n0001[0]),
6625 
    .CE(_n0231),
6626 
    .CLK(\frame_delay_cnt_5_0_0/CKMUXNOT ),
6627 
    .SET(\frame_delay_cnt_5_0_0/FFY/SET ),
6628 
    .RST(\frame_delay_cnt_5_0_0/FFY/RST ),
6629 
    .O(frame_delay_cnt_5_0_0)
6630 
  );
6631 
  X_BUF \tx_buf_reg_3<5>/FFX/RSTOR  (
6632 
    .I(GSR),
6633 
    .O(\tx_buf_reg_3<5>/FFX/RST )
6634 
  );
6635 
  X_FF tx_buf_reg_3_5 (
6636 
    .I(data_out_bus[5]),
6637 
    .CE(_n0030),
6638 
    .CLK(clk_in_BUFGP),
6639 
    .SET(GND),
6640 
    .RST(\tx_buf_reg_3<5>/FFX/RST ),
6641 
    .O(tx_buf_reg_3[5])
6642 
  );
6643 
  X_BUF \rx_shift_reg_3<5>/FFY/RSTOR  (
6644 
    .I(GSR),
6645 
    .O(\rx_shift_reg_3<5>/FFY/RST )
6646 
  );
6647 
  X_FF rx_shift_reg_3_4 (
6648 
    .I(rx_shift_reg_3[5]),
6649 
    .CE(VCC),
6650 
    .CLK(\rx_shift_reg_3<5>/CKMUXNOT ),
6651 
    .SET(GND),
6652 
    .RST(\rx_shift_reg_3<5>/FFY/RST ),
6653 
    .O(rx_shift_reg_3[4])
6654 
  );
6655 
  X_OR2 \frame_delay_cnt_7_0_0/FFY/RSTOR  (
6656 
    .I0(frame_delay_cnt_7_0_0__n0000),
6657 
    .I1(GSR),
6658 
    .O(\frame_delay_cnt_7_0_0/FFY/RST )
6659 
  );
6660 
  X_BUF \frame_delay_cnt_7_0_0/FFY/SETOR  (
6661 
    .I(\frame_delay_cnt_7_0_1__n0000/GROM ),
6662 
    .O(\frame_delay_cnt_7_0_0/FFY/SET )
6663 
  );
6664 
  X_FF frame_delay_cnt_7_0_0_97 (
6665 
    .I(frame_delay_cnt_7__n0001[0]),
6666 
    .CE(_n0233),
6667 
    .CLK(\frame_delay_cnt_7_0_0/CKMUXNOT ),
6668 
    .SET(\frame_delay_cnt_7_0_0/FFY/SET ),
6669 
    .RST(\frame_delay_cnt_7_0_0/FFY/RST ),
6670 
    .O(frame_delay_cnt_7_0_0)
6671 
  );
6672 
  X_BUF \rx_shift_reg_4<3>/FFY/RSTOR  (
6673 
    .I(GSR),
6674 
    .O(\rx_shift_reg_4<3>/FFY/RST )
6675 
  );
6676 
  X_FF rx_shift_reg_4_2 (
6677 
    .I(rx_shift_reg_4[3]),
6678 
    .CE(VCC),
6679 
    .CLK(\rx_shift_reg_4<3>/CKMUXNOT ),
6680 
    .SET(GND),
6681 
    .RST(\rx_shift_reg_4<3>/FFY/RST ),
6682 
    .O(rx_shift_reg_4[2])
6683 
  );
6684 
  X_BUF \rx_shift_reg_0<1>/FFX/RSTOR  (
6685 
    .I(GSR),
6686 
    .O(\rx_shift_reg_0<1>/FFX/RST )
6687 
  );
6688 
  X_FF rx_shift_reg_0_1 (
6689 
    .I(rx_shift_reg_0[2]),
6690 
    .CE(VCC),
6691 
    .CLK(\rx_shift_reg_0<1>/CKMUXNOT ),
6692 
    .SET(GND),
6693 
    .RST(\rx_shift_reg_0<1>/FFX/RST ),
6694 
    .O(rx_shift_reg_0[1])
6695 
  );
6696 
  X_BUF \rx_shift_reg_5<1>/FFY/RSTOR  (
6697 
    .I(GSR),
6698 
    .O(\rx_shift_reg_5<1>/FFY/RST )
6699 
  );
6700 
  X_FF rx_shift_reg_5_0 (
6701 
    .I(rx_shift_reg_5[1]),
6702 
    .CE(VCC),
6703 
    .CLK(\rx_shift_reg_5<1>/CKMUXNOT ),
6704 
    .SET(GND),
6705 
    .RST(\rx_shift_reg_5<1>/FFY/RST ),
6706 
    .O(rx_shift_reg_5[0])
6707 
  );
6708 
  X_BUF \rx_shift_reg_1<5>/FFX/RSTOR  (
6709 
    .I(GSR),
6710 
    .O(\rx_shift_reg_1<5>/FFX/RST )
6711 
  );
6712 
  X_FF rx_shift_reg_1_5 (
6713 
    .I(rx_shift_reg_1[6]),
6714 
    .CE(VCC),
6715 
    .CLK(\rx_shift_reg_1<5>/CKMUXNOT ),
6716 
    .SET(GND),
6717 
    .RST(\rx_shift_reg_1<5>/FFX/RST ),
6718 
    .O(rx_shift_reg_1[5])
6719 
  );
6720 
  X_OR2 \div_reg/FFY/RSTOR  (
6721 
    .I0(\div_reg/SRMUX_OUTPUTNOT ),
6722 
    .I1(GSR),
6723 
    .O(\div_reg/FFY/RST )
6724 
  );
6725 
  X_FF div_reg_98 (
6726 
    .I(\div_reg/BYMUXNOT ),
6727 
    .CE(VCC),
6728 
    .CLK(clk_in_BUFGP),
6729 
    .SET(GND),
6730 
    .RST(\div_reg/FFY/RST ),
6731 
    .O(div_reg)
6732 
  );
6733 
  X_BUF \rx_shift_reg_0<1>/FFY/RSTOR  (
6734 
    .I(GSR),
6735 
    .O(\rx_shift_reg_0<1>/FFY/RST )
6736 
  );
6737 
  X_FF rx_shift_reg_0_0 (
6738 
    .I(rx_shift_reg_0[1]),
6739 
    .CE(VCC),
6740 
    .CLK(\rx_shift_reg_0<1>/CKMUXNOT ),
6741 
    .SET(GND),
6742 
    .RST(\rx_shift_reg_0<1>/FFY/RST ),
6743 
    .O(rx_shift_reg_0[0])
6744 
  );
6745 
  X_BUF \rx_shift_reg_1<1>/FFX/RSTOR  (
6746 
    .I(GSR),
6747 
    .O(\rx_shift_reg_1<1>/FFX/RST )
6748 
  );
6749 
  X_FF rx_shift_reg_1_1 (
6750 
    .I(rx_shift_reg_1[2]),
6751 
    .CE(VCC),
6752 
    .CLK(\rx_shift_reg_1<1>/CKMUXNOT ),
6753 
    .SET(GND),
6754 
    .RST(\rx_shift_reg_1<1>/FFX/RST ),
6755 
    .O(rx_shift_reg_1[1])
6756 
  );
6757 
  X_BUF \rx_shift_reg_2<3>/FFX/RSTOR  (
6758 
    .I(GSR),
6759 
    .O(\rx_shift_reg_2<3>/FFX/RST )
6760 
  );
6761 
  X_FF rx_shift_reg_2_3 (
6762 
    .I(rx_shift_reg_2[4]),
6763 
    .CE(VCC),
6764 
    .CLK(\rx_shift_reg_2<3>/CKMUXNOT ),
6765 
    .SET(GND),
6766 
    .RST(\rx_shift_reg_2<3>/FFX/RST ),
6767 
    .O(rx_shift_reg_2[3])
6768 
  );
6769 
  X_BUF \rx_shift_reg_2<3>/FFY/RSTOR  (
6770 
    .I(GSR),
6771 
    .O(\rx_shift_reg_2<3>/FFY/RST )
6772 
  );
6773 
  X_FF rx_shift_reg_2_2 (
6774 
    .I(rx_shift_reg_2[3]),
6775 
    .CE(VCC),
6776 
    .CLK(\rx_shift_reg_2<3>/CKMUXNOT ),
6777 
    .SET(GND),
6778 
    .RST(\rx_shift_reg_2<3>/FFY/RST ),
6779 
    .O(rx_shift_reg_2[2])
6780 
  );
6781 
  X_BUF \rx_shift_reg_0<5>/FFX/RSTOR  (
6782 
    .I(GSR),
6783 
    .O(\rx_shift_reg_0<5>/FFX/RST )
6784 
  );
6785 
  X_FF rx_shift_reg_0_5 (
6786 
    .I(rx_shift_reg_0[6]),
6787 
    .CE(VCC),
6788 
    .CLK(\rx_shift_reg_0<5>/CKMUXNOT ),
6789 
    .SET(GND),
6790 
    .RST(\rx_shift_reg_0<5>/FFX/RST ),
6791 
    .O(rx_shift_reg_0[5])
6792 
  );
6793 
  X_BUF \rx_shift_reg_1<3>/FFX/RSTOR  (
6794 
    .I(GSR),
6795 
    .O(\rx_shift_reg_1<3>/FFX/RST )
6796 
  );
6797 
  X_FF rx_shift_reg_1_3 (
6798 
    .I(rx_shift_reg_1[4]),
6799 
    .CE(VCC),
6800 
    .CLK(\rx_shift_reg_1<3>/CKMUXNOT ),
6801 
    .SET(GND),
6802 
    .RST(\rx_shift_reg_1<3>/FFX/RST ),
6803 
    .O(rx_shift_reg_1[3])
6804 
  );
6805 
  X_BUF \rx_shift_reg_0<3>/FFY/RSTOR  (
6806 
    .I(GSR),
6807 
    .O(\rx_shift_reg_0<3>/FFY/RST )
6808 
  );
6809 
  X_FF rx_shift_reg_0_2 (
6810 
    .I(rx_shift_reg_0[3]),
6811 
    .CE(VCC),
6812 
    .CLK(\rx_shift_reg_0<3>/CKMUXNOT ),
6813 
    .SET(GND),
6814 
    .RST(\rx_shift_reg_0<3>/FFY/RST ),
6815 
    .O(rx_shift_reg_0[2])
6816 
  );
6817 
  X_BUF \rx_shift_reg_0<3>/FFX/RSTOR  (
6818 
    .I(GSR),
6819 
    .O(\rx_shift_reg_0<3>/FFX/RST )
6820 
  );
6821 
  X_FF rx_shift_reg_0_3 (
6822 
    .I(rx_shift_reg_0[4]),
6823 
    .CE(VCC),
6824 
    .CLK(\rx_shift_reg_0<3>/CKMUXNOT ),
6825 
    .SET(GND),
6826 
    .RST(\rx_shift_reg_0<3>/FFX/RST ),
6827 
    .O(rx_shift_reg_0[3])
6828 
  );
6829 
  X_BUF \rx_shift_reg_0<5>/FFY/RSTOR  (
6830 
    .I(GSR),
6831 
    .O(\rx_shift_reg_0<5>/FFY/RST )
6832 
  );
6833 
  X_FF rx_shift_reg_0_4 (
6834 
    .I(rx_shift_reg_0[5]),
6835 
    .CE(VCC),
6836 
    .CLK(\rx_shift_reg_0<5>/CKMUXNOT ),
6837 
    .SET(GND),
6838 
    .RST(\rx_shift_reg_0<5>/FFY/RST ),
6839 
    .O(rx_shift_reg_0[4])
6840 
  );
6841 
  X_BUF \rx_shift_reg_2<1>/FFY/RSTOR  (
6842 
    .I(GSR),
6843 
    .O(\rx_shift_reg_2<1>/FFY/RST )
6844 
  );
6845 
  X_FF rx_shift_reg_2_0 (
6846 
    .I(rx_shift_reg_2[1]),
6847 
    .CE(VCC),
6848 
    .CLK(\rx_shift_reg_2<1>/CKMUXNOT ),
6849 
    .SET(GND),
6850 
    .RST(\rx_shift_reg_2<1>/FFY/RST ),
6851 
    .O(rx_shift_reg_2[0])
6852 
  );
6853 
  X_BUF \rx_shift_reg_4<3>/FFX/RSTOR  (
6854 
    .I(GSR),
6855 
    .O(\rx_shift_reg_4<3>/FFX/RST )
6856 
  );
6857 
  X_FF rx_shift_reg_4_3 (
6858 
    .I(rx_shift_reg_4[4]),
6859 
    .CE(VCC),
6860 
    .CLK(\rx_shift_reg_4<3>/CKMUXNOT ),
6861 
    .SET(GND),
6862 
    .RST(\rx_shift_reg_4<3>/FFX/RST ),
6863 
    .O(rx_shift_reg_4[3])
6864 
  );
6865 
  X_BUF \rx_buf_reg_5<3>/FFY/RSTOR  (
6866 
    .I(GSR),
6867 
    .O(\rx_buf_reg_5<3>/FFY/RST )
6868 
  );
6869 
  X_FF rx_buf_reg_5_2 (
6870 
    .I(rx_shift_reg_5[2]),
6871 
    .CE(\_n00581/O ),
6872 
    .CLK(div_reg),
6873 
    .SET(GND),
6874 
    .RST(\rx_buf_reg_5<3>/FFY/RST ),
6875 
    .O(rx_buf_reg_5[2])
6876 
  );
6877 
  X_BUF \rx_shift_reg_1<1>/FFY/RSTOR  (
6878 
    .I(GSR),
6879 
    .O(\rx_shift_reg_1<1>/FFY/RST )
6880 
  );
6881 
  X_FF rx_shift_reg_1_0 (
6882 
    .I(rx_shift_reg_1[1]),
6883 
    .CE(VCC),
6884 
    .CLK(\rx_shift_reg_1<1>/CKMUXNOT ),
6885 
    .SET(GND),
6886 
    .RST(\rx_shift_reg_1<1>/FFY/RST ),
6887 
    .O(rx_shift_reg_1[0])
6888 
  );
6889 
  X_BUF \rx_shift_reg_1<5>/FFY/RSTOR  (
6890 
    .I(GSR),
6891 
    .O(\rx_shift_reg_1<5>/FFY/RST )
6892 
  );
6893 
  X_FF rx_shift_reg_1_4 (
6894 
    .I(rx_shift_reg_1[5]),
6895 
    .CE(VCC),
6896 
    .CLK(\rx_shift_reg_1<5>/CKMUXNOT ),
6897 
    .SET(GND),
6898 
    .RST(\rx_shift_reg_1<5>/FFY/RST ),
6899 
    .O(rx_shift_reg_1[4])
6900 
  );
6901 
  X_BUF \rx_shift_reg_2<1>/FFX/RSTOR  (
6902 
    .I(GSR),
6903 
    .O(\rx_shift_reg_2<1>/FFX/RST )
6904 
  );
6905 
  X_FF rx_shift_reg_2_1 (
6906 
    .I(rx_shift_reg_2[2]),
6907 
    .CE(VCC),
6908 
    .CLK(\rx_shift_reg_2<1>/CKMUXNOT ),
6909 
    .SET(GND),
6910 
    .RST(\rx_shift_reg_2<1>/FFX/RST ),
6911 
    .O(rx_shift_reg_2[1])
6912 
  );
6913 
  X_BUF \rx_shift_reg_0<6>/FFY/RSTOR  (
6914 
    .I(GSR),
6915 
    .O(\rx_shift_reg_0<6>/FFY/RST )
6916 
  );
6917 
  X_FF rx_shift_reg_0_6 (
6918 
    .I(rx_shift_reg_0[7]),
6919 
    .CE(VCC),
6920 
    .CLK(\rx_shift_reg_0<6>/CKMUXNOT ),
6921 
    .SET(GND),
6922 
    .RST(\rx_shift_reg_0<6>/FFY/RST ),
6923 
    .O(rx_shift_reg_0[6])
6924 
  );
6925 
  X_BUF \rx_shift_reg_1<3>/FFY/RSTOR  (
6926 
    .I(GSR),
6927 
    .O(\rx_shift_reg_1<3>/FFY/RST )
6928 
  );
6929 
  X_FF rx_shift_reg_1_2 (
6930 
    .I(rx_shift_reg_1[3]),
6931 
    .CE(VCC),
6932 
    .CLK(\rx_shift_reg_1<3>/CKMUXNOT ),
6933 
    .SET(GND),
6934 
    .RST(\rx_shift_reg_1<3>/FFY/RST ),
6935 
    .O(rx_shift_reg_1[2])
6936 
  );
6937 
  X_BUF \rx_shift_reg_6<1>/FFY/RSTOR  (
6938 
    .I(GSR),
6939 
    .O(\rx_shift_reg_6<1>/FFY/RST )
6940 
  );
6941 
  X_FF rx_shift_reg_6_0 (
6942 
    .I(rx_shift_reg_6[1]),
6943 
    .CE(VCC),
6944 
    .CLK(\rx_shift_reg_6<1>/CKMUXNOT ),
6945 
    .SET(GND),
6946 
    .RST(\rx_shift_reg_6<1>/FFY/RST ),
6947 
    .O(rx_shift_reg_6[0])
6948 
  );
6949 
  X_BUF \rx_shift_reg_4<1>/FFY/RSTOR  (
6950 
    .I(GSR),
6951 
    .O(\rx_shift_reg_4<1>/FFY/RST )
6952 
  );
6953 
  X_FF rx_shift_reg_4_0 (
6954 
    .I(rx_shift_reg_4[1]),
6955 
    .CE(VCC),
6956 
    .CLK(\rx_shift_reg_4<1>/CKMUXNOT ),
6957 
    .SET(GND),
6958 
    .RST(\rx_shift_reg_4<1>/FFY/RST ),
6959 
    .O(rx_shift_reg_4[0])
6960 
  );
6961 
  X_BUF \rx_shift_reg_1<6>/FFY/RSTOR  (
6962 
    .I(GSR),
6963 
    .O(\rx_shift_reg_1<6>/FFY/RST )
6964 
  );
6965 
  X_FF rx_shift_reg_1_6 (
6966 
    .I(rx_shift_reg_1[7]),
6967 
    .CE(VCC),
6968 
    .CLK(\rx_shift_reg_1<6>/CKMUXNOT ),
6969 
    .SET(GND),
6970 
    .RST(\rx_shift_reg_1<6>/FFY/RST ),
6971 
    .O(rx_shift_reg_1[6])
6972 
  );
6973 
  X_BUF \rx_shift_reg_4<1>/FFX/RSTOR  (
6974 
    .I(GSR),
6975 
    .O(\rx_shift_reg_4<1>/FFX/RST )
6976 
  );
6977 
  X_FF rx_shift_reg_4_1 (
6978 
    .I(rx_shift_reg_4[2]),
6979 
    .CE(VCC),
6980 
    .CLK(\rx_shift_reg_4<1>/CKMUXNOT ),
6981 
    .SET(GND),
6982 
    .RST(\rx_shift_reg_4<1>/FFX/RST ),
6983 
    .O(rx_shift_reg_4[1])
6984 
  );
6985 
  X_BUF \rx_shift_reg_2<5>/FFX/RSTOR  (
6986 
    .I(GSR),
6987 
    .O(\rx_shift_reg_2<5>/FFX/RST )
6988 
  );
6989 
  X_FF rx_shift_reg_2_5 (
6990 
    .I(rx_shift_reg_2[6]),
6991 
    .CE(VCC),
6992 
    .CLK(\rx_shift_reg_2<5>/CKMUXNOT ),
6993 
    .SET(GND),
6994 
    .RST(\rx_shift_reg_2<5>/FFX/RST ),
6995 
    .O(rx_shift_reg_2[5])
6996 
  );
6997 
  X_BUF \rx_shift_reg_6<1>/FFX/RSTOR  (
6998 
    .I(GSR),
6999 
    .O(\rx_shift_reg_6<1>/FFX/RST )
7000 
  );
7001 
  X_FF rx_shift_reg_6_1 (
7002 
    .I(rx_shift_reg_6[2]),
7003 
    .CE(VCC),
7004 
    .CLK(\rx_shift_reg_6<1>/CKMUXNOT ),
7005 
    .SET(GND),
7006 
    .RST(\rx_shift_reg_6<1>/FFX/RST ),
7007 
    .O(rx_shift_reg_6[1])
7008 
  );
7009 
  X_BUF \rx_shift_reg_3<1>/FFX/RSTOR  (
7010 
    .I(GSR),
7011 
    .O(\rx_shift_reg_3<1>/FFX/RST )
7012 
  );
7013 
  X_FF rx_shift_reg_3_1 (
7014 
    .I(rx_shift_reg_3[2]),
7015 
    .CE(VCC),
7016 
    .CLK(\rx_shift_reg_3<1>/CKMUXNOT ),
7017 
    .SET(GND),
7018 
    .RST(\rx_shift_reg_3<1>/FFX/RST ),
7019 
    .O(rx_shift_reg_3[1])
7020 
  );
7021 
  X_BUF \rx_shift_reg_2<5>/FFY/RSTOR  (
7022 
    .I(GSR),
7023 
    .O(\rx_shift_reg_2<5>/FFY/RST )
7024 
  );
7025 
  X_FF rx_shift_reg_2_4 (
7026 
    .I(rx_shift_reg_2[5]),
7027 
    .CE(VCC),
7028 
    .CLK(\rx_shift_reg_2<5>/CKMUXNOT ),
7029 
    .SET(GND),
7030 
    .RST(\rx_shift_reg_2<5>/FFY/RST ),
7031 
    .O(rx_shift_reg_2[4])
7032 
  );
7033 
  X_BUF \rx_shift_reg_3<1>/FFY/RSTOR  (
7034 
    .I(GSR),
7035 
    .O(\rx_shift_reg_3<1>/FFY/RST )
7036 
  );
7037 
  X_FF rx_shift_reg_3_0 (
7038 
    .I(rx_shift_reg_3[1]),
7039 
    .CE(VCC),
7040 
    .CLK(\rx_shift_reg_3<1>/CKMUXNOT ),
7041 
    .SET(GND),
7042 
    .RST(\rx_shift_reg_3<1>/FFY/RST ),
7043 
    .O(rx_shift_reg_3[0])
7044 
  );
7045 
  X_BUF \rx_shift_reg_2<6>/FFY/RSTOR  (
7046 
    .I(GSR),
7047 
    .O(\rx_shift_reg_2<6>/FFY/RST )
7048 
  );
7049 
  X_FF rx_shift_reg_2_6 (
7050 
    .I(rx_shift_reg_2[7]),
7051 
    .CE(VCC),
7052 
    .CLK(\rx_shift_reg_2<6>/CKMUXNOT ),
7053 
    .SET(GND),
7054 
    .RST(\rx_shift_reg_2<6>/FFY/RST ),
7055 
    .O(rx_shift_reg_2[6])
7056 
  );
7057 
  X_BUF \rx_buf_reg_5<3>/FFX/RSTOR  (
7058 
    .I(GSR),
7059 
    .O(\rx_buf_reg_5<3>/FFX/RST )
7060 
  );
7061 
  X_FF rx_buf_reg_5_3 (
7062 
    .I(rx_shift_reg_5[3]),
7063 
    .CE(\_n00581/O ),
7064 
    .CLK(div_reg),
7065 
    .SET(GND),
7066 
    .RST(\rx_buf_reg_5<3>/FFX/RST ),
7067 
    .O(rx_buf_reg_5[3])
7068 
  );
7069 
  X_BUF \tx_buf_reg_4<3>/FFY/RSTOR  (
7070 
    .I(GSR),
7071 
    .O(\tx_buf_reg_4<3>/FFY/RST )
7072 
  );
7073 
  X_FF tx_buf_reg_4_2 (
7074 
    .I(data_out_bus[2]),
7075 
    .CE(\_n00311/O ),
7076 
    .CLK(clk_in_BUFGP),
7077 
    .SET(GND),
7078 
    .RST(\tx_buf_reg_4<3>/FFY/RST ),
7079 
    .O(tx_buf_reg_4[2])
7080 
  );
7081 
  X_BUF \rx_shift_reg_5<3>/FFY/RSTOR  (
7082 
    .I(GSR),
7083 
    .O(\rx_shift_reg_5<3>/FFY/RST )
7084 
  );
7085 
  X_FF rx_shift_reg_5_2 (
7086 
    .I(rx_shift_reg_5[3]),
7087 
    .CE(VCC),
7088 
    .CLK(\rx_shift_reg_5<3>/CKMUXNOT ),
7089 
    .SET(GND),
7090 
    .RST(\rx_shift_reg_5<3>/FFY/RST ),
7091 
    .O(rx_shift_reg_5[2])
7092 
  );
7093 
  X_BUF \rx_shift_reg_5<3>/FFX/RSTOR  (
7094 
    .I(GSR),
7095 
    .O(\rx_shift_reg_5<3>/FFX/RST )
7096 
  );
7097 
  X_FF rx_shift_reg_5_3 (
7098 
    .I(rx_shift_reg_5[4]),
7099 
    .CE(VCC),
7100 
    .CLK(\rx_shift_reg_5<3>/CKMUXNOT ),
7101 
    .SET(GND),
7102 
    .RST(\rx_shift_reg_5<3>/FFX/RST ),
7103 
    .O(rx_shift_reg_5[3])
7104 
  );
7105 
  X_BUF \rx_shift_reg_5<1>/FFX/RSTOR  (
7106 
    .I(GSR),
7107 
    .O(\rx_shift_reg_5<1>/FFX/RST )
7108 
  );
7109 
  X_FF rx_shift_reg_5_1 (
7110 
    .I(rx_shift_reg_5[2]),
7111 
    .CE(VCC),
7112 
    .CLK(\rx_shift_reg_5<1>/CKMUXNOT ),
7113 
    .SET(GND),
7114 
    .RST(\rx_shift_reg_5<1>/FFX/RST ),
7115 
    .O(rx_shift_reg_5[1])
7116 
  );
7117 
  X_BUF \rx_shift_reg_7<1>/FFX/RSTOR  (
7118 
    .I(GSR),
7119 
    .O(\rx_shift_reg_7<1>/FFX/RST )
7120 
  );
7121 
  X_FF rx_shift_reg_7_1 (
7122 
    .I(rx_shift_reg_7[2]),
7123 
    .CE(VCC),
7124 
    .CLK(\rx_shift_reg_7<1>/CKMUXNOT ),
7125 
    .SET(GND),
7126 
    .RST(\rx_shift_reg_7<1>/FFX/RST ),
7127 
    .O(rx_shift_reg_7[1])
7128 
  );
7129 
  X_BUF \rx_shift_reg_5<6>/FFY/RSTOR  (
7130 
    .I(GSR),
7131 
    .O(\rx_shift_reg_5<6>/FFY/RST )
7132 
  );
7133 
  X_FF rx_shift_reg_5_6 (
7134 
    .I(rx_shift_reg_5[7]),
7135 
    .CE(VCC),
7136 
    .CLK(\rx_shift_reg_5<6>/CKMUXNOT ),
7137 
    .SET(GND),
7138 
    .RST(\rx_shift_reg_5<6>/FFY/RST ),
7139 
    .O(rx_shift_reg_5[6])
7140 
  );
7141 
  X_BUF \rx_shift_reg_6<3>/FFX/RSTOR  (
7142 
    .I(GSR),
7143 
    .O(\rx_shift_reg_6<3>/FFX/RST )
7144 
  );
7145 
  X_FF rx_shift_reg_6_3 (
7146 
    .I(rx_shift_reg_6[4]),
7147 
    .CE(VCC),
7148 
    .CLK(\rx_shift_reg_6<3>/CKMUXNOT ),
7149 
    .SET(GND),
7150 
    .RST(\rx_shift_reg_6<3>/FFX/RST ),
7151 
    .O(rx_shift_reg_6[3])
7152 
  );
7153 
  X_BUF \rx_shift_reg_7<3>/FFX/RSTOR  (
7154 
    .I(GSR),
7155 
    .O(\rx_shift_reg_7<3>/FFX/RST )
7156 
  );
7157 
  X_FF rx_shift_reg_7_3 (
7158 
    .I(rx_shift_reg_7[4]),
7159 
    .CE(VCC),
7160 
    .CLK(\rx_shift_reg_7<3>/CKMUXNOT ),
7161 
    .SET(GND),
7162 
    .RST(\rx_shift_reg_7<3>/FFX/RST ),
7163 
    .O(rx_shift_reg_7[3])
7164 
  );
7165 
  X_BUF \rx_shift_reg_7<5>/FFY/RSTOR  (
7166 
    .I(GSR),
7167 
    .O(\rx_shift_reg_7<5>/FFY/RST )
7168 
  );
7169 
  X_FF rx_shift_reg_7_4 (
7170 
    .I(rx_shift_reg_7[5]),
7171 
    .CE(VCC),
7172 
    .CLK(\rx_shift_reg_7<5>/CKMUXNOT ),
7173 
    .SET(GND),
7174 
    .RST(\rx_shift_reg_7<5>/FFY/RST ),
7175 
    .O(rx_shift_reg_7[4])
7176 
  );
7177 
  X_BUF \rx_shift_reg_6<3>/FFY/RSTOR  (
7178 
    .I(GSR),
7179 
    .O(\rx_shift_reg_6<3>/FFY/RST )
7180 
  );
7181 
  X_FF rx_shift_reg_6_2 (
7182 
    .I(rx_shift_reg_6[3]),
7183 
    .CE(VCC),
7184 
    .CLK(\rx_shift_reg_6<3>/CKMUXNOT ),
7185 
    .SET(GND),
7186 
    .RST(\rx_shift_reg_6<3>/FFY/RST ),
7187 
    .O(rx_shift_reg_6[2])
7188 
  );
7189 
  X_BUF \rx_shift_reg_6<5>/FFX/RSTOR  (
7190 
    .I(GSR),
7191 
    .O(\rx_shift_reg_6<5>/FFX/RST )
7192 
  );
7193 
  X_FF rx_shift_reg_6_5 (
7194 
    .I(rx_shift_reg_6[6]),
7195 
    .CE(VCC),
7196 
    .CLK(\rx_shift_reg_6<5>/CKMUXNOT ),
7197 
    .SET(GND),
7198 
    .RST(\rx_shift_reg_6<5>/FFX/RST ),
7199 
    .O(rx_shift_reg_6[5])
7200 
  );
7201 
  X_BUF \rx_shift_reg_7<3>/FFY/RSTOR  (
7202 
    .I(GSR),
7203 
    .O(\rx_shift_reg_7<3>/FFY/RST )
7204 
  );
7205 
  X_FF rx_shift_reg_7_2 (
7206 
    .I(rx_shift_reg_7[3]),
7207 
    .CE(VCC),
7208 
    .CLK(\rx_shift_reg_7<3>/CKMUXNOT ),
7209 
    .SET(GND),
7210 
    .RST(\rx_shift_reg_7<3>/FFY/RST ),
7211 
    .O(rx_shift_reg_7[2])
7212 
  );
7213 
  X_BUF \rx_shift_reg_7<1>/FFY/RSTOR  (
7214 
    .I(GSR),
7215 
    .O(\rx_shift_reg_7<1>/FFY/RST )
7216 
  );
7217 
  X_FF rx_shift_reg_7_0 (
7218 
    .I(rx_shift_reg_7[1]),
7219 
    .CE(VCC),
7220 
    .CLK(\rx_shift_reg_7<1>/CKMUXNOT ),
7221 
    .SET(GND),
7222 
    .RST(\rx_shift_reg_7<1>/FFY/RST ),
7223 
    .O(rx_shift_reg_7[0])
7224 
  );
7225 
  X_BUF \rx_shift_reg_7<5>/FFX/RSTOR  (
7226 
    .I(GSR),
7227 
    .O(\rx_shift_reg_7<5>/FFX/RST )
7228 
  );
7229 
  X_FF rx_shift_reg_7_5 (
7230 
    .I(rx_shift_reg_7[6]),
7231 
    .CE(VCC),
7232 
    .CLK(\rx_shift_reg_7<5>/CKMUXNOT ),
7233 
    .SET(GND),
7234 
    .RST(\rx_shift_reg_7<5>/FFX/RST ),
7235 
    .O(rx_shift_reg_7[5])
7236 
  );
7237 
  X_BUF \rx_shift_reg_6<6>/FFY/RSTOR  (
7238 
    .I(GSR),
7239 
    .O(\rx_shift_reg_6<6>/FFY/RST )
7240 
  );
7241 
  X_FF rx_shift_reg_6_6 (
7242 
    .I(rx_shift_reg_6[7]),
7243 
    .CE(VCC),
7244 
    .CLK(\rx_shift_reg_6<6>/CKMUXNOT ),
7245 
    .SET(GND),
7246 
    .RST(\rx_shift_reg_6<6>/FFY/RST ),
7247 
    .O(rx_shift_reg_6[6])
7248 
  );
7249 
  X_BUF \rx_shift_reg_6<5>/FFY/RSTOR  (
7250 
    .I(GSR),
7251 
    .O(\rx_shift_reg_6<5>/FFY/RST )
7252 
  );
7253 
  X_FF rx_shift_reg_6_4 (
7254 
    .I(rx_shift_reg_6[5]),
7255 
    .CE(VCC),
7256 
    .CLK(\rx_shift_reg_6<5>/CKMUXNOT ),
7257 
    .SET(GND),
7258 
    .RST(\rx_shift_reg_6<5>/FFY/RST ),
7259 
    .O(rx_shift_reg_6[4])
7260 
  );
7261 
  X_BUF \rx_buf_reg_1<5>/FFY/RSTOR  (
7262 
    .I(GSR),
7263 
    .O(\rx_buf_reg_1<5>/FFY/RST )
7264 
  );
7265 
  X_FF rx_buf_reg_1_4 (
7266 
    .I(rx_shift_reg_1[4]),
7267 
    .CE(\_n00621/O ),
7268 
    .CLK(div_reg),
7269 
    .SET(GND),
7270 
    .RST(\rx_buf_reg_1<5>/FFY/RST ),
7271 
    .O(rx_buf_reg_1[4])
7272 
  );
7273 
  X_OR2 \div_reg_2/FFY/RSTOR  (
7274 
    .I0(\div_reg_2/SRMUX_OUTPUTNOT ),
7275 
    .I1(GSR),
7276 
    .O(\div_reg_2/FFY/RST )
7277 
  );
7278 
  X_FF div_reg_1_99 (
7279 
    .I(\div_reg_2/BYMUXNOT ),
7280 
    .CE(VCC),
7281 
    .CLK(clk_in_BUFGP),
7282 
    .SET(GND),
7283 
    .RST(\div_reg_2/FFY/RST ),
7284 
    .O(div_reg_1)
7285 
  );
7286 
  X_OR2 \div_reg_2/FFX/RSTOR  (
7287 
    .I0(\div_reg_2/SRMUX_OUTPUTNOT ),
7288 
    .I1(GSR),
7289 
    .O(\div_reg_2/FFX/RST )
7290 
  );
7291 
  X_FF div_reg_2_100 (
7292 
    .I(\div_reg_2/BXMUXNOT ),
7293 
    .CE(VCC),
7294 
    .CLK(clk_in_BUFGP),
7295 
    .SET(GND),
7296 
    .RST(\div_reg_2/FFX/RST ),
7297 
    .O(div_reg_2)
7298 
  );
7299 
  X_BUF \rx_shift_reg_7<6>/FFY/RSTOR  (
7300 
    .I(GSR),
7301 
    .O(\rx_shift_reg_7<6>/FFY/RST )
7302 
  );
7303 
  X_FF rx_shift_reg_7_6 (
7304 
    .I(rx_shift_reg_7[7]),
7305 
    .CE(VCC),
7306 
    .CLK(\rx_shift_reg_7<6>/CKMUXNOT ),
7307 
    .SET(GND),
7308 
    .RST(\rx_shift_reg_7<6>/FFY/RST ),
7309 
    .O(rx_shift_reg_7[6])
7310 
  );
7311 
  X_BUF \tx_buf_reg_5<7>/FFX/RSTOR  (
7312 
    .I(GSR),
7313 
    .O(\tx_buf_reg_5<7>/FFX/RST )
7314 
  );
7315 
  X_FF tx_buf_reg_5_7 (
7316 
    .I(data_out_bus[7]),
7317 
    .CE(\_n00321/O ),
7318 
    .CLK(clk_in_BUFGP),
7319 
    .SET(GND),
7320 
    .RST(\tx_buf_reg_5<7>/FFX/RST ),
7321 
    .O(tx_buf_reg_5[7])
7322 
  );
7323 
  X_BUF \rx_buf_reg_0<3>/FFY/RSTOR  (
7324 
    .I(GSR),
7325 
    .O(\rx_buf_reg_0<3>/FFY/RST )
7326 
  );
7327 
  X_FF rx_buf_reg_0_2 (
7328 
    .I(rx_shift_reg_0[2]),
7329 
    .CE(\_n00631/O ),
7330 
    .CLK(div_reg),
7331 
    .SET(GND),
7332 
    .RST(\rx_buf_reg_0<3>/FFY/RST ),
7333 
    .O(rx_buf_reg_0[2])
7334 
  );
7335 
  X_BUF \rx_buf_reg_1<3>/FFX/RSTOR  (
7336 
    .I(GSR),
7337 
    .O(\rx_buf_reg_1<3>/FFX/RST )
7338 
  );
7339 
  X_FF rx_buf_reg_1_3 (
7340 
    .I(rx_shift_reg_1[3]),
7341 
    .CE(\_n00621/O ),
7342 
    .CLK(div_reg),
7343 
    .SET(GND),
7344 
    .RST(\rx_buf_reg_1<3>/FFX/RST ),
7345 
    .O(rx_buf_reg_1[3])
7346 
  );
7347 
  X_BUF \rx_buf_reg_2<3>/FFY/RSTOR  (
7348 
    .I(GSR),
7349 
    .O(\rx_buf_reg_2<3>/FFY/RST )
7350 
  );
7351 
  X_FF rx_buf_reg_2_2 (
7352 
    .I(rx_shift_reg_2[2]),
7353 
    .CE(\_n00611/O ),
7354 
    .CLK(div_reg),
7355 
    .SET(GND),
7356 
    .RST(\rx_buf_reg_2<3>/FFY/RST ),
7357 
    .O(rx_buf_reg_2[2])
7358 
  );
7359 
  X_BUF \rx_buf_reg_2<3>/FFX/RSTOR  (
7360 
    .I(GSR),
7361 
    .O(\rx_buf_reg_2<3>/FFX/RST )
7362 
  );
7363 
  X_FF rx_buf_reg_2_3 (
7364 
    .I(rx_shift_reg_2[3]),
7365 
    .CE(\_n00611/O ),
7366 
    .CLK(div_reg),
7367 
    .SET(GND),
7368 
    .RST(\rx_buf_reg_2<3>/FFX/RST ),
7369 
    .O(rx_buf_reg_2[3])
7370 
  );
7371 
  X_BUF \rx_buf_reg_0<5>/FFY/RSTOR  (
7372 
    .I(GSR),
7373 
    .O(\rx_buf_reg_0<5>/FFY/RST )
7374 
  );
7375 
  X_FF rx_buf_reg_0_4 (
7376 
    .I(rx_shift_reg_0[4]),
7377 
    .CE(\_n00631/O ),
7378 
    .CLK(div_reg),
7379 
    .SET(GND),
7380 
    .RST(\rx_buf_reg_0<5>/FFY/RST ),
7381 
    .O(rx_buf_reg_0[4])
7382 
  );
7383 
  X_BUF \rx_buf_reg_5<5>/FFY/RSTOR  (
7384 
    .I(GSR),
7385 
    .O(\rx_buf_reg_5<5>/FFY/RST )
7386 
  );
7387 
  X_FF rx_buf_reg_5_4 (
7388 
    .I(rx_shift_reg_5[4]),
7389 
    .CE(\_n00581/O ),
7390 
    .CLK(div_reg),
7391 
    .SET(GND),
7392 
    .RST(\rx_buf_reg_5<5>/FFY/RST ),
7393 
    .O(rx_buf_reg_5[4])
7394 
  );
7395 
  X_BUF \rx_buf_reg_1<7>/FFX/RSTOR  (
7396 
    .I(GSR),
7397 
    .O(\rx_buf_reg_1<7>/FFX/RST )
7398 
  );
7399 
  X_FF rx_buf_reg_1_7 (
7400 
    .I(rx_shift_reg_1[7]),
7401 
    .CE(\_n00621/O ),
7402 
    .CLK(div_reg),
7403 
    .SET(GND),
7404 
    .RST(\rx_buf_reg_1<7>/FFX/RST ),
7405 
    .O(rx_buf_reg_1[7])
7406 
  );
7407 
  X_BUF \rx_buf_reg_4<7>/FFX/RSTOR  (
7408 
    .I(GSR),
7409 
    .O(\rx_buf_reg_4<7>/FFX/RST )
7410 
  );
7411 
  X_FF rx_buf_reg_4_7 (
7412 
    .I(rx_shift_reg_4[7]),
7413 
    .CE(\_n00591/O ),
7414 
    .CLK(div_reg),
7415 
    .SET(GND),
7416 
    .RST(\rx_buf_reg_4<7>/FFX/RST ),
7417 
    .O(rx_buf_reg_4[7])
7418 
  );
7419 
  X_BUF \rx_buf_reg_1<7>/FFY/RSTOR  (
7420 
    .I(GSR),
7421 
    .O(\rx_buf_reg_1<7>/FFY/RST )
7422 
  );
7423 
  X_FF rx_buf_reg_1_6 (
7424 
    .I(rx_shift_reg_1[6]),
7425 
    .CE(\_n00621/O ),
7426 
    .CLK(div_reg),
7427 
    .SET(GND),
7428 
    .RST(\rx_buf_reg_1<7>/FFY/RST ),
7429 
    .O(rx_buf_reg_1[6])
7430 
  );
7431 
  X_BUF \rx_buf_reg_4<7>/FFY/RSTOR  (
7432 
    .I(GSR),
7433 
    .O(\rx_buf_reg_4<7>/FFY/RST )
7434 
  );
7435 
  X_FF rx_buf_reg_4_6 (
7436 
    .I(rx_shift_reg_4[6]),
7437 
    .CE(\_n00591/O ),
7438 
    .CLK(div_reg),
7439 
    .SET(GND),
7440 
    .RST(\rx_buf_reg_4<7>/FFY/RST ),
7441 
    .O(rx_buf_reg_4[6])
7442 
  );
7443 
  X_BUF \rx_buf_reg_1<5>/FFX/RSTOR  (
7444 
    .I(GSR),
7445 
    .O(\rx_buf_reg_1<5>/FFX/RST )
7446 
  );
7447 
  X_FF rx_buf_reg_1_5 (
7448 
    .I(rx_shift_reg_1[5]),
7449 
    .CE(\_n00621/O ),
7450 
    .CLK(div_reg),
7451 
    .SET(GND),
7452 
    .RST(\rx_buf_reg_1<5>/FFX/RST ),
7453 
    .O(rx_buf_reg_1[5])
7454 
  );
7455 
  X_BUF \rx_buf_reg_0<3>/FFX/RSTOR  (
7456 
    .I(GSR),
7457 
    .O(\rx_buf_reg_0<3>/FFX/RST )
7458 
  );
7459 
  X_FF rx_buf_reg_0_3 (
7460 
    .I(rx_shift_reg_0[3]),
7461 
    .CE(\_n00631/O ),
7462 
    .CLK(div_reg),
7463 
    .SET(GND),
7464 
    .RST(\rx_buf_reg_0<3>/FFX/RST ),
7465 
    .O(rx_buf_reg_0[3])
7466 
  );
7467 
  X_BUF \tx_buf_reg_5<5>/FFX/RSTOR  (
7468 
    .I(GSR),
7469 
    .O(\tx_buf_reg_5<5>/FFX/RST )
7470 
  );
7471 
  X_FF tx_buf_reg_5_5 (
7472 
    .I(data_out_bus[5]),
7473 
    .CE(\_n00321/O ),
7474 
    .CLK(clk_in_BUFGP),
7475 
    .SET(GND),
7476 
    .RST(\tx_buf_reg_5<5>/FFX/RST ),
7477 
    .O(tx_buf_reg_5[5])
7478 
  );
7479 
  X_BUF \rx_buf_reg_0<5>/FFX/RSTOR  (
7480 
    .I(GSR),
7481 
    .O(\rx_buf_reg_0<5>/FFX/RST )
7482 
  );
7483 
  X_FF rx_buf_reg_0_5 (
7484 
    .I(rx_shift_reg_0[5]),
7485 
    .CE(\_n00631/O ),
7486 
    .CLK(div_reg),
7487 
    .SET(GND),
7488 
    .RST(\rx_buf_reg_0<5>/FFX/RST ),
7489 
    .O(rx_buf_reg_0[5])
7490 
  );
7491 
  X_BUF \rx_buf_reg_0<7>/FFX/RSTOR  (
7492 
    .I(GSR),
7493 
    .O(\rx_buf_reg_0<7>/FFX/RST )
7494 
  );
7495 
  X_FF rx_buf_reg_0_7 (
7496 
    .I(rx_shift_reg_0[7]),
7497 
    .CE(\_n00631/O ),
7498 
    .CLK(div_reg),
7499 
    .SET(GND),
7500 
    .RST(\rx_buf_reg_0<7>/FFX/RST ),
7501 
    .O(rx_buf_reg_0[7])
7502 
  );
7503 
  X_BUF \rx_buf_reg_0<7>/FFY/RSTOR  (
7504 
    .I(GSR),
7505 
    .O(\rx_buf_reg_0<7>/FFY/RST )
7506 
  );
7507 
  X_FF rx_buf_reg_0_6 (
7508 
    .I(rx_shift_reg_0[6]),
7509 
    .CE(\_n00631/O ),
7510 
    .CLK(div_reg),
7511 
    .SET(GND),
7512 
    .RST(\rx_buf_reg_0<7>/FFY/RST ),
7513 
    .O(rx_buf_reg_0[6])
7514 
  );
7515 
  X_BUF \rx_buf_reg_3<5>/FFX/RSTOR  (
7516 
    .I(GSR),
7517 
    .O(\rx_buf_reg_3<5>/FFX/RST )
7518 
  );
7519 
  X_FF rx_buf_reg_3_5 (
7520 
    .I(rx_shift_reg_3[5]),
7521 
    .CE(\_n00601/O ),
7522 
    .CLK(div_reg),
7523 
    .SET(GND),
7524 
    .RST(\rx_buf_reg_3<5>/FFX/RST ),
7525 
    .O(rx_buf_reg_3[5])
7526 
  );
7527 
  X_BUF \rx_buf_reg_1<3>/FFY/RSTOR  (
7528 
    .I(GSR),
7529 
    .O(\rx_buf_reg_1<3>/FFY/RST )
7530 
  );
7531 
  X_FF rx_buf_reg_1_2 (
7532 
    .I(rx_shift_reg_1[2]),
7533 
    .CE(\_n00621/O ),
7534 
    .CLK(div_reg),
7535 
    .SET(GND),
7536 
    .RST(\rx_buf_reg_1<3>/FFY/RST ),
7537 
    .O(rx_buf_reg_1[2])
7538 
  );
7539 
  X_BUF \rx_buf_reg_2<7>/FFY/RSTOR  (
7540 
    .I(GSR),
7541 
    .O(\rx_buf_reg_2<7>/FFY/RST )
7542 
  );
7543 
  X_FF rx_buf_reg_2_6 (
7544 
    .I(rx_shift_reg_2[6]),
7545 
    .CE(\_n00611/O ),
7546 
    .CLK(div_reg),
7547 
    .SET(GND),
7548 
    .RST(\rx_buf_reg_2<7>/FFY/RST ),
7549 
    .O(rx_buf_reg_2[6])
7550 
  );
7551 
  X_BUF \tx_buf_reg_4<7>/FFX/RSTOR  (
7552 
    .I(GSR),
7553 
    .O(\tx_buf_reg_4<7>/FFX/RST )
7554 
  );
7555 
  X_FF tx_buf_reg_4_7 (
7556 
    .I(data_out_bus[7]),
7557 
    .CE(\_n00311/O ),
7558 
    .CLK(clk_in_BUFGP),
7559 
    .SET(GND),
7560 
    .RST(\tx_buf_reg_4<7>/FFX/RST ),
7561 
    .O(tx_buf_reg_4[7])
7562 
  );
7563 
  X_BUF \tx_buf_reg_5<7>/FFY/RSTOR  (
7564 
    .I(GSR),
7565 
    .O(\tx_buf_reg_5<7>/FFY/RST )
7566 
  );
7567 
  X_FF tx_buf_reg_5_6 (
7568 
    .I(data_out_bus[6]),
7569 
    .CE(\_n00321/O ),
7570 
    .CLK(clk_in_BUFGP),
7571 
    .SET(GND),
7572 
    .RST(\tx_buf_reg_5<7>/FFY/RST ),
7573 
    .O(tx_buf_reg_5[6])
7574 
  );
7575 
  X_BUF \rx_buf_reg_2<7>/FFX/RSTOR  (
7576 
    .I(GSR),
7577 
    .O(\rx_buf_reg_2<7>/FFX/RST )
7578 
  );
7579 
  X_FF rx_buf_reg_2_7 (
7580 
    .I(rx_shift_reg_2[7]),
7581 
    .CE(\_n00611/O ),
7582 
    .CLK(div_reg),
7583 
    .SET(GND),
7584 
    .RST(\rx_buf_reg_2<7>/FFX/RST ),
7585 
    .O(rx_buf_reg_2[7])
7586 
  );
7587 
  X_BUF \rx_buf_reg_3<5>/FFY/RSTOR  (
7588 
    .I(GSR),
7589 
    .O(\rx_buf_reg_3<5>/FFY/RST )
7590 
  );
7591 
  X_FF rx_buf_reg_3_4 (
7592 
    .I(rx_shift_reg_3[4]),
7593 
    .CE(\_n00601/O ),
7594 
    .CLK(div_reg),
7595 
    .SET(GND),
7596 
    .RST(\rx_buf_reg_3<5>/FFY/RST ),
7597 
    .O(rx_buf_reg_3[4])
7598 
  );
7599 
  X_BUF \tx_buf_reg_5<5>/FFY/RSTOR  (
7600 
    .I(GSR),
7601 
    .O(\tx_buf_reg_5<5>/FFY/RST )
7602 
  );
7603 
  X_FF tx_buf_reg_5_4 (
7604 
    .I(data_out_bus[4]),
7605 
    .CE(\_n00321/O ),
7606 
    .CLK(clk_in_BUFGP),
7607 
    .SET(GND),
7608 
    .RST(\tx_buf_reg_5<5>/FFY/RST ),
7609 
    .O(tx_buf_reg_5[4])
7610 
  );
7611 
  X_BUF \rx_buf_reg_4<3>/FFY/RSTOR  (
7612 
    .I(GSR),
7613 
    .O(\rx_buf_reg_4<3>/FFY/RST )
7614 
  );
7615 
  X_FF rx_buf_reg_4_2 (
7616 
    .I(rx_shift_reg_4[2]),
7617 
    .CE(\_n00591/O ),
7618 
    .CLK(div_reg),
7619 
    .SET(GND),
7620 
    .RST(\rx_buf_reg_4<3>/FFY/RST ),
7621 
    .O(rx_buf_reg_4[2])
7622 
  );
7623 
  X_BUF \rx_buf_reg_4<3>/FFX/RSTOR  (
7624 
    .I(GSR),
7625 
    .O(\rx_buf_reg_4<3>/FFX/RST )
7626 
  );
7627 
  X_FF rx_buf_reg_4_3 (
7628 
    .I(rx_shift_reg_4[3]),
7629 
    .CE(\_n00591/O ),
7630 
    .CLK(div_reg),
7631 
    .SET(GND),
7632 
    .RST(\rx_buf_reg_4<3>/FFX/RST ),
7633 
    .O(rx_buf_reg_4[3])
7634 
  );
7635 
  X_BUF \tx_buf_reg_4<7>/FFY/RSTOR  (
7636 
    .I(GSR),
7637 
    .O(\tx_buf_reg_4<7>/FFY/RST )
7638 
  );
7639 
  X_FF tx_buf_reg_4_6 (
7640 
    .I(data_out_bus[6]),
7641 
    .CE(\_n00311/O ),
7642 
    .CLK(clk_in_BUFGP),
7643 
    .SET(GND),
7644 
    .RST(\tx_buf_reg_4<7>/FFY/RST ),
7645 
    .O(tx_buf_reg_4[6])
7646 
  );
7647 
  X_BUF \rx_buf_reg_5<5>/FFX/RSTOR  (
7648 
    .I(GSR),
7649 
    .O(\rx_buf_reg_5<5>/FFX/RST )
7650 
  );
7651 
  X_FF rx_buf_reg_5_5 (
7652 
    .I(rx_shift_reg_5[5]),
7653 
    .CE(\_n00581/O ),
7654 
    .CLK(div_reg),
7655 
    .SET(GND),
7656 
    .RST(\rx_buf_reg_5<5>/FFX/RST ),
7657 
    .O(rx_buf_reg_5[5])
7658 
  );
7659 
  X_BUF \rx_buf_reg_7<7>/FFX/RSTOR  (
7660 
    .I(GSR),
7661 
    .O(\rx_buf_reg_7<7>/FFX/RST )
7662 
  );
7663 
  X_FF rx_buf_reg_7_7 (
7664 
    .I(rx_shift_reg_7[7]),
7665 
    .CE(\_n00561/O ),
7666 
    .CLK(div_reg_2),
7667 
    .SET(GND),
7668 
    .RST(\rx_buf_reg_7<7>/FFX/RST ),
7669 
    .O(rx_buf_reg_7[7])
7670 
  );
7671 
  X_BUF \tx_buf_reg_1<7>/FFX/RSTOR  (
7672 
    .I(GSR),
7673 
    .O(\tx_buf_reg_1<7>/FFX/RST )
7674 
  );
7675 
  X_FF tx_buf_reg_1_7 (
7676 
    .I(data_out_bus[7]),
7677 
    .CE(_n0028),
7678 
    .CLK(clk_in_BUFGP),
7679 
    .SET(GND),
7680 
    .RST(\tx_buf_reg_1<7>/FFX/RST ),
7681 
    .O(tx_buf_reg_1[7])
7682 
  );
7683 
  X_BUF \rx_buf_reg_5<7>/FFY/RSTOR  (
7684 
    .I(GSR),
7685 
    .O(\rx_buf_reg_5<7>/FFY/RST )
7686 
  );
7687 
  X_FF rx_buf_reg_5_6 (
7688 
    .I(rx_shift_reg_5[6]),
7689 
    .CE(\_n00581/O ),
7690 
    .CLK(div_reg),
7691 
    .SET(GND),
7692 
    .RST(\rx_buf_reg_5<7>/FFY/RST ),
7693 
    .O(rx_buf_reg_5[6])
7694 
  );
7695 
  X_OR2 \frame_cnt_1_1/FFY/RSTOR  (
7696 
    .I0(\frame_cnt_1_1/SRMUX_OUTPUTNOT ),
7697 
    .I1(GSR),
7698 
    .O(\frame_cnt_1_1/FFY/RST )
7699 
  );
7700 
  X_FF frame_cnt_1_1_101 (
7701 
    .I(frame_cnt__n0000[1]),
7702 
    .CE(VCC),
7703 
    .CLK(\frame_cnt_1_1/CKMUXNOT ),
7704 
    .SET(GND),
7705 
    .RST(\frame_cnt_1_1/FFY/RST ),
7706 
    .O(frame_cnt_1_1)
7707 
  );
7708 
  X_BUF \rx_buf_reg_5<7>/FFX/RSTOR  (
7709 
    .I(GSR),
7710 
    .O(\rx_buf_reg_5<7>/FFX/RST )
7711 
  );
7712 
  X_FF rx_buf_reg_5_7 (
7713 
    .I(rx_shift_reg_5[7]),
7714 
    .CE(\_n00581/O ),
7715 
    .CLK(div_reg),
7716 
    .SET(GND),
7717 
    .RST(\rx_buf_reg_5<7>/FFX/RST ),
7718 
    .O(rx_buf_reg_5[7])
7719 
  );
7720 
  X_BUF \rx_buf_reg_6<3>/FFX/RSTOR  (
7721 
    .I(GSR),
7722 
    .O(\rx_buf_reg_6<3>/FFX/RST )
7723 
  );
7724 
  X_FF rx_buf_reg_6_3 (
7725 
    .I(rx_shift_reg_6[3]),
7726 
    .CE(\_n00571/O ),
7727 
    .CLK(div_reg),
7728 
    .SET(GND),
7729 
    .RST(\rx_buf_reg_6<3>/FFX/RST ),
7730 
    .O(rx_buf_reg_6[3])
7731 
  );
7732 
  X_BUF \rx_buf_reg_6<7>/FFY/RSTOR  (
7733 
    .I(GSR),
7734 
    .O(\rx_buf_reg_6<7>/FFY/RST )
7735 
  );
7736 
  X_FF rx_buf_reg_6_7 (
7737 
    .I(rx_shift_reg_6[7]),
7738 
    .CE(\_n00571/O ),
7739 
    .CLK(div_reg_2),
7740 
    .SET(GND),
7741 
    .RST(\rx_buf_reg_6<7>/FFY/RST ),
7742 
    .O(rx_buf_reg_6[7])
7743 
  );
7744 
  X_BUF \rx_buf_reg_7<3>/FFX/RSTOR  (
7745 
    .I(GSR),
7746 
    .O(\rx_buf_reg_7<3>/FFX/RST )
7747 
  );
7748 
  X_FF rx_buf_reg_7_3 (
7749 
    .I(rx_shift_reg_7[3]),
7750 
    .CE(\_n00561/O ),
7751 
    .CLK(div_reg_2),
7752 
    .SET(GND),
7753 
    .RST(\rx_buf_reg_7<3>/FFX/RST ),
7754 
    .O(rx_buf_reg_7[3])
7755 
  );
7756 
  X_BUF \rx_buf_reg_6<3>/FFY/RSTOR  (
7757 
    .I(GSR),
7758 
    .O(\rx_buf_reg_6<3>/FFY/RST )
7759 
  );
7760 
  X_FF rx_buf_reg_6_2 (
7761 
    .I(rx_shift_reg_6[2]),
7762 
    .CE(\_n00571/O ),
7763 
    .CLK(div_reg),
7764 
    .SET(GND),
7765 
    .RST(\rx_buf_reg_6<3>/FFY/RST ),
7766 
    .O(rx_buf_reg_6[2])
7767 
  );
7768 
  X_BUF \rx_buf_reg_6<5>/FFX/RSTOR  (
7769 
    .I(GSR),
7770 
    .O(\rx_buf_reg_6<5>/FFX/RST )
7771 
  );
7772 
  X_FF rx_buf_reg_6_5 (
7773 
    .I(rx_shift_reg_6[5]),
7774 
    .CE(\_n00571/O ),
7775 
    .CLK(div_reg),
7776 
    .SET(GND),
7777 
    .RST(\rx_buf_reg_6<5>/FFX/RST ),
7778 
    .O(rx_buf_reg_6[5])
7779 
  );
7780 
  X_BUF \tx_buf_reg_0<5>/FFY/RSTOR  (
7781 
    .I(GSR),
7782 
    .O(\tx_buf_reg_0<5>/FFY/RST )
7783 
  );
7784 
  X_FF tx_buf_reg_0_4 (
7785 
    .I(data_out_bus[4]),
7786 
    .CE(_n0027),
7787 
    .CLK(clk_in_BUFGP),
7788 
    .SET(GND),
7789 
    .RST(\tx_buf_reg_0<5>/FFY/RST ),
7790 
    .O(tx_buf_reg_0[4])
7791 
  );
7792 
  X_BUF \rx_buf_reg_7<3>/FFY/RSTOR  (
7793 
    .I(GSR),
7794 
    .O(\rx_buf_reg_7<3>/FFY/RST )
7795 
  );
7796 
  X_FF rx_buf_reg_7_2 (
7797 
    .I(rx_shift_reg_7[2]),
7798 
    .CE(\_n00561/O ),
7799 
    .CLK(div_reg_2),
7800 
    .SET(GND),
7801 
    .RST(\rx_buf_reg_7<3>/FFY/RST ),
7802 
    .O(rx_buf_reg_7[2])
7803 
  );
7804 
  X_BUF \rx_buf_reg_7<7>/FFY/RSTOR  (
7805 
    .I(GSR),
7806 
    .O(\rx_buf_reg_7<7>/FFY/RST )
7807 
  );
7808 
  X_FF rx_buf_reg_7_6 (
7809 
    .I(rx_shift_reg_7[6]),
7810 
    .CE(\_n00561/O ),
7811 
    .CLK(div_reg_2),
7812 
    .SET(GND),
7813 
    .RST(\rx_buf_reg_7<7>/FFY/RST ),
7814 
    .O(rx_buf_reg_7[6])
7815 
  );
7816 
  X_BUF \rx_buf_reg_7<5>/FFY/RSTOR  (
7817 
    .I(GSR),
7818 
    .O(\rx_buf_reg_7<5>/FFY/RST )
7819 
  );
7820 
  X_FF rx_buf_reg_7_4 (
7821 
    .I(rx_shift_reg_7[4]),
7822 
    .CE(\_n00561/O ),
7823 
    .CLK(div_reg_2),
7824 
    .SET(GND),
7825 
    .RST(\rx_buf_reg_7<5>/FFY/RST ),
7826 
    .O(rx_buf_reg_7[4])
7827 
  );
7828 
  X_BUF \rx_buf_reg_7<5>/FFX/RSTOR  (
7829 
    .I(GSR),
7830 
    .O(\rx_buf_reg_7<5>/FFX/RST )
7831 
  );
7832 
  X_FF rx_buf_reg_7_5 (
7833 
    .I(rx_shift_reg_7[5]),
7834 
    .CE(\_n00561/O ),
7835 
    .CLK(div_reg_2),
7836 
    .SET(GND),
7837 
    .RST(\rx_buf_reg_7<5>/FFX/RST ),
7838 
    .O(rx_buf_reg_7[5])
7839 
  );
7840 
  X_BUF \rx_buf_reg_6<5>/FFY/RSTOR  (
7841 
    .I(GSR),
7842 
    .O(\rx_buf_reg_6<5>/FFY/RST )
7843 
  );
7844 
  X_FF rx_buf_reg_6_4 (
7845 
    .I(rx_shift_reg_6[4]),
7846 
    .CE(\_n00571/O ),
7847 
    .CLK(div_reg),
7848 
    .SET(GND),
7849 
    .RST(\rx_buf_reg_6<5>/FFY/RST ),
7850 
    .O(rx_buf_reg_6[4])
7851 
  );
7852 
  X_BUF \rx_buf_reg_6<6>/FFY/RSTOR  (
7853 
    .I(GSR),
7854 
    .O(\rx_buf_reg_6<6>/FFY/RST )
7855 
  );
7856 
  X_FF rx_buf_reg_6_6 (
7857 
    .I(rx_shift_reg_6[6]),
7858 
    .CE(\_n00571/O ),
7859 
    .CLK(div_reg),
7860 
    .SET(GND),
7861 
    .RST(\rx_buf_reg_6<6>/FFY/RST ),
7862 
    .O(rx_buf_reg_6[6])
7863 
  );
7864 
  X_BUF \tx_buf_reg_0<1>/FFY/RSTOR  (
7865 
    .I(GSR),
7866 
    .O(\tx_buf_reg_0<1>/FFY/RST )
7867 
  );
7868 
  X_FF tx_buf_reg_0_0 (
7869 
    .I(data_out_bus[0]),
7870 
    .CE(_n0027),
7871 
    .CLK(clk_in_BUFGP),
7872 
    .SET(GND),
7873 
    .RST(\tx_buf_reg_0<1>/FFY/RST ),
7874 
    .O(tx_buf_reg_0[0])
7875 
  );
7876 
  X_BUF \tx_buf_reg_4<5>/FFY/RSTOR  (
7877 
    .I(GSR),
7878 
    .O(\tx_buf_reg_4<5>/FFY/RST )
7879 
  );
7880 
  X_FF tx_buf_reg_4_4 (
7881 
    .I(data_out_bus[4]),
7882 
    .CE(\_n00311/O ),
7883 
    .CLK(clk_in_BUFGP),
7884 
    .SET(GND),
7885 
    .RST(\tx_buf_reg_4<5>/FFY/RST ),
7886 
    .O(tx_buf_reg_4[4])
7887 
  );
7888 
  X_BUF \tx_buf_reg_5<3>/FFX/RSTOR  (
7889 
    .I(GSR),
7890 
    .O(\tx_buf_reg_5<3>/FFX/RST )
7891 
  );
7892 
  X_FF tx_buf_reg_5_3 (
7893 
    .I(data_out_bus[3]),
7894 
    .CE(\_n00321/O ),
7895 
    .CLK(clk_in_BUFGP),
7896 
    .SET(GND),
7897 
    .RST(\tx_buf_reg_5<3>/FFX/RST ),
7898 
    .O(tx_buf_reg_5[3])
7899 
  );
7900 
  X_BUF \tx_buf_reg_0<5>/FFX/RSTOR  (
7901 
    .I(GSR),
7902 
    .O(\tx_buf_reg_0<5>/FFX/RST )
7903 
  );
7904 
  X_FF tx_buf_reg_0_5 (
7905 
    .I(data_out_bus[5]),
7906 
    .CE(_n0027),
7907 
    .CLK(clk_in_BUFGP),
7908 
    .SET(GND),
7909 
    .RST(\tx_buf_reg_0<5>/FFX/RST ),
7910 
    .O(tx_buf_reg_0[5])
7911 
  );
7912 
  X_BUF \tx_buf_reg_1<5>/FFX/RSTOR  (
7913 
    .I(GSR),
7914 
    .O(\tx_buf_reg_1<5>/FFX/RST )
7915 
  );
7916 
  X_FF tx_buf_reg_1_5 (
7917 
    .I(data_out_bus[5]),
7918 
    .CE(_n0028),
7919 
    .CLK(clk_in_BUFGP),
7920 
    .SET(GND),
7921 
    .RST(\tx_buf_reg_1<5>/FFX/RST ),
7922 
    .O(tx_buf_reg_1[5])
7923 
  );
7924 
  X_BUF \tx_buf_reg_0<3>/FFY/RSTOR  (
7925 
    .I(GSR),
7926 
    .O(\tx_buf_reg_0<3>/FFY/RST )
7927 
  );
7928 
  X_FF tx_buf_reg_0_2 (
7929 
    .I(data_out_bus[2]),
7930 
    .CE(_n0027),
7931 
    .CLK(clk_in_BUFGP),
7932 
    .SET(GND),
7933 
    .RST(\tx_buf_reg_0<3>/FFY/RST ),
7934 
    .O(tx_buf_reg_0[2])
7935 
  );
7936 
  X_BUF \tx_buf_reg_0<1>/FFX/RSTOR  (
7937 
    .I(GSR),
7938 
    .O(\tx_buf_reg_0<1>/FFX/RST )
7939 
  );
7940 
  X_FF tx_buf_reg_0_1 (
7941 
    .I(data_out_bus[1]),
7942 
    .CE(_n0027),
7943 
    .CLK(clk_in_BUFGP),
7944 
    .SET(GND),
7945 
    .RST(\tx_buf_reg_0<1>/FFX/RST ),
7946 
    .O(tx_buf_reg_0[1])
7947 
  );
7948 
  X_BUF \tx_buf_reg_6<1>/FFY/RSTOR  (
7949 
    .I(GSR),
7950 
    .O(\tx_buf_reg_6<1>/FFY/RST )
7951 
  );
7952 
  X_FF tx_buf_reg_6_0 (
7953 
    .I(data_out_bus[0]),
7954 
    .CE(_n0033),
7955 
    .CLK(clk_in_BUFGP),
7956 
    .SET(GND),
7957 
    .RST(\tx_buf_reg_6<1>/FFY/RST ),
7958 
    .O(tx_buf_reg_6[0])
7959 
  );
7960 
  X_BUF \tx_buf_reg_0<3>/FFX/RSTOR  (
7961 
    .I(GSR),
7962 
    .O(\tx_buf_reg_0<3>/FFX/RST )
7963 
  );
7964 
  X_FF tx_buf_reg_0_3 (
7965 
    .I(data_out_bus[3]),
7966 
    .CE(_n0027),
7967 
    .CLK(clk_in_BUFGP),
7968 
    .SET(GND),
7969 
    .RST(\tx_buf_reg_0<3>/FFX/RST ),
7970 
    .O(tx_buf_reg_0[3])
7971 
  );
7972 
  X_BUF \tx_buf_reg_1<3>/FFX/RSTOR  (
7973 
    .I(GSR),
7974 
    .O(\tx_buf_reg_1<3>/FFX/RST )
7975 
  );
7976 
  X_FF tx_buf_reg_1_3 (
7977 
    .I(data_out_bus[3]),
7978 
    .CE(_n0028),
7979 
    .CLK(clk_in_BUFGP),
7980 
    .SET(GND),
7981 
    .RST(\tx_buf_reg_1<3>/FFX/RST ),
7982 
    .O(tx_buf_reg_1[3])
7983 
  );
7984 
  X_BUF \tx_buf_reg_1<1>/FFX/RSTOR  (
7985 
    .I(GSR),
7986 
    .O(\tx_buf_reg_1<1>/FFX/RST )
7987 
  );
7988 
  X_FF tx_buf_reg_1_1 (
7989 
    .I(data_out_bus[1]),
7990 
    .CE(_n0028),
7991 
    .CLK(clk_in_BUFGP),
7992 
    .SET(GND),
7993 
    .RST(\tx_buf_reg_1<1>/FFX/RST ),
7994 
    .O(tx_buf_reg_1[1])
7995 
  );
7996 
  X_BUF \tx_buf_reg_2<5>/FFX/RSTOR  (
7997 
    .I(GSR),
7998 
    .O(\tx_buf_reg_2<5>/FFX/RST )
7999 
  );
8000 
  X_FF tx_buf_reg_2_5 (
8001 
    .I(data_out_bus[5]),
8002 
    .CE(_n0029),
8003 
    .CLK(clk_in_BUFGP),
8004 
    .SET(GND),
8005 
    .RST(\tx_buf_reg_2<5>/FFX/RST ),
8006 
    .O(tx_buf_reg_2[5])
8007 
  );
8008 
  X_BUF \tx_buf_reg_2<1>/FFY/RSTOR  (
8009 
    .I(GSR),
8010 
    .O(\tx_buf_reg_2<1>/FFY/RST )
8011 
  );
8012 
  X_FF tx_buf_reg_2_0 (
8013 
    .I(data_out_bus[0]),
8014 
    .CE(_n0029),
8015 
    .CLK(clk_in_BUFGP),
8016 
    .SET(GND),
8017 
    .RST(\tx_buf_reg_2<1>/FFY/RST ),
8018 
    .O(tx_buf_reg_2[0])
8019 
  );
8020 
  X_BUF \tx_buf_reg_0<7>/FFX/RSTOR  (
8021 
    .I(GSR),
8022 
    .O(\tx_buf_reg_0<7>/FFX/RST )
8023 
  );
8024 
  X_FF tx_buf_reg_0_7 (
8025 
    .I(data_out_bus[7]),
8026 
    .CE(_n0027),
8027 
    .CLK(clk_in_BUFGP),
8028 
    .SET(GND),
8029 
    .RST(\tx_buf_reg_0<7>/FFX/RST ),
8030 
    .O(tx_buf_reg_0[7])
8031 
  );
8032 
  X_BUF \tx_buf_reg_1<1>/FFY/RSTOR  (
8033 
    .I(GSR),
8034 
    .O(\tx_buf_reg_1<1>/FFY/RST )
8035 
  );
8036 
  X_FF tx_buf_reg_1_0 (
8037 
    .I(data_out_bus[0]),
8038 
    .CE(_n0028),
8039 
    .CLK(clk_in_BUFGP),
8040 
    .SET(GND),
8041 
    .RST(\tx_buf_reg_1<1>/FFY/RST ),
8042 
    .O(tx_buf_reg_1[0])
8043 
  );
8044 
  X_BUF \tx_buf_reg_1<3>/FFY/RSTOR  (
8045 
    .I(GSR),
8046 
    .O(\tx_buf_reg_1<3>/FFY/RST )
8047 
  );
8048 
  X_FF tx_buf_reg_1_2 (
8049 
    .I(data_out_bus[2]),
8050 
    .CE(_n0028),
8051 
    .CLK(clk_in_BUFGP),
8052 
    .SET(GND),
8053 
    .RST(\tx_buf_reg_1<3>/FFY/RST ),
8054 
    .O(tx_buf_reg_1[2])
8055 
  );
8056 
  X_BUF \tx_buf_reg_0<7>/FFY/RSTOR  (
8057 
    .I(GSR),
8058 
    .O(\tx_buf_reg_0<7>/FFY/RST )
8059 
  );
8060 
  X_FF tx_buf_reg_0_6 (
8061 
    .I(data_out_bus[6]),
8062 
    .CE(_n0027),
8063 
    .CLK(clk_in_BUFGP),
8064 
    .SET(GND),
8065 
    .RST(\tx_buf_reg_0<7>/FFY/RST ),
8066 
    .O(tx_buf_reg_0[6])
8067 
  );
8068 
  X_BUF \tx_buf_reg_6<1>/FFX/RSTOR  (
8069 
    .I(GSR),
8070 
    .O(\tx_buf_reg_6<1>/FFX/RST )
8071 
  );
8072 
  X_FF tx_buf_reg_6_1 (
8073 
    .I(data_out_bus[1]),
8074 
    .CE(_n0033),
8075 
    .CLK(clk_in_BUFGP),
8076 
    .SET(GND),
8077 
    .RST(\tx_buf_reg_6<1>/FFX/RST ),
8078 
    .O(tx_buf_reg_6[1])
8079 
  );
8080 
  X_BUF \tx_buf_reg_2<1>/FFX/RSTOR  (
8081 
    .I(GSR),
8082 
    .O(\tx_buf_reg_2<1>/FFX/RST )
8083 
  );
8084 
  X_FF tx_buf_reg_2_1 (
8085 
    .I(data_out_bus[1]),
8086 
    .CE(_n0029),
8087 
    .CLK(clk_in_BUFGP),
8088 
    .SET(GND),
8089 
    .RST(\tx_buf_reg_2<1>/FFX/RST ),
8090 
    .O(tx_buf_reg_2[1])
8091 
  );
8092 
  X_BUF \tx_buf_reg_1<5>/FFY/RSTOR  (
8093 
    .I(GSR),
8094 
    .O(\tx_buf_reg_1<5>/FFY/RST )
8095 
  );
8096 
  X_FF tx_buf_reg_1_4 (
8097 
    .I(data_out_bus[4]),
8098 
    .CE(_n0028),
8099 
    .CLK(clk_in_BUFGP),
8100 
    .SET(GND),
8101 
    .RST(\tx_buf_reg_1<5>/FFY/RST ),
8102 
    .O(tx_buf_reg_1[4])
8103 
  );
8104 
  X_BUF \tx_buf_reg_2<3>/FFX/RSTOR  (
8105 
    .I(GSR),
8106 
    .O(\tx_buf_reg_2<3>/FFX/RST )
8107 
  );
8108 
  X_FF tx_buf_reg_2_3 (
8109 
    .I(data_out_bus[3]),
8110 
    .CE(_n0029),
8111 
    .CLK(clk_in_BUFGP),
8112 
    .SET(GND),
8113 
    .RST(\tx_buf_reg_2<3>/FFX/RST ),
8114 
    .O(tx_buf_reg_2[3])
8115 
  );
8116 
  X_BUF \tx_buf_reg_3<3>/FFY/RSTOR  (
8117 
    .I(GSR),
8118 
    .O(\tx_buf_reg_3<3>/FFY/RST )
8119 
  );
8120 
  X_FF tx_buf_reg_3_2 (
8121 
    .I(data_out_bus[2]),
8122 
    .CE(_n0030),
8123 
    .CLK(clk_in_BUFGP),
8124 
    .SET(GND),
8125 
    .RST(\tx_buf_reg_3<3>/FFY/RST ),
8126 
    .O(tx_buf_reg_3[2])
8127 
  );
8128 
  X_BUF \tx_buf_reg_3<1>/FFY/RSTOR  (
8129 
    .I(GSR),
8130 
    .O(\tx_buf_reg_3<1>/FFY/RST )
8131 
  );
8132 
  X_FF tx_buf_reg_3_0 (
8133 
    .I(data_out_bus[0]),
8134 
    .CE(_n0030),
8135 
    .CLK(clk_in_BUFGP),
8136 
    .SET(GND),
8137 
    .RST(\tx_buf_reg_3<1>/FFY/RST ),
8138 
    .O(tx_buf_reg_3[0])
8139 
  );
8140 
  X_BUF \tx_buf_reg_2<3>/FFY/RSTOR  (
8141 
    .I(GSR),
8142 
    .O(\tx_buf_reg_2<3>/FFY/RST )
8143 
  );
8144 
  X_FF tx_buf_reg_2_2 (
8145 
    .I(data_out_bus[2]),
8146 
    .CE(_n0029),
8147 
    .CLK(clk_in_BUFGP),
8148 
    .SET(GND),
8149 
    .RST(\tx_buf_reg_2<3>/FFY/RST ),
8150 
    .O(tx_buf_reg_2[2])
8151 
  );
8152 
  X_BUF \tx_buf_reg_1<7>/FFY/RSTOR  (
8153 
    .I(GSR),
8154 
    .O(\tx_buf_reg_1<7>/FFY/RST )
8155 
  );
8156 
  X_FF tx_buf_reg_1_6 (
8157 
    .I(data_out_bus[6]),
8158 
    .CE(_n0028),
8159 
    .CLK(clk_in_BUFGP),
8160 
    .SET(GND),
8161 
    .RST(\tx_buf_reg_1<7>/FFY/RST ),
8162 
    .O(tx_buf_reg_1[6])
8163 
  );
8164 
  X_BUF \tx_buf_reg_3<7>/FFX/RSTOR  (
8165 
    .I(GSR),
8166 
    .O(\tx_buf_reg_3<7>/FFX/RST )
8167 
  );
8168 
  X_FF tx_buf_reg_3_7 (
8169 
    .I(data_out_bus[7]),
8170 
    .CE(_n0030),
8171 
    .CLK(clk_in_BUFGP),
8172 
    .SET(GND),
8173 
    .RST(\tx_buf_reg_3<7>/FFX/RST ),
8174 
    .O(tx_buf_reg_3[7])
8175 
  );
8176 
  X_BUF \tx_buf_reg_3<1>/FFX/RSTOR  (
8177 
    .I(GSR),
8178 
    .O(\tx_buf_reg_3<1>/FFX/RST )
8179 
  );
8180 
  X_FF tx_buf_reg_3_1 (
8181 
    .I(data_out_bus[1]),
8182 
    .CE(_n0030),
8183 
    .CLK(clk_in_BUFGP),
8184 
    .SET(GND),
8185 
    .RST(\tx_buf_reg_3<1>/FFX/RST ),
8186 
    .O(tx_buf_reg_3[1])
8187 
  );
8188 
  X_BUF \tx_buf_reg_2<5>/FFY/RSTOR  (
8189 
    .I(GSR),
8190 
    .O(\tx_buf_reg_2<5>/FFY/RST )
8191 
  );
8192 
  X_FF tx_buf_reg_2_4 (
8193 
    .I(data_out_bus[4]),
8194 
    .CE(_n0029),
8195 
    .CLK(clk_in_BUFGP),
8196 
    .SET(GND),
8197 
    .RST(\tx_buf_reg_2<5>/FFY/RST ),
8198 
    .O(tx_buf_reg_2[4])
8199 
  );
8200 
  X_BUF \tx_buf_reg_4<5>/FFX/RSTOR  (
8201 
    .I(GSR),
8202 
    .O(\tx_buf_reg_4<5>/FFX/RST )
8203 
  );
8204 
  X_FF tx_buf_reg_4_5 (
8205 
    .I(data_out_bus[5]),
8206 
    .CE(\_n00311/O ),
8207 
    .CLK(clk_in_BUFGP),
8208 
    .SET(GND),
8209 
    .RST(\tx_buf_reg_4<5>/FFX/RST ),
8210 
    .O(tx_buf_reg_4[5])
8211 
  );
8212 
  X_BUF \tx_buf_reg_5<3>/FFY/RSTOR  (
8213 
    .I(GSR),
8214 
    .O(\tx_buf_reg_5<3>/FFY/RST )
8215 
  );
8216 
  X_FF tx_buf_reg_5_2 (
8217 
    .I(data_out_bus[2]),
8218 
    .CE(\_n00321/O ),
8219 
    .CLK(clk_in_BUFGP),
8220 
    .SET(GND),
8221 
    .RST(\tx_buf_reg_5<3>/FFY/RST ),
8222 
    .O(tx_buf_reg_5[2])
8223 
  );
8224 
  X_BUF \tx_buf_reg_3<7>/FFY/RSTOR  (
8225 
    .I(GSR),
8226 
    .O(\tx_buf_reg_3<7>/FFY/RST )
8227 
  );
8228 
  X_FF tx_buf_reg_3_6 (
8229 
    .I(data_out_bus[6]),
8230 
    .CE(_n0030),
8231 
    .CLK(clk_in_BUFGP),
8232 
    .SET(GND),
8233 
    .RST(\tx_buf_reg_3<7>/FFY/RST ),
8234 
    .O(tx_buf_reg_3[6])
8235 
  );
8236 
  X_BUF \tx_buf_reg_3<3>/FFX/RSTOR  (
8237 
    .I(GSR),
8238 
    .O(\tx_buf_reg_3<3>/FFX/RST )
8239 
  );
8240 
  X_FF tx_buf_reg_3_3 (
8241 
    .I(data_out_bus[3]),
8242 
    .CE(_n0030),
8243 
    .CLK(clk_in_BUFGP),
8244 
    .SET(GND),
8245 
    .RST(\tx_buf_reg_3<3>/FFX/RST ),
8246 
    .O(tx_buf_reg_3[3])
8247 
  );
8248 
  X_BUF \tx_buf_reg_6<5>/FFX/RSTOR  (
8249 
    .I(GSR),
8250 
    .O(\tx_buf_reg_6<5>/FFX/RST )
8251 
  );
8252 
  X_FF tx_buf_reg_6_5 (
8253 
    .I(data_out_bus[5]),
8254 
    .CE(_n0033),
8255 
    .CLK(clk_in_BUFGP),
8256 
    .SET(GND),
8257 
    .RST(\tx_buf_reg_6<5>/FFX/RST ),
8258 
    .O(tx_buf_reg_6[5])
8259 
  );
8260 
  X_BUF \tx_buf_reg_6<3>/FFY/RSTOR  (
8261 
    .I(GSR),
8262 
    .O(\tx_buf_reg_6<3>/FFY/RST )
8263 
  );
8264 
  X_FF tx_buf_reg_6_2 (
8265 
    .I(data_out_bus[2]),
8266 
    .CE(_n0033),
8267 
    .CLK(clk_in_BUFGP),
8268 
    .SET(GND),
8269 
    .RST(\tx_buf_reg_6<3>/FFY/RST ),
8270 
    .O(tx_buf_reg_6[2])
8271 
  );
8272 
  X_BUF \tx_buf_reg_6<3>/FFX/RSTOR  (
8273 
    .I(GSR),
8274 
    .O(\tx_buf_reg_6<3>/FFX/RST )
8275 
  );
8276 
  X_FF tx_buf_reg_6_3 (
8277 
    .I(data_out_bus[3]),
8278 
    .CE(_n0033),
8279 
    .CLK(clk_in_BUFGP),
8280 
    .SET(GND),
8281 
    .RST(\tx_buf_reg_6<3>/FFX/RST ),
8282 
    .O(tx_buf_reg_6[3])
8283 
  );
8284 
  X_BUF \tx_buf_reg_7<7>/FFY/RSTOR  (
8285 
    .I(GSR),
8286 
    .O(\tx_buf_reg_7<7>/FFY/RST )
8287 
  );
8288 
  X_FF tx_buf_reg_7_6 (
8289 
    .I(data_out_bus[6]),
8290 
    .CE(_n0034),
8291 
    .CLK(clk_in_BUFGP),
8292 
    .SET(GND),
8293 
    .RST(\tx_buf_reg_7<7>/FFY/RST ),
8294 
    .O(tx_buf_reg_7[6])
8295 
  );
8296 
  X_BUF \tx_buf_reg_7<3>/FFX/RSTOR  (
8297 
    .I(GSR),
8298 
    .O(\tx_buf_reg_7<3>/FFX/RST )
8299 
  );
8300 
  X_FF tx_buf_reg_7_3 (
8301 
    .I(data_out_bus[3]),
8302 
    .CE(_n0034),
8303 
    .CLK(clk_in_BUFGP),
8304 
    .SET(GND),
8305 
    .RST(\tx_buf_reg_7<3>/FFX/RST ),
8306 
    .O(tx_buf_reg_7[3])
8307 
  );
8308 
  X_BUF \tx_buf_reg_6<7>/FFX/RSTOR  (
8309 
    .I(GSR),
8310 
    .O(\tx_buf_reg_6<7>/FFX/RST )
8311 
  );
8312 
  X_FF tx_buf_reg_6_7 (
8313 
    .I(data_out_bus[7]),
8314 
    .CE(_n0033),
8315 
    .CLK(clk_in_BUFGP),
8316 
    .SET(GND),
8317 
    .RST(\tx_buf_reg_6<7>/FFX/RST ),
8318 
    .O(tx_buf_reg_6[7])
8319 
  );
8320 
  X_BUF \frame_delay_buf_4<1>/FFY/RSTOR  (
8321 
    .I(GSR),
8322 
    .O(\frame_delay_buf_4<1>/FFY/RST )
8323 
  );
8324 
  X_FF frame_delay_buf_4_0 (
8325 
    .I(mpi_data_in_0_IBUF),
8326 
    .CE(_n0042),
8327 
    .CLK(mpi_clk_BUFGP),
8328 
    .SET(GND),
8329 
    .RST(\frame_delay_buf_4<1>/FFY/RST ),
8330 
    .O(frame_delay_buf_4[0])
8331 
  );
8332 
  X_BUF \tx_buf_reg_6<5>/FFY/RSTOR  (
8333 
    .I(GSR),
8334 
    .O(\tx_buf_reg_6<5>/FFY/RST )
8335 
  );
8336 
  X_FF tx_buf_reg_6_4 (
8337 
    .I(data_out_bus[4]),
8338 
    .CE(_n0033),
8339 
    .CLK(clk_in_BUFGP),
8340 
    .SET(GND),
8341 
    .RST(\tx_buf_reg_6<5>/FFY/RST ),
8342 
    .O(tx_buf_reg_6[4])
8343 
  );
8344 
  X_BUF \tx_buf_reg_7<1>/FFY/RSTOR  (
8345 
    .I(GSR),
8346 
    .O(\tx_buf_reg_7<1>/FFY/RST )
8347 
  );
8348 
  X_FF tx_buf_reg_7_0 (
8349 
    .I(data_out_bus[0]),
8350 
    .CE(_n0034),
8351 
    .CLK(clk_in_BUFGP),
8352 
    .SET(GND),
8353 
    .RST(\tx_buf_reg_7<1>/FFY/RST ),
8354 
    .O(tx_buf_reg_7[0])
8355 
  );
8356 
  X_BUF \tx_buf_reg_7<5>/FFX/RSTOR  (
8357 
    .I(GSR),
8358 
    .O(\tx_buf_reg_7<5>/FFX/RST )
8359 
  );
8360 
  X_FF tx_buf_reg_7_5 (
8361 
    .I(data_out_bus[5]),
8362 
    .CE(_n0034),
8363 
    .CLK(clk_in_BUFGP),
8364 
    .SET(GND),
8365 
    .RST(\tx_buf_reg_7<5>/FFX/RST ),
8366 
    .O(tx_buf_reg_7[5])
8367 
  );
8368 
  X_BUF \tx_buf_reg_7<1>/FFX/RSTOR  (
8369 
    .I(GSR),
8370 
    .O(\tx_buf_reg_7<1>/FFX/RST )
8371 
  );
8372 
  X_FF tx_buf_reg_7_1 (
8373 
    .I(data_out_bus[1]),
8374 
    .CE(_n0034),
8375 
    .CLK(clk_in_BUFGP),
8376 
    .SET(GND),
8377 
    .RST(\tx_buf_reg_7<1>/FFX/RST ),
8378 
    .O(tx_buf_reg_7[1])
8379 
  );
8380 
  X_BUF \frame_delay_buf_0<1>/FFY/RSTOR  (
8381 
    .I(GSR),
8382 
    .O(\frame_delay_buf_0<1>/FFY/RST )
8383 
  );
8384 
  X_FF frame_delay_buf_0_0 (
8385 
    .I(mpi_data_in_0_IBUF),
8386 
    .CE(_n0038),
8387 
    .CLK(mpi_clk_BUFGP),
8388 
    .SET(GND),
8389 
    .RST(\frame_delay_buf_0<1>/FFY/RST ),
8390 
    .O(frame_delay_buf_0[0])
8391 
  );
8392 
  X_BUF \tx_buf_reg_7<3>/FFY/RSTOR  (
8393 
    .I(GSR),
8394 
    .O(\tx_buf_reg_7<3>/FFY/RST )
8395 
  );
8396 
  X_FF tx_buf_reg_7_2 (
8397 
    .I(data_out_bus[2]),
8398 
    .CE(_n0034),
8399 
    .CLK(clk_in_BUFGP),
8400 
    .SET(GND),
8401 
    .RST(\tx_buf_reg_7<3>/FFY/RST ),
8402 
    .O(tx_buf_reg_7[2])
8403 
  );
8404 
  X_BUF \tx_buf_reg_6<7>/FFY/RSTOR  (
8405 
    .I(GSR),
8406 
    .O(\tx_buf_reg_6<7>/FFY/RST )
8407 
  );
8408 
  X_FF tx_buf_reg_6_6 (
8409 
    .I(data_out_bus[6]),
8410 
    .CE(_n0033),
8411 
    .CLK(clk_in_BUFGP),
8412 
    .SET(GND),
8413 
    .RST(\tx_buf_reg_6<7>/FFY/RST ),
8414 
    .O(tx_buf_reg_6[6])
8415 
  );
8416 
  X_BUF \frame_delay_buf_1<1>/FFY/RSTOR  (
8417 
    .I(GSR),
8418 
    .O(\frame_delay_buf_1<1>/FFY/RST )
8419 
  );
8420 
  X_FF frame_delay_buf_1_0 (
8421 
    .I(mpi_data_in_0_IBUF),
8422 
    .CE(_n0039),
8423 
    .CLK(mpi_clk_BUFGP),
8424 
    .SET(GND),
8425 
    .RST(\frame_delay_buf_1<1>/FFY/RST ),
8426 
    .O(frame_delay_buf_1[0])
8427 
  );
8428 
  X_BUF \frame_delay_buf_6<1>/FFY/RSTOR  (
8429 
    .I(GSR),
8430 
    .O(\frame_delay_buf_6<1>/FFY/RST )
8431 
  );
8432 
  X_FF frame_delay_buf_6_0 (
8433 
    .I(mpi_data_in_0_IBUF),
8434 
    .CE(_n0044),
8435 
    .CLK(mpi_clk_BUFGP),
8436 
    .SET(GND),
8437 
    .RST(\frame_delay_buf_6<1>/FFY/RST ),
8438 
    .O(frame_delay_buf_6[0])
8439 
  );
8440 
  X_BUF \tx_buf_reg_7<7>/FFX/RSTOR  (
8441 
    .I(GSR),
8442 
    .O(\tx_buf_reg_7<7>/FFX/RST )
8443 
  );
8444 
  X_FF tx_buf_reg_7_7 (
8445 
    .I(data_out_bus[7]),
8446 
    .CE(_n0034),
8447 
    .CLK(clk_in_BUFGP),
8448 
    .SET(GND),
8449 
    .RST(\tx_buf_reg_7<7>/FFX/RST ),
8450 
    .O(tx_buf_reg_7[7])
8451 
  );
8452 
  X_BUF \tx_buf_reg_7<5>/FFY/RSTOR  (
8453 
    .I(GSR),
8454 
    .O(\tx_buf_reg_7<5>/FFY/RST )
8455 
  );
8456 
  X_FF tx_buf_reg_7_4 (
8457 
    .I(data_out_bus[4]),
8458 
    .CE(_n0034),
8459 
    .CLK(clk_in_BUFGP),
8460 
    .SET(GND),
8461 
    .RST(\tx_buf_reg_7<5>/FFY/RST ),
8462 
    .O(tx_buf_reg_7[4])
8463 
  );
8464 
  X_BUF \frame_delay_buf_4<1>/FFX/RSTOR  (
8465 
    .I(GSR),
8466 
    .O(\frame_delay_buf_4<1>/FFX/RST )
8467 
  );
8468 
  X_FF frame_delay_buf_4_1 (
8469 
    .I(mpi_data_in_1_IBUF),
8470 
    .CE(_n0042),
8471 
    .CLK(mpi_clk_BUFGP),
8472 
    .SET(GND),
8473 
    .RST(\frame_delay_buf_4<1>/FFX/RST ),
8474 
    .O(frame_delay_buf_4[1])
8475 
  );
8476 
  X_BUF \frame_delay_buf_3<1>/FFY/RSTOR  (
8477 
    .I(GSR),
8478 
    .O(\frame_delay_buf_3<1>/FFY/RST )
8479 
  );
8480 
  X_FF frame_delay_buf_3_0 (
8481 
    .I(mpi_data_in_0_IBUF),
8482 
    .CE(_n0041),
8483 
    .CLK(mpi_clk_BUFGP),
8484 
    .SET(GND),
8485 
    .RST(\frame_delay_buf_3<1>/FFY/RST ),
8486 
    .O(frame_delay_buf_3[0])
8487 
  );
8488 
  X_BUF \frame_delay_buf_0<1>/FFX/RSTOR  (
8489 
    .I(GSR),
8490 
    .O(\frame_delay_buf_0<1>/FFX/RST )
8491 
  );
8492 
  X_FF frame_delay_buf_0_1 (
8493 
    .I(mpi_data_in_1_IBUF),
8494 
    .CE(_n0038),
8495 
    .CLK(mpi_clk_BUFGP),
8496 
    .SET(GND),
8497 
    .RST(\frame_delay_buf_0<1>/FFX/RST ),
8498 
    .O(frame_delay_buf_0[1])
8499 
  );
8500 
  X_BUF \frame_delay_buf_2<1>/FFX/RSTOR  (
8501 
    .I(GSR),
8502 
    .O(\frame_delay_buf_2<1>/FFX/RST )
8503 
  );
8504 
  X_FF frame_delay_buf_2_1 (
8505 
    .I(mpi_data_in_1_IBUF),
8506 
    .CE(_n0040),
8507 
    .CLK(mpi_clk_BUFGP),
8508 
    .SET(GND),
8509 
    .RST(\frame_delay_buf_2<1>/FFX/RST ),
8510 
    .O(frame_delay_buf_2[1])
8511 
  );
8512 
  X_BUF \frame_delay_buf_2<1>/FFY/RSTOR  (
8513 
    .I(GSR),
8514 
    .O(\frame_delay_buf_2<1>/FFY/RST )
8515 
  );
8516 
  X_FF frame_delay_buf_2_0 (
8517 
    .I(mpi_data_in_0_IBUF),
8518 
    .CE(_n0040),
8519 
    .CLK(mpi_clk_BUFGP),
8520 
    .SET(GND),
8521 
    .RST(\frame_delay_buf_2<1>/FFY/RST ),
8522 
    .O(frame_delay_buf_2[0])
8523 
  );
8524 
  X_BUF \frame_delay_buf_1<1>/FFX/RSTOR  (
8525 
    .I(GSR),
8526 
    .O(\frame_delay_buf_1<1>/FFX/RST )
8527 
  );
8528 
  X_FF frame_delay_buf_1_1 (
8529 
    .I(mpi_data_in_1_IBUF),
8530 
    .CE(_n0039),
8531 
    .CLK(mpi_clk_BUFGP),
8532 
    .SET(GND),
8533 
    .RST(\frame_delay_buf_1<1>/FFX/RST ),
8534 
    .O(frame_delay_buf_1[1])
8535 
  );
8536 
  X_BUF \frame_delay_buf_3<1>/FFX/RSTOR  (
8537 
    .I(GSR),
8538 
    .O(\frame_delay_buf_3<1>/FFX/RST )
8539 
  );
8540 
  X_FF frame_delay_buf_3_1 (
8541 
    .I(mpi_data_in_1_IBUF),
8542 
    .CE(_n0041),
8543 
    .CLK(mpi_clk_BUFGP),
8544 
    .SET(GND),
8545 
    .RST(\frame_delay_buf_3<1>/FFX/RST ),
8546 
    .O(frame_delay_buf_3[1])
8547 
  );
8548 
  X_BUF \frame_delay_buf_5<1>/FFX/RSTOR  (
8549 
    .I(GSR),
8550 
    .O(\frame_delay_buf_5<1>/FFX/RST )
8551 
  );
8552 
  X_FF frame_delay_buf_5_1 (
8553 
    .I(mpi_data_in_1_IBUF),
8554 
    .CE(_n0043),
8555 
    .CLK(mpi_clk_BUFGP),
8556 
    .SET(GND),
8557 
    .RST(\frame_delay_buf_5<1>/FFX/RST ),
8558 
    .O(frame_delay_buf_5[1])
8559 
  );
8560 
  X_BUF \frame_delay_buf_5<1>/FFY/RSTOR  (
8561 
    .I(GSR),
8562 
    .O(\frame_delay_buf_5<1>/FFY/RST )
8563 
  );
8564 
  X_FF frame_delay_buf_5_0 (
8565 
    .I(mpi_data_in_0_IBUF),
8566 
    .CE(_n0043),
8567 
    .CLK(mpi_clk_BUFGP),
8568 
    .SET(GND),
8569 
    .RST(\frame_delay_buf_5<1>/FFY/RST ),
8570 
    .O(frame_delay_buf_5[0])
8571 
  );
8572 
  X_BUF \frame_delay_buf_6<1>/FFX/RSTOR  (
8573 
    .I(GSR),
8574 
    .O(\frame_delay_buf_6<1>/FFX/RST )
8575 
  );
8576 
  X_FF frame_delay_buf_6_1 (
8577 
    .I(mpi_data_in_1_IBUF),
8578 
    .CE(_n0044),
8579 
    .CLK(mpi_clk_BUFGP),
8580 
    .SET(GND),
8581 
    .RST(\frame_delay_buf_6<1>/FFX/RST ),
8582 
    .O(frame_delay_buf_6[1])
8583 
  );
8584 
  X_CKBUF \clk_in/BUF  (
8585 
    .I(clk_in),
8586 
    .O(\clk_in_BUFGP/IBUFG )
8587 
  );
8588 
  X_IPAD \clk_in/PAD  (
8589 
    .PAD(clk_in)
8590 
  );
8591 
  X_CKBUF \mpi_clk/BUF  (
8592 
    .I(mpi_clk),
8593 
    .O(\mpi_clk_BUFGP/IBUFG )
8594 
  );
8595 
  X_IPAD \mpi_clk/PAD  (
8596 
    .PAD(mpi_clk)
8597 
  );
8598 
  X_CKBUF \clk_in_BUFGP/BUFG/BUF  (
8599 
    .I(\clk_in_BUFGP/IBUFG ),
8600 
    .O(clk_in_BUFGP)
8601 
  );
8602 
  X_CKBUF \mpi_clk_BUFGP/BUFG/BUF  (
8603 
    .I(\mpi_clk_BUFGP/IBUFG ),
8604 
    .O(mpi_clk_BUFGP)
8605 
  );
8606 
  X_BUF \PWR_VCC_0/YUSED  (
8607 
    .I(\PWR_VCC_0/GROM ),
8608 
    .O(GLOBAL_LOGIC0_2)
8609 
  );
8610 
  X_BUF \PWR_VCC_0/XUSED  (
8611 
    .I(\PWR_VCC_0/FROM ),
8612 
    .O(GLOBAL_LOGIC1)
8613 
  );
8614 
  defparam \PWR_VCC_0/G .INIT = 16'h0000;
8615 
  X_LUT4 \PWR_VCC_0/G  (
8616 
    .ADR0(VCC),
8617 
    .ADR1(VCC),
8618 
    .ADR2(VCC),
8619 
    .ADR3(VCC),
8620 
    .O(\PWR_VCC_0/GROM )
8621 
  );
8622 
  defparam \PWR_VCC_0/F .INIT = 16'hFFFF;
8623 
  X_LUT4 \PWR_VCC_0/F  (
8624 
    .ADR0(VCC),
8625 
    .ADR1(VCC),
8626 
    .ADR2(VCC),
8627 
    .ADR3(VCC),
8628 
    .O(\PWR_VCC_0/FROM )
8629 
  );
8630 
  X_BUF \PWR_VCC_1/XUSED  (
8631 
    .I(\PWR_VCC_1/FROM ),
8632 
    .O(GLOBAL_LOGIC1_0)
8633 
  );
8634 
  defparam \PWR_VCC_1/F .INIT = 16'hFFFF;
8635 
  X_LUT4 \PWR_VCC_1/F  (
8636 
    .ADR0(VCC),
8637 
    .ADR1(VCC),
8638 
    .ADR2(VCC),
8639 
    .ADR3(VCC),
8640 
    .O(\PWR_VCC_1/FROM )
8641 
  );
8642 
  X_BUF \PWR_VCC_2/XUSED  (
8643 
    .I(\PWR_VCC_2/FROM ),
8644 
    .O(GLOBAL_LOGIC1_1)
8645 
  );
8646 
  defparam \PWR_VCC_2/F .INIT = 16'hFFFF;
8647 
  X_LUT4 \PWR_VCC_2/F  (
8648 
    .ADR0(VCC),
8649 
    .ADR1(VCC),
8650 
    .ADR2(VCC),
8651 
    .ADR3(VCC),
8652 
    .O(\PWR_VCC_2/FROM )
8653 
  );
8654 
  X_BUF \PWR_GND_0/YUSED  (
8655 
    .I(\PWR_GND_0/GROM ),
8656 
    .O(GLOBAL_LOGIC0)
8657 
  );
8658 
  defparam \PWR_GND_0/G .INIT = 16'h0000;
8659 
  X_LUT4 \PWR_GND_0/G  (
8660 
    .ADR0(VCC),
8661 
    .ADR1(VCC),
8662 
    .ADR2(VCC),
8663 
    .ADR3(VCC),
8664 
    .O(\PWR_GND_0/GROM )
8665 
  );
8666 
  X_BUF \PWR_GND_1/YUSED  (
8667 
    .I(\PWR_GND_1/GROM ),
8668 
    .O(GLOBAL_LOGIC0_3)
8669 
  );
8670 
  defparam \PWR_GND_1/G .INIT = 16'h0000;
8671 
  X_LUT4 \PWR_GND_1/G  (
8672 
    .ADR0(VCC),
8673 
    .ADR1(VCC),
8674 
    .ADR2(VCC),
8675 
    .ADR3(VCC),
8676 
    .O(\PWR_GND_1/GROM )
8677 
  );
8678 
  X_BUF \PWR_GND_2/YUSED  (
8679 
    .I(\PWR_GND_2/GROM ),
8680 
    .O(GLOBAL_LOGIC0_4)
8681 
  );
8682 
  defparam \PWR_GND_2/G .INIT = 16'h0000;
8683 
  X_LUT4 \PWR_GND_2/G  (
8684 
    .ADR0(VCC),
8685 
    .ADR1(VCC),
8686 
    .ADR2(VCC),
8687 
    .ADR3(VCC),
8688 
    .O(\PWR_GND_2/GROM )
8689 
  );
8690 
  X_BUF \PWR_GND_3/YUSED  (
8691 
    .I(\PWR_GND_3/GROM ),
8692 
    .O(GLOBAL_LOGIC0_5)
8693 
  );
8694 
  defparam \PWR_GND_3/G .INIT = 16'h0000;
8695 
  X_LUT4 \PWR_GND_3/G  (
8696 
    .ADR0(VCC),
8697 
    .ADR1(VCC),
8698 
    .ADR2(VCC),
8699 
    .ADR3(VCC),
8700 
    .O(\PWR_GND_3/GROM )
8701 
  );
8702 
  X_BUF \PWR_GND_4/YUSED  (
8703 
    .I(\PWR_GND_4/GROM ),
8704 
    .O(GLOBAL_LOGIC0_6)
8705 
  );
8706 
  defparam \PWR_GND_4/G .INIT = 16'h0000;
8707 
  X_LUT4 \PWR_GND_4/G  (
8708 
    .ADR0(VCC),
8709 
    .ADR1(VCC),
8710 
    .ADR2(VCC),
8711 
    .ADR3(VCC),
8712 
    .O(\PWR_GND_4/GROM )
8713 
  );
8714 
  X_ZERO NlwBlock_tdm_switch_top_GND (
8715 
    .O(GND)
8716 
  );
8717 
  X_ONE NlwBlock_tdm_switch_top_VCC (
8718 
    .O(VCC)
8719 
  );
8720 
endmodule
8721 
 

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