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[/] [tg68kc/] [trunk/] [TG68K_ALU.vhd] - Blame information for rev 5

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1 2 tobiflex 
------------------------------------------------------------------------------
2 
------------------------------------------------------------------------------
3 
--                                                                          --
4 4 tobiflex 
-- Copyright (c) 2009-2019 Tobias Gubener                                   --
5 
-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ...                          --
6 2 tobiflex 
-- Subdesign fAMpIGA by TobiFlex                                            --
7 
--                                                                          --
8 
-- This source file is free software: you can redistribute it and/or modify --
9 
-- it under the terms of the GNU Lesser General Public License as published --
10 
-- by the Free Software Foundation, either version 3 of the License, or     --
11 
-- (at your option) any later version.                                      --
12 
--                                                                          --
13 
-- This source file is distributed in the hope that it will be useful,      --
14 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of           --
15 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --
16 
-- GNU General Public License for more details.                             --
17 
--                                                                          --
18 
-- You should have received a copy of the GNU General Public License        --
19 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --
20 
--                                                                          --
21 
------------------------------------------------------------------------------
22 
------------------------------------------------------------------------------
23 
 
24 
library ieee;
25 
use ieee.std_logic_1164.all;
26 
use ieee.std_logic_unsigned.all;
27 
use IEEE.numeric_std.all;
28 
use work.TG68K_Pack.all;
29 
 
30 
entity TG68K_ALU is
31 
generic(
32 4 tobiflex 
                MUL_Mode : integer;                     --0=>16Bit,     1=>32Bit,       2=>switchable with CPU(1),      3=>no MUL,
33 
                MUL_Hardware : integer;         --0=>no,                1=>yes,
34 
                DIV_Mode : integer;                     --0=>16Bit,     1=>32Bit,       2=>switchable with CPU(1),      3=>no DIV,
35 
                BarrelShifter :integer          --0=>no,                1=>yes,         2=>switchable with CPU(1)
36 2 tobiflex 
                );
37 5 tobiflex 
        port(clk                                        : in std_logic;
38 
                Reset                                   : in std_logic;
39 
                clkena_lw                       : in std_logic:='1';
40 
                execOPC                         : in bit;
41 
                decodeOPC                       : in bit;
42 
                exe_condition           : in std_logic;
43 
                exec_tas                                : in std_logic;
44 
                long_start                      : in bit;
45 
                non_aligned                     : in std_logic;
46 
                movem_presub            : in bit;
47 
                set_stop                                : in bit;
48 
                Z_error                                 : in bit;
49 
                rot_bits                                : in std_logic_vector(1 downto 0);
50 
                exec                                    : in bit_vector(lastOpcBit downto 0);
51 
                OP1out                          : in std_logic_vector(31 downto 0);
52 
                OP2out                          : in std_logic_vector(31 downto 0);
53 
                reg_QA                          : in std_logic_vector(31 downto 0);
54 
                reg_QB                          : in std_logic_vector(31 downto 0);
55 
                opcode                          : in std_logic_vector(15 downto 0);
56 
                exe_opcode                      : in std_logic_vector(15 downto 0);
57 
                exe_datatype            : in std_logic_vector(1 downto 0);
58 
                sndOPC                          : in std_logic_vector(15 downto 0);
59 
                last_data_read          : in std_logic_vector(15 downto 0);
60 
                data_read                       : in std_logic_vector(15 downto 0);
61 
                FlagsSR                         : in std_logic_vector(7 downto 0);
62 2 tobiflex 
                micro_state                     : in micro_states;
63 5 tobiflex 
                bf_ext_in                       : in std_logic_vector(7 downto 0);
64 
                bf_ext_out                      : out std_logic_vector(7 downto 0);
65 
                bf_shift                                : in std_logic_vector(5 downto 0);
66 
                bf_width                                : in std_logic_vector(5 downto 0);
67 
                bf_ffo_offset           : in std_logic_vector(31 downto 0);
68 
                bf_loffset                      : in std_logic_vector(4 downto 0);
69 
 
70 
                set_V_Flag                      : buffer bit;
71 
                Flags                                   : buffer std_logic_vector(7 downto 0);
72 
                c_out                                   : buffer std_logic_vector(2 downto 0);
73 
                addsub_q                                : buffer std_logic_vector(31 downto 0);
74 
                ALUout                          : out std_logic_vector(31 downto 0)
75 
        );
76 2 tobiflex 
end TG68K_ALU;
77 
 
78 
architecture logic of TG68K_ALU is
79 
-----------------------------------------------------------------------------
80 
-----------------------------------------------------------------------------
81 
-- ALU and more
82 
-----------------------------------------------------------------------------
83 
-----------------------------------------------------------------------------
84 
    signal OP1in          : std_logic_vector(31 downto 0);
85 
    signal addsub_a       : std_logic_vector(31 downto 0);
86 
    signal addsub_b       : std_logic_vector(31 downto 0);
87 
    signal notaddsub_b    : std_logic_vector(33 downto 0);
88 
    signal add_result     : std_logic_vector(33 downto 0);
89 
    signal addsub_ofl     : std_logic_vector(2 downto 0);
90 
    signal opaddsub           : bit;
91 
    signal c_in           : std_logic_vector(3 downto 0);
92 
    signal flag_z         : std_logic_vector(2 downto 0);
93 
         signal set_Flags      : std_logic_vector(3 downto 0);   --NZVC
94 
         signal CCRin          : std_logic_vector(7 downto 0);
95 
 
96 
--BCD
97 
    signal bcd_pur                : std_logic_vector(9 downto 0);
98 
    signal bcd_kor                : std_logic_vector(8 downto 0);
99 
    signal halve_carry    : std_logic;
100 
    signal Vflag_a                : std_logic;
101 
    signal bcd_a_carry    : std_logic;
102 
    signal bcd_a                  : std_logic_vector(8 downto 0);
103 
    signal result_mulu    : std_logic_vector(127 downto 0);
104 
    signal result_div     : std_logic_vector(63 downto 0);
105 
    signal set_mV_Flag    : std_logic;
106 
    signal V_Flag             : bit;
107 
 
108 
         signal rot_rot        : std_logic;
109 
         signal rot_lsb        : std_logic;
110 
         signal rot_msb        : std_logic;
111 
         signal rot_X          : std_logic;
112 
         signal rot_C          : std_logic;
113 
    signal rot_out        : std_logic_vector(31 downto 0);
114 
         signal asl_VFlag      : std_logic;
115 
    signal bit_bits       : std_logic_vector(1 downto 0);
116 
    signal bit_number     : std_logic_vector(4 downto 0);
117 
    signal bits_out       : std_logic_vector(31 downto 0);
118 
    signal one_bit_in     : std_logic;
119 
    signal bchg                   : std_logic;
120 
    signal bset                   : std_logic;
121 
 
122 
    signal mulu_sign      : std_logic;
123 
    signal mulu_signext   : std_logic_vector(16 downto 0);
124 
    signal muls_msb               : std_logic;
125 
    signal mulu_reg       : std_logic_vector(63 downto 0);
126 
    signal FAsign                 : std_logic;
127 
    signal faktorA        : std_logic_vector(31 downto 0);
128 
    signal faktorB        : std_logic_vector(31 downto 0);
129 
 
130 
    signal div_reg        : std_logic_vector(63 downto 0);
131 
    signal div_quot       : std_logic_vector(63 downto 0);
132 
    signal div_ovl            : std_logic;
133 
    signal div_neg            : std_logic;
134 
    signal div_bit            : std_logic;
135 
    signal div_sub        : std_logic_vector(32 downto 0);
136 
    signal div_over       : std_logic_vector(32 downto 0);
137 
    signal nozero         : std_logic;
138 
    signal div_qsign      : std_logic;
139 
    signal divisor        : std_logic_vector(63 downto 0);
140 
    signal divs                   : std_logic;
141 
    signal signedOP       : std_logic;
142 
    signal OP1_sign               : std_logic;
143 
    signal OP2_sign       : std_logic;
144 
    signal OP2outext      : std_logic_vector(15 downto 0);
145 
 
146 
    signal in_offset        : std_logic_vector(5 downto 0);
147 
    signal datareg       : std_logic_vector(31 downto 0);
148 
    signal insert       : std_logic_vector(31 downto 0);
149 
    signal bf_datareg       : std_logic_vector(31 downto 0);
150 
    signal result           : std_logic_vector(39 downto 0);
151 
    signal result_tmp           : std_logic_vector(39 downto 0);
152 
    signal unshifted_bitmask    : std_logic_vector(31 downto 0);
153 
    signal bf_set1          : std_logic_vector(39 downto 0);
154 
    signal inmux0           : std_logic_vector(39 downto 0);
155 
    signal inmux1           : std_logic_vector(39 downto 0);
156 
    signal inmux2           : std_logic_vector(39 downto 0);
157 
    signal inmux3           : std_logic_vector(31 downto 0);
158 
    signal shifted_bitmask            : std_logic_vector(39 downto 0);
159 
    signal bitmaskmux0           : std_logic_vector(37 downto 0);
160 
    signal bitmaskmux1           : std_logic_vector(35 downto 0);
161 
    signal bitmaskmux2           : std_logic_vector(31 downto 0);
162 
    signal bitmaskmux3           : std_logic_vector(31 downto 0);
163 
    signal bf_set2          : std_logic_vector(31 downto 0);
164 
    signal shift            : std_logic_vector(39 downto 0);
165 
    signal bf_firstbit      : std_logic_vector(5 downto 0);
166 
         signal mux     : std_logic_vector(3 downto 0);
167 
    signal bitnr  : std_logic_vector(4 downto 0);
168 
    signal mask     : std_logic_vector(31 downto 0);
169 
    signal mask_not_zero  : std_logic;
170 
    signal bf_bset  : std_logic;
171 
    signal bf_NFlag  : std_logic;
172 
    signal bf_bchg  : std_logic;
173 
    signal bf_ins  : std_logic;
174 
    signal bf_exts  : std_logic;
175 
    signal bf_fffo  : std_logic;
176 
    signal bf_d32  : std_logic;
177 
    signal bf_s32  : std_logic;
178 
    signal index  : std_logic_vector(4 downto 0);
179 
--    signal i  : integer range 0 to 31;
180 
--    signal i  : integer range 0 to 31;
181 
--    signal i  : std_logic_vector(5 downto 0);
182 
 
183 
--  signal hot_bit      : std_logic_vector(33 downto 0); simulation error =>
184 
  signal hot_bit      : std_logic_vector(63 downto 0);
185 
  signal hot_msb      : std_logic_vector(32 downto 0);
186 
  signal vector       : std_logic_vector(32 downto 0);
187 
  signal result_bs    : std_logic_vector(65 downto 0);
188 
  signal bit_nr       : std_logic_vector(5 downto 0);
189 
  signal bit_nr7       : std_logic_vector(6 downto 0);
190 
  signal bit_msb      : std_logic_vector(5 downto 0);
191 
  signal bs_shift     : std_logic_vector(5 downto 0);
192 
  signal bs_shift_mod : std_logic_vector(5 downto 0);
193 
  signal asl_over     : std_logic_vector(32 downto 0);
194 
  signal asr_sign     : std_logic_vector(32 downto 0);
195 
  signal msb          : std_logic;
196 
  signal ring               : std_logic_vector(5 downto 0);
197 
  signal ALU          : std_logic_vector(31 downto 0);
198 
  signal BSout        : std_logic_vector(31 downto 0);
199 
  signal bs_V         : std_logic;
200 
  signal bs_C         : std_logic;
201 
  signal bs_X         : std_logic;
202 
 
203 
 
204 
BEGIN
205 
-----------------------------------------------------------------------------
206 
-- set OP1in
207 
-----------------------------------------------------------------------------
208 
PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
209 
             bcd_a, result_mulu, result_div, exe_condition, bf_shift, bf_ffo_offset, mulu_reg, BSout,
210 
             Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
211 
        BEGIN
212 
                ALUout <= OP1in;
213 
                ALUout(7) <= OP1in(7) OR exec_tas;
214 
                IF exec(opcBFwb)='1' THEN
215 
                        ALUout <= result(31 downto 0);
216 
--                      ALUout <= bf_datareg(31 downto 0);
217 
                        IF bf_fffo='1' THEN
218 
--                              ALUout <= (OTHERS =>'0');
219 
--                              ALUout(5 downto 0) <= bf_firstbit + bf_shift;
220 
--                              ALUout(5 downto 0) <= bf_firstbit;
221 
                                ALUout <= bf_ffo_offset - bf_firstbit;
222 
                        END IF;
223 
                END IF;
224 
 
225 
                OP1in <= addsub_q;
226 
                IF exec(opcABCD)='1' OR exec(opcSBCD)='1' THEN
227 
                        OP1in(7 downto 0) <= bcd_a(7 downto 0);
228 
                ELSIF exec(opcMULU)='1' AND MUL_Mode/=3 THEN
229 
                        IF MUL_Hardware=0 THEN
230 
                                IF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
231 
                                        OP1in <= result_mulu(31 downto 0);
232 
                                ELSE
233 
                                        OP1in <= result_mulu(63 downto 32);
234 
                                END IF;
235 
                        ELSE
236 
                                IF exec(write_lowlong)='1' THEN --AND (MUL_Mode=1 OR MUL_Mode=2) THEN
237 
                                        OP1in <= result_mulu(31 downto 0);
238 
                                ELSE
239 
--                                      OP1in <= result_mulu(63 downto 32);
240 
                                        OP1in <= mulu_reg(31 downto 0);
241 
                                END IF;
242 
                        END IF;
243 
                ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
244 
                        IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
245 
--                      IF exe_opcode(15)='1' THEN
246 
                                OP1in <= result_div(47 downto 32)&result_div(15 downto 0);
247 
                        ELSE            --64bit
248 
                                IF exec(write_reminder)='1' THEN
249 
                                        OP1in <= result_div(63 downto 32);
250 
                                ELSE
251 
                                        OP1in <= result_div(31 downto 0);
252 
                                END IF;
253 
                        END IF;
254 
                ELSIF exec(opcOR)='1' THEN
255 
                        OP1in <= OP2out OR OP1out;
256 
                ELSIF exec(opcAND)='1' THEN
257 
                        OP1in <= OP2out AND OP1out;
258 
                ELSIF exec(opcScc)='1' THEN
259 
                        OP1in(7 downto 0) <= (others=>exe_condition);
260 
                ELSIF exec(opcEOR)='1' THEN
261 
                        OP1in <= OP2out XOR OP1out;
262 
                ELSIF exec(opcMOVE)='1' OR exec(exg)='1' THEN
263 
--                      OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
264 
                        OP1in <= OP2out;
265 
                ELSIF exec(opcROT)='1' THEN
266 
                        OP1in <= rot_out;
267 
                ELSIF exec(exec_BS)='1' THEN
268 
                        OP1in <= BSout;
269 
                ELSIF exec(opcSWAP)='1' THEN
270 
                        OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
271 
                ELSIF exec(opcBITS)='1' THEN
272 
                        OP1in <= bits_out;
273 
                ELSIF exec(opcBF)='1' THEN
274 
                        OP1in <= bf_datareg;            --new bitfieldvector for bfins - for others the old bitfieldvector
275 
                ELSIF exec(opcMOVESR)='1' THEN
276 
                        OP1in(7 downto 0) <= Flags;
277 
--                      IF exe_datatype="00" THEN
278 
                        IF exe_opcode(9)='1' THEN
279 
                                OP1in(15 downto 8) <= "00000000";
280 
                        ELSE
281 
                                OP1in(15 downto 8) <= FlagsSR;
282 
                        END IF;
283 
                ELSIF exec(opcPACK)='1' THEN
284 
                        OP1in(7 downto 0) <= addsub_q(11 downto 8) & addsub_q(3 downto 0);
285 
                END IF;
286 
        END PROCESS;
287 
 
288 
-----------------------------------------------------------------------------
289 
-- addsub
290 
-----------------------------------------------------------------------------
291 
PROCESS (OP1out, OP2out, execOPC, Flags, long_start, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
292 
             notaddsub_b, add_result, c_in, sndOPC, non_aligned)
293 
        BEGIN
294 
                addsub_a <= OP1out;
295 
                IF exec(get_bfoffset)='1' THEN
296 
                        IF sndOPC(11)='1' THEN
297 
                                addsub_a <= OP1out(31)&OP1out(31)&OP1out(31)&OP1out(31 downto 3);
298 
                        ELSE
299 
                                addsub_a <= "000000000000000000000000000000"&sndOPC(10 downto 9);
300 
                        END IF;
301 
                END IF;
302 
 
303 
                IF exec(subidx)='1' THEN
304 
                        opaddsub <= '1';
305 
                ELSE
306 
                        opaddsub <= '0';
307 
                END IF;
308 
 
309 
                c_in(0) <='0';
310 
                addsub_b <= OP2out;
311 
                IF exec(opcUNPACK)='1' THEN
312 
                        addsub_b(15 downto 0) <= "0000" & OP2out(7 downto 4) & "0000" & OP2out(3 downto 0);
313 
                ELSIF execOPC='0' AND exec(OP2out_one)='0' AND exec(get_bfoffset)='0'THEN
314 
                        IF long_start='0' AND exe_datatype="00" AND exec(use_SP)='0' THEN
315 
                                addsub_b <= "00000000000000000000000000000001";
316 
                        ELSIF long_start='0' AND exe_datatype="10" AND (exec(presub) OR exec(postadd) OR movem_presub)='1' THEN
317 
                                IF exec(movem_action)='1' THEN
318 
                                        addsub_b <= "00000000000000000000000000000110";
319 
                                ELSE
320 
                                        addsub_b <= "00000000000000000000000000000100";
321 
                                END IF;
322 
                        ELSE
323 
                                addsub_b <= "00000000000000000000000000000010";
324 
                        END IF;
325 
                ELSE
326 
                        IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN
327 
                                c_in(0) <= '1';
328 
                        END IF;
329 
                        opaddsub <= exec(addsub);
330 
                END IF;
331 
 
332 
                -- patch for un-aligned movem --mikej
333 
                if (exec(movem_action) = '1') then
334 
                  if (movem_presub = '0') then -- up
335 
                        if (non_aligned = '1') and (long_start = '0') then -- hold
336 
                          addsub_b <= (others => '0');
337 
                        end if;
338 
                  else
339 
                        if (non_aligned = '1') and (long_start = '0') then
340 
                          if (exe_datatype = "10") then
341 
                                addsub_b <= "00000000000000000000000000001000";
342 
                          else
343 
                                addsub_b <= "00000000000000000000000000000100";
344 
                          end if;
345 
                        end if;
346 
                  end if;
347 
                end if;
348 
 
349 
                IF opaddsub='0' OR long_start='1' THEN           --ADD
350 
                        notaddsub_b <= '0'&addsub_b&c_in(0);
351 
                ELSE                                    --SUB
352 
                        notaddsub_b <= NOT ('0'&addsub_b&c_in(0));
353 
                END IF;
354 
                add_result <= (('0'&addsub_a&notaddsub_b(0))+notaddsub_b);
355 
                c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
356 
                c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
357 
                c_in(3) <= add_result(33);
358 
                addsub_q <= add_result(32 downto 1);
359 
                addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7));            --V Byte
360 
                addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15));        --V Word
361 
                addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31));        --V Long
362 
                c_out <= c_in(3 downto 1);
363 
        END PROCESS;
364 
 
365 
------------------------------------------------------------------------------
366 
--ALU
367 
------------------------------------------------------------------------------
368 
PROCESS (OP1out, OP2out, exec, add_result, bcd_pur, bcd_a, bcd_kor, halve_carry, c_in)
369 
        BEGIN
370 
--BCD_ARITH-------------------------------------------------------------------
371 
--04.04.2017 by Tobiflex - BCD handling with all undefined behavior!
372 
                bcd_pur <= c_in(1)&add_result(8 downto 0);
373 
                bcd_kor <= "000000000";
374 
                halve_carry <= OP1out(4) XOR OP2out(4) XOR bcd_pur(5);
375 
                IF halve_carry='1' THEN
376 
                        bcd_kor(3 downto 0) <= "0110"; --  -6
377 
                END IF;
378 
                IF bcd_pur(9)='1' THEN
379 
                        bcd_kor(7 downto 4) <= "0110"; --  -60
380 
                END IF;
381 
                IF exec(opcABCD)='1' THEN
382 
                        Vflag_a <= NOT bcd_pur(8) AND bcd_a(7);
383 
--                      bcd_pur <= ('0'&OP1out(7 downto 0)&'1') + ('0'&OP2out(7 downto 0)&Flags(4));
384 
                        bcd_a <= bcd_pur(9 downto 1) + bcd_kor;
385 
                        IF (bcd_pur(4) AND (bcd_pur(3) OR bcd_pur(2)))='1' THEN
386 
                                bcd_kor(3 downto 0) <= "0110"; --  +6
387 
                        END IF;
388 
                        IF (bcd_pur(8) AND (bcd_pur(7) OR bcd_pur(6) OR (bcd_pur(5) AND bcd_pur(4) AND (bcd_pur(3) OR bcd_pur(2)))))='1' THEN
389 
                                bcd_kor(7 downto 4) <= "0110"; --  +60
390 
                        END IF;
391 
                ELSE --opcSBCD
392 
                        Vflag_a <= bcd_pur(8) AND NOT bcd_a(7);
393 
--                      bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4));
394 
                        bcd_a <= bcd_pur(9 downto 1) - bcd_kor;
395 
                END IF;
396 
                bcd_a_carry <= bcd_pur(9) OR bcd_a(8);
397 
        END PROCESS;
398 
 
399 
-----------------------------------------------------------------------------
400 
-- Bits
401 
-----------------------------------------------------------------------------
402 
PROCESS (clk, exe_opcode, OP1out, OP2out, reg_QB, one_bit_in, bchg, bset, bit_Number, sndOPC)
403 
        BEGIN
404 
                IF rising_edge(clk) THEN
405 
                IF  clkena_lw = '1' THEN
406 
                                bchg <= '0';
407 
                                bset <= '0';
408 
                                CASE opcode(7 downto 6) IS
409 
                                        WHEN "01" =>                                    --bchg
410 
                                                bchg <= '1';
411 
                                        WHEN "11" =>                                    --bset
412 
                                                bset <= '1';
413 
                                        WHEN OTHERS => NULL;
414 
                                END CASE;
415 
                        END IF;
416 
                END IF;
417 
 
418 
                IF exe_opcode(8)='0' THEN
419 
                        IF exe_opcode(5 downto 4)="00" THEN
420 
                                bit_number <= sndOPC(4 downto 0);
421 
                        ELSE
422 
                                bit_number <= "00"&sndOPC(2 downto 0);
423 
                        END IF;
424 
                ELSE
425 
                        IF exe_opcode(5 downto 4)="00" THEN
426 
                                bit_number <= reg_QB(4 downto 0);
427 
                        ELSE
428 
                                bit_number <= "00"&reg_QB(2 downto 0);
429 
                        END IF;
430 
                END IF;
431 
 
432 
                one_bit_in <= OP1out(conv_integer(bit_Number));
433 
                bits_out <= OP1out;
434 
                bits_out(conv_integer(bit_Number)) <= (bchg AND NOT one_bit_in) OR bset ;
435 
        END PROCESS;
436 
 
437 
-----------------------------------------------------------------------------
438 
-- Bit Field
439 
-----------------------------------------------------------------------------
440 
 
441 
PROCESS (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out,
442 
                        result_tmp, bf_ext_in, mask_not_zero, exec, shift, datareg, bf_NFlag, result, reg_QB, unshifted_bitmask, bf_d32, bf_s32,
443 
                        shifted_bitmask, bf_loffset, bitmaskmux0, bitmaskmux1, bitmaskmux2, bitmaskmux3, bf_width)
444 
        BEGIN
445 
                IF rising_edge(clk) THEN
446 4 tobiflex 
                        IF clkena_lw = '1' THEN
447 2 tobiflex 
                                bf_bset <= '0';
448 
                                bf_bchg <= '0';
449 
                                bf_ins <= '0';
450 
                                bf_exts <= '0';
451 
                                bf_fffo <= '0';
452 
                                bf_d32 <= '0';
453 
                                bf_s32 <= '0';
454 5 tobiflex 
--              000-bftst, 001-bfextu, 010-bfchg, 011-bfexts, 100-bfclr, 101-bfff0, 110-bfset, 111-bfins
455 
                                IF opcode(5 downto 4) ="00" THEN
456 
                                          bf_s32 <= '1';
457 
                                END IF;
458 2 tobiflex 
                                CASE opcode(10 downto 8) IS
459 5 tobiflex 
                                        WHEN "010" => bf_bchg <= '1';                                   --BFCHG
460 
                                        WHEN "011" => bf_exts <= '1';                                   --BFEXTS
461 
--                                      WHEN "100" => insert <= (OTHERS =>'0'); --BFCLR
462 
                                        WHEN "101" => bf_fffo <= '1';                                   --BFFFO
463 
                                        WHEN "110" => bf_bset <= '1';                                   --BFSET
464 2 tobiflex 
                                        WHEN "111" => bf_ins <= '1';                                    --BFINS
465 5 tobiflex 
                                                                          bf_s32 <= '1';
466 2 tobiflex 
                                        WHEN OTHERS => NULL;
467 
                                END CASE;
468 
                                IF opcode(4 downto 3)="00" THEN
469 
                                        bf_d32 <= '1';
470 
                                END IF;
471 
                                bf_ext_out <= result(39 downto 32);
472 
                        END IF;
473 
                END IF;
474 
 
475 
                IF bf_ins='1' THEN
476 
                        datareg <= reg_QB;
477 
                ELSE
478 
                        datareg <= bf_set2;
479 
                END IF;
480 
 
481 
 
482 
-- create bitmask for operation
483 
-- unshifted bitmask '0' => bit is in the Bitfieldvector
484 
--                                       '1' => bit isn't in the Bitfieldvector
485 
-- Example bf_with=11    => "11111111 11111111 11111000 00000000"
486 
-- datareg
487 
                unshifted_bitmask <= (OTHERS => '0');
488 
                FOR i in 0 to 31 LOOP
489 
                        IF i>bf_width(4 downto 0) THEN
490 
                                datareg(i) <= '0';
491 
                                unshifted_bitmask(i) <= '1';
492 
                        END IF;
493 
                END LOOP;
494 
 
495 
                bf_NFlag <= datareg(conv_integer(bf_width));
496 
                IF bf_exts='1' AND bf_NFlag='1' THEN
497 
                        bf_datareg <= datareg OR unshifted_bitmask;
498 
                ELSE
499 
                        bf_datareg <= datareg;
500 
                END IF;
501 
--      bf_datareg <= shifted_bitmask(31 downto 4)&"0000";
502 
--      result(31 downto 0)<=datareg;
503 
 
504 
-- shift bitmask for operation
505 
                IF bf_loffset(4)='1' THEN
506 
                        bitmaskmux3 <= unshifted_bitmask(15 downto 0)&unshifted_bitmask(31 downto 16);
507 
                ELSE
508 
                        bitmaskmux3 <= unshifted_bitmask;
509 
                END IF;
510 
                IF bf_loffset(3)='1' THEN
511 
                        bitmaskmux2(31 downto 0) <= bitmaskmux3(23 downto 0)&bitmaskmux3(31 downto 24);
512 
                ELSE
513 
                        bitmaskmux2(31 downto 0) <= bitmaskmux3;
514 
                END IF;
515 
                IF bf_loffset(2)='1' THEN
516 
                        bitmaskmux1 <= bitmaskmux2&"1111";
517 
                        IF bf_d32='1' THEN
518 
                                bitmaskmux1(3 downto 0) <= bitmaskmux2(31 downto 28);
519 
                        END IF;
520 
                ELSE
521 
                        bitmaskmux1 <= "1111"&bitmaskmux2;
522 
                END IF;
523 
                IF bf_loffset(1)='1' THEN
524 
                        bitmaskmux0 <= bitmaskmux1&"11";
525 
                        IF bf_d32='1' THEN
526 
                                bitmaskmux0(1 downto 0) <= bitmaskmux1(31 downto 30);
527 
                        END IF;
528 
                ELSE
529 
                        bitmaskmux0 <= "11"&bitmaskmux1;
530 
                END IF;
531 
                IF bf_loffset(0)='1' THEN
532 
                        shifted_bitmask <= '1'&bitmaskmux0&'1';
533 
                        IF bf_d32='1' THEN
534 
                                shifted_bitmask(0) <= bitmaskmux0(31);
535 
                        END IF;
536 
                ELSE
537 
                        shifted_bitmask <= "11"&bitmaskmux0;
538 
                END IF;
539 
 
540 
 
541 
-- shift for ins
542 
                shift <= bf_ext_in&OP2out;
543 
                IF bf_s32='1' THEN
544 
                        shift(39 downto 32) <= OP2out(7 downto 0);
545 
                END IF;
546 
 
547 
                IF bf_shift(0)='1' THEN
548 
                        inmux0 <= shift(0)&shift(39 downto 1);
549 
                ELSE
550 
                        inmux0 <= shift;
551 
                END IF;
552 
                IF bf_shift(1)='1' THEN
553 
                        inmux1 <= inmux0(1 downto 0)&inmux0(39 downto 2);
554 
                ELSE
555 
                        inmux1 <= inmux0;
556 
                END IF;
557 
                IF bf_shift(2)='1' THEN
558 
                        inmux2 <= inmux1(3 downto 0)&inmux1(39 downto 4);
559 
                ELSE
560 
                        inmux2 <= inmux1;
561 
                END IF;
562 
                IF bf_shift(3)='1' THEN
563 
                        inmux3 <= inmux2(7 downto 0)&inmux2(31 downto 8);
564 
                ELSE
565 
                        inmux3 <= inmux2(31 downto 0);
566 
                END IF;
567 
                IF bf_shift(4)='1' THEN
568 
                        bf_set2(31 downto 0) <= inmux3(15 downto 0)&inmux3(31 downto 16);
569 
                ELSE
570 
                        bf_set2(31 downto 0) <= inmux3;
571 
                END IF;
572 
 
573 
                IF bf_ins='1' THEN
574 
                        result(31 downto 0) <= bf_set2;
575 
                        result(39 downto 32) <= bf_set2(7 downto 0);
576 
                ELSIF bf_bchg='1' THEN
577 
                        result(31 downto 0) <= NOT OP2out;
578 
                        result(39 downto 32) <= NOT bf_ext_in;
579 
                ELSE
580 
                        result <= (OTHERS => '0');
581 
                END IF;
582 
                IF bf_bset='1' THEN
583 
                        result <= (OTHERS => '1');
584 
                END IF;
585 
--
586 
                IF bf_ins='1' THEN
587 
                        result_tmp <= bf_ext_in&OP1out;
588 
                ELSE
589 
                        result_tmp <= bf_ext_in&OP2out;
590 
                END IF;
591 
                FOR i in 0 to 39 LOOP
592 
                        IF shifted_bitmask(i)='1' THEN
593 
                                result(i) <= result_tmp(i);   --restore old data
594 
                        END IF;
595 
                END LOOP;
596 
 
597 
--BFFFO
598 
                mask <= datareg;
599 
                bf_firstbit <= ('0'&bitnr)+mask_not_zero;
600 
                bitnr <= "11111";
601 
                mask_not_zero <= '1';
602 
                IF mask(31 downto 28)="0000" THEN
603 
                        IF mask(27 downto 24)="0000" THEN
604 
                                IF mask(23 downto 20)="0000" THEN
605 
                                        IF mask(19 downto 16)="0000" THEN
606 
                                                bitnr(4) <= '0';
607 
                                                IF mask(15 downto 12)="0000" THEN
608 
                                                        IF mask(11 downto 8)="0000" THEN
609 
                                                                bitnr(3) <= '0';
610 
                                                                IF mask(7 downto 4)="0000" THEN
611 
                                                                        bitnr(2) <= '0';
612 
                                                                        mux <= mask(3 downto 0);
613 
                                                                ELSE
614 
                                                                        mux <= mask(7 downto 4);
615 
                                                                END IF;
616 
                                                        ELSE
617 
                                                                mux <= mask(11 downto 8);
618 
                                                                bitnr(2) <= '0';
619 
                                                        END IF;
620 
                                                ELSE
621 
                                                        mux <= mask(15 downto 12);
622 
                                                END IF;
623 
                                        ELSE
624 
                                                mux <= mask(19 downto 16);
625 
                                                bitnr(3) <= '0';
626 
                                                bitnr(2) <= '0';
627 
                                        END IF;
628 
                                ELSE
629 
                                        mux <= mask(23 downto 20);
630 
                                        bitnr(3) <= '0';
631 
                                END IF;
632 
                        ELSE
633 
                                mux <= mask(27 downto 24);
634 
                                bitnr(2) <= '0';
635 
                        END IF;
636 
                ELSE
637 
                        mux <= mask(31 downto 28);
638 
                END IF;
639 
 
640 
                IF mux(3 downto 2)="00" THEN
641 
                        bitnr(1) <= '0';
642 
                        IF mux(1)='0' THEN
643 
                                bitnr(0) <= '0';
644 
                                IF mux(0)='0' THEN
645 
                                        mask_not_zero <= '0';
646 
                                END IF;
647 
                        END IF;
648 
                ELSE
649 
                        IF mux(3)='0' THEN
650 
                                bitnr(0) <= '0';
651 
                        END IF;
652 
                END  IF;
653 
        END PROCESS;
654 
 
655 
-----------------------------------------------------------------------------
656 
-- Rotation
657 
-----------------------------------------------------------------------------
658 
PROCESS (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec, BSout)
659 
        BEGIN
660 
                CASE exe_opcode(7 downto 6) IS
661 
                        WHEN "00" =>                                    --Byte
662 
                                                rot_rot <= OP1out(7);
663 
                        WHEN "01"|"11" =>                               --Word
664 
                                                rot_rot <= OP1out(15);
665 
                        WHEN "10" =>                                    --Long
666 
                                                rot_rot <= OP1out(31);
667 
                        WHEN OTHERS => NULL;
668 
                END CASE;
669 
 
670 
                CASE rot_bits IS
671 
                        WHEN "00" =>                                    --ASL, ASR
672 
                                                rot_lsb <= '0';
673 
                                                rot_msb <= rot_rot;
674 
                        WHEN "01" =>                                    --LSL, LSR
675 
                                                rot_lsb <= '0';
676 
                                                rot_msb <= '0';
677 
                        WHEN "10" =>                                    --ROXL, ROXR
678 
                                                rot_lsb <= Flags(4);
679 
                                                rot_msb <= Flags(4);
680 
                        WHEN "11" =>                                    --ROL, ROR
681 
                                                rot_lsb <= rot_rot;
682 
                                                rot_msb <= OP1out(0);
683 
                        WHEN OTHERS => NULL;
684 
                END CASE;
685 
 
686 
                IF exec(rot_nop)='1' THEN
687 
                        rot_out <= OP1out;
688 
                        rot_X <= Flags(4);
689 
                        IF rot_bits="10" THEN   --ROXL, ROXR
690 
                                rot_C <= Flags(4);
691 
                        ELSE
692 
                                rot_C <= '0';
693 
                        END IF;
694 
                ELSE
695 
                        IF exe_opcode(8)='1' THEN               --left
696 
                                rot_out <= OP1out(30 downto 0)&rot_lsb;
697 
                                rot_X <= rot_rot;
698 
                                rot_C <= rot_rot;
699 
                        ELSE                                            --right
700 
                                rot_X <= OP1out(0);
701 
                                rot_C <= OP1out(0);
702 
                                rot_out <= rot_msb&OP1out(31 downto 1);
703 
                                CASE exe_opcode(7 downto 6) IS
704 
                                        WHEN "00" =>                                    --Byte
705 
                                                rot_out(7) <= rot_msb;
706 
                                        WHEN "01"|"11" =>                               --Word
707 
                                                rot_out(15) <= rot_msb;
708 
                                        WHEN OTHERS => NULL;
709 
                                END CASE;
710 
                        END IF;
711 
                        IF BarrelShifter/=0 THEN
712 
                           rot_out <= BSout;
713 
                        END IF;
714 
                END IF;
715 
        END PROCESS;
716 
 
717 
-----------------------------------------------------------------------------
718 
-- Barrel Shifter
719 
-----------------------------------------------------------------------------
720 
process (OP1out, OP2out, opcode, bit_nr, bit_nr7, bit_msb, hot_bit, bs_shift, bs_shift_mod, ring, result_bs, exe_opcode, vector,
721 
         rot_bits, Flags, msb, hot_msb, asl_over, ALU, asr_sign, exec)
722 
        begin
723 
                ring <= "100000";
724 
                IF rot_bits="10" THEN --ROX L/R
725 
                        CASE exe_opcode(7 downto 6) IS
726 
                                WHEN "00" =>                                    --Byte
727 
                                                        ring <= "001001";
728 
                                WHEN "01"|"11" =>                               --Word
729 
                                                        ring <= "010001";
730 
                                WHEN "10" =>                                    --Long
731 
                                                        ring <= "100001";
732 
                                WHEN OTHERS => NULL;
733 
                        END CASE;
734 
                ELSE
735 
                        CASE exe_opcode(7 downto 6) IS
736 
                                WHEN "00" =>                                    --Byte
737 
                                                        ring <= "001000";
738 
                                WHEN "01"|"11" =>                               --Word
739 
                                                        ring <= "010000";
740 
                                WHEN "10" =>                                    --Long
741 
                                                        ring <= "100000";
742 
                                WHEN OTHERS => NULL;
743 
                        END CASE;
744 
                END IF;
745 
 
746 
                IF exe_opcode(7 downto 6)="11" OR exec(exec_BS)='0' THEN
747 
                        bs_shift <="000001";
748 
                ELSIF exe_opcode(5)='1' THEN
749 
                        bs_shift <= OP2out(5 downto 0);
750 
                ELSE
751 
                        bs_shift(2 downto 0) <= exe_opcode(11 downto 9);
752 
                        IF exe_opcode(11 downto 9)="000" THEN
753 
                                bs_shift(5 downto 3) <="001";
754 
                        ELSE
755 
                                bs_shift(5 downto 3) <="000";
756 
                        END IF;
757 
                END IF;
758 
 
759 
                bs_shift_mod <= std_logic_vector(unsigned(bs_shift) rem unsigned(ring));
760 
 
761 
                bit_nr <= bs_shift_mod(5 downto 0);
762 
                bit_nr7 <= ('1'&ring)-('0'&bs_shift_mod);
763 
                IF exe_opcode(8)='0' THEN  --right shift
764 
                        bit_nr <= bit_nr7(5 downto 0);
765 
                END IF;
766 
                IF rot_bits(1)='0' THEN --only shift
767 
                        IF unsigned(bs_shift)<33 THEN
768 
                                IF exe_opcode(8)='0' THEN  --right shift
769 
                                        bit_nr <= 32-bs_shift;
770 
                                ELSE
771 
                                        bit_nr <= bs_shift;
772 
                                END IF;
773 
                        ELSE
774 
                                bit_nr <= "100001";
775 
                                bit_msb <= "000000";
776 
                        END IF;
777 
                END IF;
778 
 
779 
 
780 
-- calc V-Flag by ASL
781 
                hot_msb <= (OTHERS =>'0');
782 
                hot_msb(conv_integer(bit_msb)) <= '1';
783 
                if bs_shift > ring then
784 
                   bit_msb <= "000000";
785 
                else
786 
                        bit_msb <= ring-bs_shift;
787 
                end if;
788 
                asl_over <= ((('0'&vector(30 downto 0)) XOR ('0'&vector(31 downto 1)))&'0') - ('0'&hot_msb(31 downto 0));
789 
                bs_V <= '0';
790 
                IF rot_bits="00" AND exe_opcode(8)='1' THEN --ASL
791 
                        bs_V <= not asl_over(32);
792 
                END IF;
793 
 
794 
                IF exe_opcode(8)='0' THEN --right shift
795 
                        bs_C <= result_bs(31);
796 
                        bs_X <= result_bs(31);
797 
                ELSE                  --left shift
798 
                        CASE exe_opcode(7 downto 6) IS
799 
                                WHEN "00" =>                                    --Byte
800 
                                        bs_C <= result_bs(8);
801 
                                        bs_X <= result_bs(8);
802 
                                WHEN "01"|"11" =>                               --Word
803 
                                        bs_C <= result_bs(16);
804 
                                        bs_X <= result_bs(16);
805 
                                WHEN "10" =>                                    --Long
806 
                                        bs_C <= result_bs(32);
807 
                                        bs_X <= result_bs(32);
808 
                                WHEN OTHERS => NULL;
809 
                        END CASE;
810 
                END IF;
811 
 
812 
                ALU <= (others=>'-');
813 
                IF rot_bits="11" THEN --RO L/R
814 
                        bs_X <= Flags(4);
815 
                        CASE exe_opcode(7 downto 6) IS
816 
                                WHEN "00" =>                                    --Byte
817 
                                        ALU(7 downto 0) <= result_bs(7 downto 0) OR result_bs(15 downto 8);
818 
                              bs_C <= ALU(7);
819 
                                WHEN "01"|"11" =>                               --Word
820 
                                        ALU(15 downto 0) <= result_bs(15 downto 0) OR result_bs(31 downto 16);
821 
                              bs_C <= ALU(15);
822 
                                WHEN "10" =>                                    --Long
823 
                                        ALU <= result_bs(31 downto 0) OR result_bs(63 downto 32);
824 
                              bs_C <= ALU(31);
825 
                                WHEN OTHERS => NULL;
826 
                        END CASE;
827 
                        IF exe_opcode(0)='1' THEN --left shift
828 
                                bs_C <= ALU(0);
829 
                        END IF;
830 
                ELSIF rot_bits="10" THEN --ROX L/R
831 
                        CASE exe_opcode(7 downto 6) IS
832 
                                WHEN "00" =>                                    --Byte
833 
                                        ALU(7 downto 0) <= result_bs(7 downto 0) OR result_bs(16 downto 9);
834 
                                        bs_C <= result_bs(8) OR result_bs(17);
835 
                                        bs_X <= result_bs(8) OR result_bs(17);
836 
                                WHEN "01"|"11" =>                               --Word
837 
                                        ALU(15 downto 0) <= result_bs(15 downto 0) OR result_bs(32 downto 17);
838 
                                        bs_C <= result_bs(16) OR result_bs(33);
839 
                                        bs_X <= result_bs(16) OR result_bs(33);
840 
                                WHEN "10" =>                                    --Long
841 
                                        ALU <= result_bs(31 downto 0) OR result_bs(64 downto 33);
842 
                                        bs_C <= result_bs(32) OR result_bs(65);
843 
                                        bs_X <= result_bs(32) OR result_bs(65);
844 
                                WHEN OTHERS => NULL;
845 
                        END CASE;
846 
                ELSE
847 
                        IF exe_opcode(8)='0' THEN --right shift
848 
                                ALU <= result_bs(63 downto 32);
849 
                        ELSE                  --left shift
850 
                                ALU <= result_bs(31 downto 0);
851 
                        END IF;
852 
                END IF;
853 
 
854 
                IF(bs_shift = "000000") THEN
855 
                        IF rot_bits="10" THEN --ROX L/R
856 
                          bs_C <= Flags(4);
857 
                        ELSE
858 
                          bs_C <= '0';
859 
                        END IF;
860 
                        bs_X <= Flags(4);
861 
                        bs_V <= '0';
862 
                END IF;
863 
 
864 
-- calc ASR sign
865 
                BSout <= ALU;
866 
                asr_sign <= (OTHERS =>'0');
867 
                asr_sign(32 downto 1) <= asr_sign(31 downto 0) OR hot_msb(31 downto 0);
868 
--              IF opcode(2 downto 0)="000" AND msb='1' THEN --ASR
869 
                IF rot_bits="00" AND exe_opcode(8)='0' AND msb='1' THEN --ASR
870 
                        BSout <= ALU or asr_sign(32 downto 1);
871 
                        IF bs_shift > ring THEN
872 
                                bs_C <= '1';
873 
                                bs_X <= '1';
874 
                        END IF;
875 
                END IF;
876 
 
877 
                vector(32 downto 0) <= '0'&OP1out;
878 
                CASE exe_opcode(7 downto 6) IS
879 
                        WHEN "00" =>                                    --Byte
880 
                                msb <= OP1out(7);
881 
                                vector(31 downto 8) <= X"000000";
882 
                                BSout(31 downto 8) <= X"000000";
883 
                                IF rot_bits="10" THEN --ROX L/R
884 
                                        vector(8) <= Flags(4);
885 
                                END IF;
886 
                        WHEN "01"|"11" =>                               --Word
887 
                                msb <= OP1out(15);
888 
                                vector(31 downto 16) <= X"0000";
889 
                                BSout(31 downto 16) <= X"0000";
890 
                                IF rot_bits="10" THEN --ROX L/R
891 
                                        vector(16) <= Flags(4);
892 
                                END IF;
893 
                        WHEN "10" =>                                    --Long
894 
                                msb <= OP1out(31);
895 
                                IF rot_bits="10" THEN --ROX L/R
896 
                                        vector(32) <= Flags(4);
897 
                                END IF;
898 
                        WHEN OTHERS => NULL;
899 
                END CASE;
900 
 
901 
                hot_bit <= (OTHERS =>'0');
902 
                hot_bit(conv_integer(bit_nr(5 downto 0))) <= '1';
903 
                result_bs <= vector * hot_bit(32 downto 0);
904 
-- if you don't like to use the multiplier -> uncommend next line       and commend the lines before
905 
--              result_bs <= std_logic_vector(unsigned('0'&X"00000000"&vector) sll to_integer(unsigned(bit_nr(5 downto 0))));
906 
 
907 
  end process;
908 
 
909 
 
910 
------------------------------------------------------------------------------
911 
--CCR op
912 
------------------------------------------------------------------------------
913 
PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1IN, c_out, addsub_ofl,
914 
             bcd_a, bcd_a_carry, Vflag_a, exec)
915 
        BEGIN
916 
                IF exec(andiSR)='1' THEN
917 
                        CCRin <= Flags AND last_data_read(7 downto 0);
918 
                ELSIF exec(eoriSR)='1' THEN
919 
                        CCRin <= Flags XOR last_data_read(7 downto 0);
920 
                ELSIF exec(oriSR)='1' THEN
921 
                        CCRin <= Flags OR last_data_read(7 downto 0);
922 
                ELSE
923 
                        CCRin <= OP2out(7 downto 0);
924 
                END IF;
925 
 
926 
------------------------------------------------------------------------------
927 
--Flags
928 
------------------------------------------------------------------------------
929 
                flag_z <= "000";
930 
                IF exec(use_XZFlag)='1' AND flags(2)='0' THEN
931 
                        flag_z <= "000";
932 
                ELSIF OP1in(7 downto 0)="00000000" THEN
933 
                        flag_z(0) <= '1';
934 
                        IF OP1in(15 downto 8)="00000000" THEN
935 
                                flag_z(1) <= '1';
936 
                                IF OP1in(31 downto 16)="0000000000000000" THEN
937 
                                        flag_z(2) <= '1';
938 
                                END IF;
939 
                        END IF;
940 
                END IF;
941 
 
942 
--                                      --Flags NZVC
943 
                IF exe_datatype="00" THEN                                               --Byte
944 
                        set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
945 
                        IF exec(opcABCD)='1' OR exec(opcSBCD)='1' THEN
946 
                                set_flags(0) <= bcd_a_carry;
947 
                                set_flags(1) <= Vflag_a;
948 
                        END IF;
949 
                ELSIF exe_datatype="10" OR exec(opcCPMAW)='1' THEN                                              --Long
950 
                        set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
951 
                ELSE                                            --Word
952 
                        set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
953 
                END IF;
954 
 
955 
                IF rising_edge(clk) THEN
956 4 tobiflex 
                IF Reset='1' THEN
957 
                                Flags(7 downto 0) <= "00000000";
958 
                ELSIF clkena_lw = '1' THEN
959 2 tobiflex 
                                IF exec(directSR)='1' OR set_stop='1' THEN
960 
                                        Flags(7 downto 0) <= data_read(7 downto 0);
961 
                                END IF;
962 
                                IF exec(directCCR)='1' THEN
963 
                                        Flags(7 downto 0) <= data_read(7 downto 0);
964 
                                END IF;
965 
 
966 
                                IF exec(opcROT)='1' AND decodeOPC='0' THEN
967 
                                        asl_VFlag <= ((set_flags(3) XOR rot_rot) OR asl_VFlag);
968 
                                ELSE
969 
                                        asl_VFlag <= '0';
970 
                                END IF;
971 
                                IF exec(to_CCR)='1' THEN
972 
                                        Flags(7 downto 0) <= CCRin(7 downto 0);                   --CCR
973 
                                ELSIF Z_error='1' THEN
974 
                                        IF exe_opcode(8)='0' THEN
975 
--                                              Flags(3 downto 0) <= reg_QA(31)&"000";
976 
                                                Flags(3 downto 0) <= '0'&NOT reg_QA(31)&"00";
977 
                                        ELSE
978 
                                                Flags(3 downto 0) <= "0100";
979 
                                        END IF;
980 
                                ELSIF exec(no_Flags)='0' THEN
981 
                                        IF exec(opcADD)='1' THEN
982 
                                                Flags(4) <= set_flags(0);
983 
                                        ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
984 
                                                Flags(4) <= rot_X;
985 
                                        ELSIF exec(exec_BS)='1' THEN
986 
                                                Flags(4) <= BS_X;
987 
                                        END IF;
988 
 
989 
                                        IF (exec(opcADD) OR exec(opcCMP))='1' THEN
990 
                                                Flags(3 downto 0) <= set_flags;
991 
                                        ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
992 
                                                IF V_Flag='1' THEN
993 
                                                        Flags(3 downto 0) <= "1010";
994 
                                                ELSE
995 
                                                        Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
996 
                                                END IF;
997 
                                        ELSIF exec(write_reminder)='1' AND MUL_Mode/=3 THEN -- z-flag MULU.l
998 
                                                Flags(3) <= set_flags(3);
999 
                                                Flags(2) <= set_flags(2) AND Flags(2);
1000 
                                                Flags(1) <= '0';
1001 
                                                Flags(0) <= '0';
1002 
                                        ELSIF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN  -- flag MULU.l
1003 
                                                Flags(3) <= set_flags(3);
1004 
                                                Flags(2) <= set_flags(2);
1005 
                                                Flags(1) <= set_mV_Flag;        --V
1006 
                                                Flags(0) <= '0';
1007 
                                        ELSIF exec(opcOR)='1' OR exec(opcAND)='1' OR exec(opcEOR)='1' OR exec(opcMOVE)='1' OR exec(opcMOVEQ)='1' OR exec(opcSWAP)='1' OR exec(opcBF)='1' OR (exec(opcMULU)='1' AND MUL_Mode/=3) THEN
1008 
                                                Flags(1 downto 0) <= "00";
1009 
                                                Flags(3 downto 2) <= set_flags(3 downto 2);
1010 
                                                IF exec(opcBF)='1' THEN
1011 
                                                        Flags(3) <= bf_NFlag;
1012 
                                                END IF;
1013 
                                        ELSIF exec(opcROT)='1' THEN
1014 
                                                Flags(3 downto 2) <= set_flags(3 downto 2);
1015 
                                                Flags(0) <= rot_C;
1016 
                                                IF rot_bits="00" AND ((set_flags(3) XOR rot_rot) OR asl_VFlag)='1' THEN         --ASL/ASR
1017 
                                                        Flags(1) <= '1';
1018 
                                                ELSE
1019 
                                                        Flags(1) <= '0';
1020 
                                                END IF;
1021 
                                        ELSIF exec(exec_BS)='1' THEN
1022 
                                                Flags(3 downto 2) <= set_flags(3 downto 2);
1023 
                                                Flags(0) <= BS_C;
1024 
                                                Flags(1) <= BS_V;
1025 
                                        ELSIF exec(opcBITS)='1' THEN
1026 
                                                Flags(2) <= NOT one_bit_in;
1027 
                                        ELSIF exec(opcCHK)='1' THEN
1028 
                                                IF exe_datatype="01" THEN                                               --Word
1029 
                                                        Flags(3) <= OP1out(15);
1030 
                                                ELSE
1031 
                                                        Flags(3) <= OP1out(31);
1032 
                                                END IF;
1033 
                                                IF OP1out(15 downto 0)=X"0000" AND (exe_datatype="01" OR OP1out(31 downto 16)=X"0000") THEN
1034 
                                                        Flags(2) <='1';
1035 
                                                ELSE
1036 
                                                        Flags(2) <='0';
1037 
                                                END IF;
1038 
                                                Flags(1 downto 0) <= "00";
1039 
                                        END IF;
1040 
                                END IF;
1041 
                        END IF;
1042 
                        Flags(7 downto 5) <= "000";
1043 
                END IF;
1044 
        END PROCESS;
1045 
 
1046 
---------------------------------------------------------------------------------
1047 
------ MULU/MULS
1048 
---------------------------------------------------------------------------------
1049 
PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorA, faktorB, result_mulu, signedOP)
1050 
--PROCESS (exec, reg_QA, OP2out, faktorA, faktorB, signedOP)
1051 
        BEGIN
1052 
        IF MUL_Hardware=1 THEN
1053 
--              IF exe_opcode(15)='1' OR MUL_Mode=0 THEN        -- 16 Bit
1054 
                IF MUL_Mode=0 THEN       -- 16 Bit
1055 
                        IF signedOP='1' AND reg_QA(15)='1' THEN
1056 
                                faktorA <= X"FFFFFFFF";
1057 
                        ELSE
1058 
                                faktorA <= X"00000000";
1059 
                        END IF;
1060 
                        IF signedOP='1' AND OP2out(15)='1' THEN
1061 
                                faktorB <= X"FFFFFFFF";
1062 
                        ELSE
1063 
                                faktorB <= X"00000000";
1064 
                        END IF;
1065 
                        result_mulu(63 downto 0) <= (faktorA(15 downto 0) & reg_QA(15 downto 0)) * (faktorB(15 downto 0) & OP2out(15 downto 0));
1066 
                ELSE
1067 
                        IF exe_opcode(15)='1' THEN      -- 16 Bit
1068 
                                IF signedOP='1' AND reg_QA(15)='1' THEN
1069 
                                        faktorA <= X"FFFFFFFF";
1070 
                                ELSE
1071 
                                        faktorA <= X"00000000";
1072 
                                END IF;
1073 
                                IF signedOP='1' AND OP2out(15)='1' THEN
1074 
                                        faktorB <= X"FFFFFFFF";
1075 
                                ELSE
1076 
                                        faktorB <= X"00000000";
1077 
                                END IF;
1078 
                        ELSE
1079 
                                faktorA(15 downto 0) <= reg_QA(31 downto 16);
1080 
                                faktorB(15 downto 0) <= OP2out(31 downto 16);
1081 
                                IF signedOP='1' AND reg_QA(31)='1' THEN
1082 
                                        faktorA(31 downto 16) <= X"FFFF";
1083 
                                ELSE
1084 
                                        faktorA(31 downto 16) <= X"0000";
1085 
                                END IF;
1086 
                                IF signedOP='1' AND OP2out(31)='1' THEN
1087 
                                        faktorB(31 downto 16) <= X"FFFF";
1088 
                                ELSE
1089 
                                        faktorB(31 downto 16) <= X"0000";
1090 
                                END IF;
1091 
                        END IF;
1092 
                        result_mulu(127 downto 0) <= (faktorA(31 downto 16) & faktorA(31 downto 0) & reg_QA(15 downto 0)) * (faktorB(31 downto 16) & faktorB(31 downto 0) & OP2out(15 downto 0));
1093 
                END IF;
1094 
--      END PROCESS;
1095 
-------------------------------------------------------------------------------
1096 
---- MULU/MULS
1097 
-------------------------------------------------------------------------------
1098 
--PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
1099 
--      BEGIN
1100 
        ELSE
1101 
                IF (signedOP='1' AND faktorB(31)='1') OR FAsign='1' THEN
1102 
                        muls_msb <= mulu_reg(63);
1103 
                ELSE
1104 
                        muls_msb <= '0';
1105 
                END IF;
1106 
 
1107 
                IF signedOP='1' AND faktorB(31)='1' THEN
1108 
                        mulu_sign <= '1';
1109 
                ELSE
1110 
                        mulu_sign <= '0';
1111 
                END IF;
1112 
 
1113 
                IF MUL_Mode=0 THEN       -- 16 Bit
1114 
                        result_mulu(63 downto 32) <= muls_msb&mulu_reg(63 downto 33);
1115 
                        result_mulu(15 downto 0) <= 'X'&mulu_reg(15 downto 1);
1116 
                        IF mulu_reg(0)='1' THEN
1117 
                                IF FAsign='1' THEN
1118 
                                        result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)-(mulu_sign&faktorB(31 downto 16)));
1119 
                                ELSE
1120 
                                        result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)+(mulu_sign&faktorB(31 downto 16)));
1121 
                                END IF;
1122 
                        END IF;
1123 
                ELSE                            -- 32 Bit
1124 
                        result_mulu(63 downto 0) <= muls_msb&mulu_reg(63 downto 1);
1125 
                        IF mulu_reg(0)='1' THEN
1126 
                                IF FAsign='1' THEN
1127 
                                        result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)-(mulu_sign&faktorB));
1128 
                                ELSE
1129 
                                        result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)+(mulu_sign&faktorB));
1130 
                                END IF;
1131 
                        END IF;
1132 
                END IF;
1133 
                IF exe_opcode(15)='1' OR MUL_Mode=0 THEN
1134 
                        faktorB(31 downto 16) <= OP2out(15 downto 0);
1135 
                        faktorB(15 downto 0) <= (OTHERS=>'0');
1136 
                ELSE
1137 
                        faktorB <= OP2out;
1138 
                END IF;
1139 
        END IF;
1140 
                IF (result_mulu(63 downto 32)=X"00000000" AND (signedOP='0' OR result_mulu(31)='0')) OR
1141 
                        (result_mulu(63 downto 32)=X"FFFFFFFF" AND signedOP='1' AND result_mulu(31)='1') THEN
1142 
                        set_mV_Flag <= '0';
1143 
                ELSE
1144 
                        set_mV_Flag <= '1';
1145 
                END IF;
1146 
        END PROCESS;
1147 
 
1148 
PROCESS (clk)
1149 
        BEGIN
1150 
                IF rising_edge(clk) THEN
1151 
                        IF clkena_lw='1' THEN
1152 
                                IF MUL_Hardware=0 THEN
1153 
                                        IF micro_state=mul1 THEN
1154 
                                                mulu_reg(63 downto 32) <= (OTHERS=>'0');
1155 
                                                IF divs='1' AND ((exe_opcode(15)='1' AND reg_QA(15)='1') OR (exe_opcode(15)='0' AND reg_QA(31)='1')) THEN                                --MULS Neg faktor
1156 
                                                        FAsign <= '1';
1157 
                                                        mulu_reg(31 downto 0) <= 0-reg_QA;
1158 
                                                ELSE
1159 
                                                        FAsign <= '0';
1160 
                                                        mulu_reg(31 downto 0) <= reg_QA;
1161 
                                                END IF;
1162 
                                        ELSIF exec(opcMULU)='0' THEN
1163 
                                                mulu_reg(63 downto 32) <= (OTHERS=>'-');
1164 
                                                mulu_reg <= result_mulu(63 downto 0);
1165 
                                        END IF;
1166 
                                ELSE
1167 
                                        mulu_reg(31 downto 0) <= result_mulu(63 downto 32);
1168 
                                END IF;
1169 
                        END IF;
1170 
                END IF;
1171 
        END PROCESS;
1172 
 
1173 
-------------------------------------------------------------------------------
1174 
---- DIVU/DIVS
1175 
-------------------------------------------------------------------------------
1176 
 
1177 
PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
1178 
             signedOP, nozero, div_qsign, OP2outext)
1179 
        BEGIN
1180 
                divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
1181 
                divisor(15 downto 0) <= (OTHERS=> '0');
1182 
                divisor(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
1183 
                IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
1184 
                        divisor(47 downto 16) <= reg_QA;
1185 
                ELSE
1186 
                        divisor(31 downto 0) <= reg_QA;
1187 
                        IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
1188 
                                divisor(63 downto 32) <= reg_QB;
1189 
                        END IF;
1190 
                END IF;
1191 
                IF signedOP='1' OR opcode(15)='0' THEN
1192 
                        OP2outext <= OP2out(31 downto 16);
1193 
                ELSE
1194 
                        OP2outext <= (OTHERS=> '0');
1195 
                END IF;
1196 
                IF signedOP='1' AND OP2out(31) ='1' THEN
1197 
                        div_sub <= (div_reg(63 downto 31))+('1'&OP2out(31 downto 0));
1198 
                ELSE
1199 
                        div_sub <= (div_reg(63 downto 31))-('0'&OP2outext(15 downto 0)&OP2out(15 downto 0));
1200 
                END IF;
1201 
                IF DIV_Mode=0 THEN
1202 
                        div_bit <= div_sub(16);
1203 
                ELSE
1204 
                        div_bit <= div_sub(32);
1205 
                END IF;
1206 
                IF div_bit='1' THEN
1207 
                        div_quot(63 downto 32) <= div_reg(62 downto 31);
1208 
                ELSE
1209 
                        div_quot(63 downto 32) <= div_sub(31 downto 0);
1210 
                END IF;
1211 
                div_quot(31 downto 0) <= div_reg(30 downto 0)&NOT div_bit;
1212 
 
1213 
 
1214 
                IF ((nozero='1' AND signedOP='1' AND (OP2out(31) XOR OP1_sign XOR div_neg XOR div_qsign)='1' )  --Overflow DIVS
1215 
                        OR (signedOP='0' AND div_over(32)='0')) AND DIV_Mode/=3 THEN      --Overflow DIVU
1216 
                        set_V_Flag <= '1';
1217 
                ELSE
1218 
                        set_V_Flag <= '0';
1219 
                END IF;
1220 
        END PROCESS;
1221 
 
1222 
PROCESS (clk)
1223 
        BEGIN
1224 
                IF rising_edge(clk) THEN
1225 
                        IF clkena_lw='1' THEN
1226 
                                V_Flag <= set_V_Flag;
1227 
                                signedOP <= divs;
1228 
                                IF micro_state=div1 THEN
1229 
                                        nozero <= '0';
1230 
                                        IF divs='1' AND divisor(63)='1' THEN                            -- Neg divisor
1231 
                                                OP1_sign <= '1';
1232 
                                                div_reg <= 0-divisor;
1233 
                                        ELSE
1234 
                                                OP1_sign <= '0';
1235 
                                                div_reg <= divisor;
1236 
                                        END IF;
1237 
                                ELSE
1238 
                                        div_reg <= div_quot;
1239 
                                        nozero <= NOT div_bit OR nozero;
1240 
                                END IF;
1241 
                                IF micro_state=div2 THEN
1242 
                                        div_qsign <= NOT div_bit;
1243 
                                        div_neg <= signedOP AND (OP2out(31) XOR OP1_sign);
1244 
                                        IF DIV_Mode=0 THEN
1245 
                                                div_over(32 downto 16) <= ('0'&div_reg(47 downto 32))-('0'&OP2out(15 downto 0));
1246 
                                        ELSE
1247 
                                                div_over <= ('0'&div_reg(63 downto 32))-('0'&OP2out);
1248 
                                        END IF;
1249 
                                END IF;
1250 
                                IF exec(write_reminder)='0' THEN
1251 
--                              IF exec_DIVU='0' THEN
1252 
                                        IF div_neg='1' THEN
1253 
                                                result_div(31 downto 0) <= 0-div_quot(31 downto 0);
1254 
                                        ELSE
1255 
                                                result_div(31 downto 0) <= div_quot(31 downto 0);
1256 
                                        END IF;
1257 
 
1258 
                                        IF OP1_sign='1' THEN
1259 
                                                result_div(63 downto 32) <= 0-div_quot(63 downto 32);
1260 
                                        ELSE
1261 
                                                result_div(63 downto 32) <= div_quot(63 downto 32);
1262 
                                        END IF;
1263 
                                END IF;
1264 
                        END IF;
1265 
                END IF;
1266 
        END PROCESS;
1267 
END;

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