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[/] [tg68kc/] [trunk/] [TG68KdotC_Kernel.vhd] - Blame information for rev 2

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1 2 tobiflex 
------------------------------------------------------------------------------
2 
------------------------------------------------------------------------------
3 
--                                                                          --
4 
-- Copyright (c) 2009-2018 Tobias Gubener                                   --
5 
-- Subdesign fAMpIGA by TobiFlex                                            --
6 
-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ...                          --
7 
--                                                                          --
8 
-- This source file is free software: you can redistribute it and/or modify --
9 
-- it under the terms of the GNU Lesser General Public License as published --
10 
-- by the Free Software Foundation, either version 3 of the License, or     --
11 
-- (at your option) any later version.                                      --
12 
--                                                                          --
13 
-- This source file is distributed in the hope that it will be useful,      --
14 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of           --
15 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --
16 
-- GNU General Public License for more details.                             --
17 
--                                                                          --
18 
-- You should have received a copy of the GNU General Public License        --
19 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --
20 
--                                                                          --
21 
------------------------------------------------------------------------------
22 
------------------------------------------------------------------------------
23 
 
24 
-- 05.12.2018 TG insert RTD opcode
25 
-- 03.12.2018 TG insert barrel shifter
26 
-- 01.11.2017 TG bugfix V-Flag for ASL/ASR - thanks Peter Graf
27 
-- 29.05.2017 TG decode 0x4AFB as illegal, needed for QL BKP - thanks Peter Graf
28 
-- 21.05.2017 TG insert generic for hardware multiplier for MULU & MULS
29 
-- 04.04.2017 TG change GPL to LGPL
30 
-- 04.04.2017 TG BCD handling with all undefined behavior!
31 
-- 02.04.2017 TG bugfix Bitfield Opcodes
32 
-- 19.03.2017 TG insert PACK/UNPACK
33 
-- 19.03.2017 TG bugfix CMPI ...(PC) - thanks Till Harbaum
34 
--     ???    MJ bugfix non_aligned movem access
35 
-- add berr handling 10.03.2013 - needed for ATARI Core
36 
 
37 
-- bugfix session 07/08.Feb.2013
38 
-- movem ,-(an)
39 
-- movem (an)+,          - thanks  Gerhard Suttner
40 
-- btst dn,#data         - thanks  Peter Graf
41 
-- movep                 - thanks  Till Harbaum
42 
-- IPL vector            - thanks  Till Harbaum
43 
--
44 
 
45 
-- optimize Register file
46 
 
47 
-- to do 68010:
48 
-- (MOVEC)
49 
-- BKPT
50 
-- MOVES
51 
--
52 
-- to do 68020:
53 
-- (CALLM)
54 
-- (RETM)
55 
 
56 
-- CAS, CAS2
57 
-- CHK2
58 
-- CMP2
59 
-- cpXXX Coprozessor stuff
60 
-- TRAPcc
61 
 
62 
-- done 020:
63 
-- PACK
64 
-- UNPK
65 
-- Bitfields
66 
-- address modes
67 
-- long bra
68 
-- DIVS.L, DIVU.L
69 
-- LINK long
70 
-- MULS.L, MULU.L
71 
-- extb.l
72 
 
73 
library ieee;
74 
use ieee.std_logic_1164.all;
75 
use ieee.std_logic_unsigned.all;
76 
use work.TG68K_Pack.all;
77 
 
78 
entity TG68KdotC_Kernel is
79 
        generic(
80 
                SR_Read : integer:= 1;         --0=>user,   1=>privileged,      2=>switchable with CPU(0)
81 
                VBR_Stackframe : integer:= 1;  --0=>no,     1=>yes/extended,    2=>switchable with CPU(0)
82 
                extAddr_Mode : integer:= 1;    --0=>no,     1=>yes,    2=>switchable with CPU(1)
83 
                MUL_Mode : integer := 1;           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no MUL,
84 
                MUL_Hardware : integer := 1;   --0=>no,         1=>yes,
85 
                DIV_Mode : integer := 1;           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no DIV,
86 
                BarrelShifter : integer := 2;  --0=>no,     1=>yes,    2=>switchable with CPU(1)
87 
                BitField : integer := 1            --0=>no,     1=>yes,    2=>switchable with CPU(1)
88 
--              SR_Read : integer:= 0;         --0=>user,   1=>privileged,      2=>switchable with CPU(0)
89 
--              VBR_Stackframe : integer:= 0;  --0=>no,     1=>yes/extended,    2=>switchable with CPU(0)
90 
--              extAddr_Mode : integer:= 0;    --0=>no,     1=>yes,    2=>switchable with CPU(1)
91 
--              MUL_Mode : integer := 0;           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no MUL,
92 
--              MUL_Hardware : integer := 1;   --0=>no,         1=>yes,
93 
--              DIV_Mode : integer := 0;           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no DIV,
94 
--              BarrelShifter : integer := 0;  --0=>no,     1=>yes,    2=>switchable with CPU(1)
95 
--              BitField : integer := 0            --0=>no,     1=>yes,    2=>switchable with CPU(1)
96 
                );
97 
   port(clk                     : in std_logic;
98 
        nReset                  : in std_logic;                 --low active
99 
        clkena_in               : in std_logic:='1';
100 
        data_in                 : in std_logic_vector(15 downto 0);
101 
                IPL                                     : in std_logic_vector(2 downto 0):="111";
102 
                IPL_autovector          : in std_logic:='0';
103 
                berr                            : in std_logic:='0';                                     -- only 68000 Stackpointer dummy
104 
                CPU                     : in std_logic_vector(1 downto 0):="00";  -- 00->68000  01->68010  11->68020(only some parts - yet)
105 
        addr                    : buffer std_logic_vector(31 downto 0);
106 
        data_write              : out std_logic_vector(15 downto 0);
107 
                nWr                                     : out std_logic;
108 
                nUDS, nLDS                      : out std_logic;
109 
                busstate                        : out std_logic_vector(1 downto 0);      -- 00-> fetch code 10->read data 11->write data 01->no memaccess
110 
                nResetOut                       : out std_logic;
111 
        FC                      : out std_logic_vector(2 downto 0);
112 
--
113 
                clr_berr                        : out std_logic;
114 
-- for debug
115 
                skipFetch                       : out std_logic;
116 
--      regin                   : buffer std_logic_vector(31 downto 0)
117 
--              regin_out      : out std_logic_vector(31 downto 0);
118 
                CACR_out       : out std_logic_vector( 3 downto 0);
119 
                VBR_out        : out std_logic_vector(31 downto 0)
120 
        );
121 
end TG68KdotC_Kernel;
122 
 
123 
architecture logic of TG68KdotC_Kernel is
124 
 
125 
 
126 
        signal syncReset        : std_logic_vector(3 downto 0);
127 
        signal Reset                    : std_logic;
128 
        signal clkena_lw                : std_logic;
129 
        signal TG68_PC          : std_logic_vector(31 downto 0);
130 
        signal tmp_TG68_PC      : std_logic_vector(31 downto 0);
131 
        signal TG68_PC_add      : std_logic_vector(31 downto 0);
132 
        signal PC_dataa         : std_logic_vector(31 downto 0);
133 
        signal PC_datab         : std_logic_vector(31 downto 0);
134 
        signal memaddr          : std_logic_vector(31 downto 0);
135 
    signal state                        : std_logic_vector(1 downto 0);
136 
    signal datatype                     : std_logic_vector(1 downto 0);
137 
    signal set_datatype         : std_logic_vector(1 downto 0);
138 
    signal exe_datatype         : std_logic_vector(1 downto 0);
139 
        signal setstate         : std_logic_vector(1 downto 0);
140 
 
141 
        signal opcode                   : std_logic_vector(15 downto 0);
142 
        signal exe_opcode       : std_logic_vector(15 downto 0);
143 
        signal sndOPC                   : std_logic_vector(15 downto 0);
144 
 
145 
        signal last_opc_read    : std_logic_vector(15 downto 0);
146 
        signal registerin       : std_logic_vector(31 downto 0);
147 
        signal reg_QA           : std_logic_vector(31 downto 0);
148 
        signal reg_QB           : std_logic_vector(31 downto 0);
149 
        signal Wwrena,Lwrena    : bit;
150 
        signal Bwrena                   : bit;
151 
        signal Regwrena_now             : bit;
152 
        signal rf_dest_addr             : std_logic_vector(3 downto 0);
153 
        signal rf_source_addr   : std_logic_vector(3 downto 0);
154 
        signal rf_source_addrd  : std_logic_vector(3 downto 0);
155 
 
156 
    signal regin                : std_logic_vector(31 downto 0);
157 
        type regfile_t is array(0 to 15) of std_logic_vector(31 downto 0);
158 
   signal regfile       : regfile_t := (OTHERS => (OTHERS => '0')); -- mikej stops sim X issues;
159 
        signal RDindex_A                : integer range 0 to 15;
160 
        signal RDindex_B                : integer range 0 to 15;
161 
        signal WR_AReg                  : std_logic;
162 
 
163 
 
164 
    signal memaddr_reg      : std_logic_vector(31 downto 0);
165 
    signal memaddr_delta    : std_logic_vector(31 downto 0);
166 
        signal use_base                 : bit;
167 
 
168 
   signal ea_data         : std_logic_vector(31 downto 0);
169 
   signal OP1out, OP2out  : std_logic_vector(31 downto 0);
170 
   signal OP1outbrief     : std_logic_vector(15 downto 0);
171 
   signal OP1in           : std_logic_vector(31 downto 0);
172 
   signal ALUout           : std_logic_vector(31 downto 0);
173 
   signal data_write_tmp  : std_logic_vector(31 downto 0);
174 
   signal data_write_muxin  : std_logic_vector(31 downto 0);
175 
   signal data_write_mux  : std_logic_vector(47 downto 0);
176 
   signal nextpass            : bit;
177 
   signal setnextpass     : bit;
178 
   signal setdispbyte     : bit;
179 
   signal setdisp             : bit;
180 
   signal regdirectsource :bit;         -- checken !!!
181 
   signal addsub_q        : std_logic_vector(31 downto 0);
182 
   signal briefdata       : std_logic_vector(31 downto 0);
183 
--   signal c_in                  : std_logic_vector(3 downto 0);
184 
   signal c_out           : std_logic_vector(2 downto 0);
185 
 
186 
   signal mem_address     : std_logic_vector(31 downto 0);
187 
   signal memaddr_a       : std_logic_vector(31 downto 0);
188 
 
189 
        signal TG68_PC_brw    : bit;
190 
        signal TG68_PC_word   : bit;
191 
        signal getbrief       : bit;
192 
        signal brief          : std_logic_vector(15 downto 0);
193 
        signal dest_areg      : std_logic;
194 
        signal source_areg    : std_logic;
195 
        signal data_is_source : bit;
196 
        signal store_in_tmp   : bit;
197 
        signal write_back     : bit;
198 
        signal exec_write_back: bit;
199 
        signal setstackaddr   : bit;
200 
        signal writePC        : bit;
201 
        signal writePCbig     : bit;
202 
        signal set_writePCbig : bit;
203 
        signal setopcode      : bit;
204 
        signal decodeOPC      : bit;
205 
        signal execOPC        : bit;
206 
        signal setexecOPC     : bit;
207 
        signal endOPC         : bit;
208 
        signal setendOPC      : bit;
209 
        signal Flags          : std_logic_vector(7 downto 0);    -- ...XNZVC
210 
        signal FlagsSR        : std_logic_vector(7 downto 0);    -- T.S..III
211 
        signal SRin           : std_logic_vector(7 downto 0);
212 
        signal exec_DIRECT    : bit;
213 
        signal exec_tas       : std_logic;
214 
        signal set_exec_tas   : std_logic;
215 
 
216 
        signal exe_condition  : std_logic;
217 
        signal ea_only        : bit;
218 
        signal source_lowbits : bit;
219 
        signal source_2ndHbits : bit;
220 
        signal source_2ndLbits : bit;
221 
        signal dest_2ndHbits  : bit;
222 
        signal dest_hbits     : bit;
223 
    signal rot_bits       : std_logic_vector(1 downto 0);
224 
    signal set_rot_bits   : std_logic_vector(1 downto 0);
225 
    signal rot_cnt        : std_logic_vector(5 downto 0);
226 
    signal set_rot_cnt    : std_logic_vector(5 downto 0);
227 
        signal movem_actiond  : bit;
228 
        signal movem_regaddr  : std_logic_vector(3 downto 0);
229 
        signal movem_mux      : std_logic_vector(3 downto 0);
230 
    signal movem_presub   : bit;
231 
        signal movem_run      : bit;
232 
    signal ea_calc_b      : std_logic_vector(31 downto 0);
233 
        signal set_direct_data: bit;
234 
        signal use_direct_data: bit;
235 
        signal direct_data        : bit;
236 
 
237 
    signal set_V_Flag     : bit;
238 
    signal set_vectoraddr : bit;
239 
    signal writeSR            : bit;
240 
        signal trap_berr   : bit;
241 
        signal trap_illegal   : bit;
242 
        signal trap_addr_error   : bit;
243 
        signal trap_priv      : bit;
244 
        signal trap_trace     : bit;
245 
        signal trap_1010      : bit;
246 
        signal trap_1111      : bit;
247 
        signal trap_trap      : bit;
248 
        signal trap_trapv     : bit;
249 
        signal trap_interrupt : bit;
250 
        signal trapmake       : bit;
251 
        signal trapd          : bit;
252 
    signal trap_SR        : std_logic_vector(7 downto 0);
253 
        signal make_trace     : std_logic;
254 
        signal make_berr     : std_logic;
255 
 
256 
    signal set_stop           : bit;
257 
    signal stop           : bit;
258 
    signal trap_vector    : std_logic_vector(31 downto 0);
259 
    signal trap_vector_vbr    : std_logic_vector(31 downto 0);
260 
        signal USP            : std_logic_vector(31 downto 0);
261 
--    signal illegal_write_mode   : bit;
262 
--    signal illegal_read_mode    : bit;
263 
--    signal illegal_byteaddr       : bit;
264 
 
265 
        signal IPL_nr             : std_logic_vector(2 downto 0);
266 
        signal rIPL_nr            : std_logic_vector(2 downto 0);
267 
        signal IPL_vec        : std_logic_vector(7 downto 0);
268 
    signal interrupt      : bit;
269 
    signal setinterrupt   : bit;
270 
    signal SVmode             : std_logic;
271 
    signal preSVmode      : std_logic;
272 
        signal Suppress_Base  : bit;
273 
        signal set_Suppress_Base : bit;
274 
        signal set_Z_error        : bit;
275 
        signal Z_error        : bit;
276 
        signal ea_build_now   : bit;
277 
        signal build_logical  : bit;
278 
        signal build_bcd      : bit;
279 
 
280 
        signal data_read        : std_logic_vector(31 downto 0);
281 
        signal bf_ext_in                : std_logic_vector(7 downto 0);
282 
        signal bf_ext_out               : std_logic_vector(7 downto 0);
283 
--      signal byte                 : bit;
284 
        signal long_start               : bit;
285 
        signal long_start_alu   : bit;
286 
   signal non_aligned            : std_logic;
287 
        signal long_done            : bit;
288 
        signal memmask          : std_logic_vector(5 downto 0);
289 
        signal set_memmask      : std_logic_vector(5 downto 0);
290 
        signal memread          : std_logic_vector(3 downto 0);
291 
        signal wbmemmask        : std_logic_vector(5 downto 0);
292 
        signal memmaskmux       : std_logic_vector(5 downto 0);
293 
        signal oddout           : std_logic;
294 
        signal set_oddout       : std_logic;
295 
        signal PCbase           : std_logic;
296 
        signal set_PCbase       : std_logic;
297 
 
298 
        signal last_data_read   : std_logic_vector(31 downto 0);
299 
        signal last_data_in     : std_logic_vector(31 downto 0);
300 
 
301 
    signal bf_offset        : std_logic_vector(5 downto 0);
302 
    signal bf_width         : std_logic_vector(5 downto 0);
303 
    signal bf_bhits         : std_logic_vector(5 downto 0);
304 
    signal bf_shift         : std_logic_vector(5 downto 0);
305 
    signal alu_width        : std_logic_vector(5 downto 0);
306 
    signal alu_bf_shift     : std_logic_vector(5 downto 0);
307 
        signal bf_loffset       : std_logic_vector(5 downto 0);
308 
        signal bf_full_offset    : std_logic_vector(31 downto 0);
309 
        signal alu_bf_ffo_offset    : std_logic_vector(31 downto 0);
310 
        signal alu_bf_loffset   : std_logic_vector(5 downto 0);
311 
 
312 
        signal movec_data       : std_logic_vector(31 downto 0);
313 
        signal VBR              : std_logic_vector(31 downto 0);
314 
        signal CACR             : std_logic_vector(3 downto 0);
315 
        signal DFC              : std_logic_vector(2 downto 0);
316 
        signal SFC              : std_logic_vector(2 downto 0);
317 
 
318 
 
319 
        signal set              : bit_vector(lastOpcBit downto 0);
320 
        signal set_exec         : bit_vector(lastOpcBit downto 0);
321 
        signal exec             : bit_vector(lastOpcBit downto 0);
322 
 
323 
        signal micro_state              : micro_states;
324 
        signal next_micro_state : micro_states;
325 
 
326 
 
327 
 
328 
BEGIN
329 
 
330 
ALU: TG68K_ALU
331 
        generic map(
332 
                MUL_Mode => MUL_Mode,                --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no MUL,
333 
                MUL_Hardware => MUL_Hardware,   --0=>no,        1=>yes,
334 
                DIV_Mode => DIV_Mode,                --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no DIV,
335 
                BarrelShifter => BarrelShifter  --0=>no,     1=>yes,    2=>switchable with CPU(1)
336 
                )
337 
    port map(
338 
        clk => clk,                             --: in std_logic;
339 
        Reset => Reset,                         --: in std_logic;
340 
        clkena_lw => clkena_lw,         --: in std_logic:='1';
341 
        execOPC => execOPC,             --: in bit;
342 
        decodeOPC => decodeOPC,         --: in bit;
343 
        exe_condition => exe_condition, --: in std_logic;
344 
        exec_tas => exec_tas,                   --: in std_logic;
345 
        long_start => long_start_alu,   --: in bit;
346 
             non_aligned => non_aligned,
347 
        movem_presub => movem_presub,   --: in bit;
348 
        set_stop => set_stop,                   --: in bit;
349 
        Z_error => Z_error,             --: in bit;
350 
 
351 
        rot_bits => rot_bits,           --: in std_logic_vector(1 downto 0);
352 
                exec => exec,                   --: in bit_vector(lastOpcBit downto 0);
353 
        OP1out => OP1out,                       --: in std_logic_vector(31 downto 0);
354 
        OP2out => OP2out,                       --: in std_logic_vector(31 downto 0);
355 
        reg_QA => reg_QA,                       --: in std_logic_vector(31 downto 0);
356 
        reg_QB => reg_QB,                       --: in std_logic_vector(31 downto 0);
357 
        opcode => opcode,                       --: in std_logic_vector(15 downto 0);
358 
--        datatype => datatype,                 --: in std_logic_vector(1 downto 0);
359 
        exe_opcode => exe_opcode,       --: in std_logic_vector(15 downto 0);
360 
        exe_datatype => exe_datatype,   --: in std_logic_vector(1 downto 0);
361 
        sndOPC => sndOPC,                       --: in std_logic_vector(15 downto 0);
362 
        last_data_read => last_data_read(15 downto 0),   --: in std_logic_vector(31 downto 0);
363 
        data_read => data_read(15 downto 0),                     --: in std_logic_vector(31 downto 0);
364 
        FlagsSR => FlagsSR,             --: in std_logic_vector(7 downto 0);
365 
                micro_state => micro_state,             --: in micro_states;
366 
                bf_ext_in => bf_ext_in,
367 
                bf_ext_out => bf_ext_out,
368 
                bf_shift => alu_bf_shift,
369 
                bf_width => alu_width,
370 
                bf_ffo_offset => alu_bf_ffo_offset,
371 
                bf_loffset => alu_bf_loffset(4 downto 0),
372 
 
373 
        set_V_Flag => set_V_Flag,           --: buffer bit;
374 
        Flags => Flags,                         --: buffer std_logic_vector(8 downto 0);
375 
        c_out => c_out,                         --: buffer std_logic_vector(2 downto 0);
376 
        addsub_q => addsub_q,           --: buffer std_logic_vector(31 downto 0);
377 
        ALUout => ALUout                        --: buffer std_logic_vector(31 downto 0)
378 
    );
379 
 
380 
        long_start_alu <= to_bit(NOT memmaskmux(3));
381 
 
382 
   process (memmaskmux)
383 
   begin
384 
           non_aligned <= '0';
385 
           if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then
386 
              non_aligned <= '1';
387 
           end if;
388 
    end process;
389 
-----------------------------------------------------------------------------
390 
-- Bus control
391 
-----------------------------------------------------------------------------
392 
        nWr <= '0' WHEN state="11" ELSE '1';
393 
        busstate <= state;
394 
        nResetOut <= '0' WHEN exec(opcRESET)='1' ELSE '1';
395 
 
396 
   -- does shift for byte access. note active low me
397 
   -- should produce address error on 68000
398 
   memmaskmux <= memmask when addr(0) = '1' else memmask(4 downto 0) & '1';
399 
        nUDS <= memmaskmux(5);
400 
        nLDS <= memmaskmux(4);
401 
        clkena_lw <= '1' WHEN clkena_in='1' AND memmaskmux(3)='1' ELSE '0';
402 
        clr_berr <= '1' WHEN setopcode='1' AND trap_berr='1' ELSE '0';
403 
 
404 
        PROCESS (clk, nReset)
405 
        BEGIN
406 
                IF nReset='0' THEN
407 
                        syncReset <= "0000";
408 
                        Reset <= '1';
409 
                ELSIF rising_edge(clk) THEN
410 
                        IF clkena_in='1' THEN
411 
                                syncReset <= syncReset(2 downto 0)&'1';
412 
                                Reset <= NOT syncReset(3);
413 
                        END IF;
414 
                END IF;
415 
        END PROCESS;
416 
 
417 
PROCESS (clk, long_done, last_data_in, data_in, addr, long_start, memmaskmux, memread, memmask, data_read)
418 
        BEGIN
419 
                IF memmaskmux(4)='0' THEN
420 
                        data_read <= last_data_in(15 downto 0)&data_in;
421 
                ELSE
422 
                        data_read <= last_data_in(23 downto 0)&data_in(15 downto 8);
423 
                END IF;
424 
                IF memread(0)='1' OR (memread(1 downto 0)="10" AND memmaskmux(4)='1')THEN
425 
                        data_read(31 downto 16) <= (OTHERS=>data_read(15));
426 
                END IF;
427 
 
428 
                IF rising_edge(clk) THEN
429 
                        IF clkena_lw='1' AND state="10" THEN
430 
                                IF memmaskmux(4)='0' THEN
431 
                                        bf_ext_in <= last_data_in(23 downto 16);
432 
                                ELSE
433 
                                        bf_ext_in <= last_data_in(31 downto 24);
434 
                                END IF;
435 
                        END IF;
436 
                        IF Reset='1' THEN
437 
                                last_data_read <= (OTHERS => '0');
438 
                        ELSIF clkena_in='1' THEN
439 
                                IF state="00" OR exec(update_ld)='1' THEN
440 
                                        last_data_read <= data_read;
441 
                                        IF state(1)='0' AND memmask(1)='0' THEN
442 
                                                last_data_read(31 downto 16) <= last_opc_read;
443 
                                        ELSIF state(1)='0' OR memread(1)='1' THEN
444 
                                                last_data_read(31 downto 16) <= (OTHERS=>data_in(15));
445 
                                        END IF;
446 
                                END IF;
447 
                                last_data_in <= last_data_in(15 downto 0)&data_in(15 downto 0);
448 
 
449 
                        END IF;
450 
                END IF;
451 
                                long_start <= to_bit(NOT memmask(1));
452 
                                long_done <= to_bit(NOT memread(1));
453 
        END PROCESS;
454 
 
455 
PROCESS (long_start, reg_QB, data_write_tmp, exec, data_read, data_write_mux, memmaskmux, bf_ext_out,
456 
                 data_write_muxin, memmask, oddout, addr)
457 
        BEGIN
458 
                IF exec(write_reg)='1' THEN
459 
                        data_write_muxin <= reg_QB;
460 
                ELSE
461 
                        data_write_muxin <= data_write_tmp;
462 
                END IF;
463 
 
464 
                IF BitField=0 THEN
465 
                        IF oddout=addr(0) THEN
466 
                                data_write_mux <= "--------"&"--------"&data_write_muxin;
467 
                        ELSE
468 
                                data_write_mux <= "--------"&data_write_muxin&"--------";
469 
                        END IF;
470 
                ELSE
471 
                        IF oddout=addr(0) THEN
472 
                                data_write_mux <= "--------"&bf_ext_out&data_write_muxin;
473 
                        ELSE
474 
                                data_write_mux <= bf_ext_out&data_write_muxin&"--------";
475 
                        END IF;
476 
                END IF;
477 
 
478 
                IF memmaskmux(1)='0' THEN
479 
                        data_write <= data_write_mux(47 downto 32);
480 
                ELSIF memmaskmux(3)='0' THEN
481 
                        data_write <= data_write_mux(31 downto 16);
482 
                ELSE
483 
                        data_write <= data_write_mux(15 downto 0);
484 
                END IF;
485 
                IF exec(mem_byte)='1' THEN      --movep
486 
                        data_write(7 downto 0) <= data_write_tmp(15 downto 8);
487 
                END IF;
488 
        END PROCESS;
489 
 
490 
-----------------------------------------------------------------------------
491 
-- Registerfile
492 
-----------------------------------------------------------------------------
493 
PROCESS (clk, regfile, RDindex_A, RDindex_B, exec)
494 
        BEGIN
495 
                reg_QA <= regfile(RDindex_A);
496 
                reg_QB <= regfile(RDindex_B);
497 
                IF rising_edge(clk) THEN
498 
                    IF clkena_lw='1' THEN
499 
                                rf_source_addrd <= rf_source_addr;
500 
                                WR_AReg <= rf_dest_addr(3);
501 
                                RDindex_A <= conv_integer(rf_dest_addr(3 downto 0));
502 
                                RDindex_B <= conv_integer(rf_source_addr(3 downto 0));
503 
                                IF Wwrena='1' THEN
504 
                                        regfile(RDindex_A) <= regin;
505 
                                END IF;
506 
 
507 
                                IF exec(to_USP)='1' THEN
508 
                                        USP <= reg_QA;
509 
                                END IF;
510 
                        END IF;
511 
                END IF;
512 
        END PROCESS;
513 
 
514 
-----------------------------------------------------------------------------
515 
-- Write Reg
516 
-----------------------------------------------------------------------------
517 
PROCESS (OP1in, reg_QA, Regwrena_now, Bwrena, Lwrena, exe_datatype, WR_AReg, movem_actiond, exec, ALUout, memaddr, memaddr_a, ea_only, USP, movec_data)
518 
        BEGIN
519 
                regin <= ALUout;
520 
                IF exec(save_memaddr)='1' THEN
521 
                        regin <= memaddr;
522 
                ELSIF exec(get_ea_now)='1' AND ea_only='1' THEN
523 
                        regin <= memaddr_a;
524 
                ELSIF exec(from_USP)='1' THEN
525 
                        regin <= USP;
526 
                ELSIF exec(movec_rd)='1' THEN
527 
                        regin <= movec_data;
528 
                END IF;
529 
 
530 
                IF Bwrena='1' THEN
531 
                        regin(15 downto 8) <= reg_QA(15 downto 8);
532 
                END IF;
533 
                IF Lwrena='0' THEN
534 
                        regin(31 downto 16) <= reg_QA(31 downto 16);
535 
                END IF;
536 
 
537 
                Bwrena <= '0';
538 
                Wwrena <= '0';
539 
                Lwrena <= '0';
540 
                IF exec(presub)='1' OR exec(postadd)='1' OR exec(changeMode)='1' THEN           -- -(An)+
541 
                        Wwrena <= '1';
542 
                        Lwrena <= '1';
543 
                ELSIF Regwrena_now='1' THEN             --dbcc
544 
                        Wwrena <= '1';
545 
                ELSIF exec(Regwrena)='1' THEN           --read (mem)
546 
                        Wwrena <= '1';
547 
                        CASE exe_datatype IS
548 
                                WHEN "00" =>            --BYTE
549 
                                        Bwrena <= '1';
550 
                                WHEN "01" =>            --WORD
551 
                                        IF WR_AReg='1' OR movem_actiond='1' THEN
552 
                                                Lwrena <='1';
553 
                                        END IF;
554 
                                WHEN OTHERS =>          --LONG
555 
                                        Lwrena <= '1';
556 
                        END CASE;
557 
                END IF;
558 
        END PROCESS;
559 
 
560 
-----------------------------------------------------------------------------
561 
-- set dest regaddr
562 
-----------------------------------------------------------------------------
563 
PROCESS (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, data_is_source, sndOPC, exec, set, dest_2ndHbits)
564 
        BEGIN
565 
                IF exec(movem_action) ='1' THEN
566 
                        rf_dest_addr <= rf_source_addrd;
567 
                ELSIF set(briefext)='1' THEN
568 
                        rf_dest_addr <= brief(15 downto 12);
569 
                ELSIF set(get_bfoffset)='1' THEN
570 
                        rf_dest_addr <= sndOPC(9 downto 6);
571 
                ELSIF dest_2ndHbits='1' THEN
572 
                        rf_dest_addr <= sndOPC(15 downto 12);
573 
                ELSIF set(write_reminder)='1' THEN
574 
                        rf_dest_addr <= sndOPC(3 downto 0);
575 
                ELSIF setstackaddr='1' THEN
576 
                        rf_dest_addr <= "1111";
577 
                ELSIF dest_hbits='1' THEN
578 
                        rf_dest_addr <= dest_areg&opcode(11 downto 9);
579 
                ELSE
580 
                        IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
581 
                                rf_dest_addr <= dest_areg&opcode(2 downto 0);
582 
                        ELSE
583 
                                rf_dest_addr <= '1'&opcode(2 downto 0);
584 
                        END IF;
585 
                END IF;
586 
        END PROCESS;
587 
 
588 
-----------------------------------------------------------------------------
589 
-- set source regaddr
590 
-----------------------------------------------------------------------------
591 
PROCESS (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits)
592 
        BEGIN
593 
                IF exec(movem_action)='1' OR set(movem_action) ='1' THEN
594 
                        IF movem_presub='1' THEN
595 
                                rf_source_addr <= movem_regaddr XOR "1111";
596 
                        ELSE
597 
                                rf_source_addr <= movem_regaddr;
598 
                        END IF;
599 
                ELSIF source_2ndLbits='1' THEN
600 
                        rf_source_addr <= sndOPC(3 downto 0);
601 
                ELSIF source_2ndHbits='1' THEN
602 
                        rf_source_addr <= sndOPC(15 downto 12);
603 
                ELSIF source_lowbits='1' THEN
604 
                        rf_source_addr <= source_areg&opcode(2 downto 0);
605 
                ELSIF exec(linksp)='1' THEN
606 
                        rf_source_addr <= "1111";
607 
                ELSE
608 
                        rf_source_addr <= source_areg&opcode(11 downto 9);
609 
                END IF;
610 
        END PROCESS;
611 
 
612 
-----------------------------------------------------------------------------
613 
-- set OP1out
614 
-----------------------------------------------------------------------------
615 
PROCESS (reg_QA, store_in_tmp, ea_data, long_start, addr, exec, memmaskmux)
616 
        BEGIN
617 
                OP1out <= reg_QA;
618 
                IF exec(OP1out_zero)='1' THEN
619 
                        OP1out <= (OTHERS => '0');
620 
                ELSIF exec(ea_data_OP1)='1' AND store_in_tmp='1' THEN
621 
                        OP1out <= ea_data;
622 
                ELSIF exec(movem_action)='1' OR memmaskmux(3)='0' OR exec(OP1addr)='1' THEN
623 
                        OP1out <= addr;
624 
                END IF;
625 
        END PROCESS;
626 
 
627 
-----------------------------------------------------------------------------
628 
-- set OP2out
629 
-----------------------------------------------------------------------------
630 
PROCESS (OP2out, reg_QB, exe_opcode, exe_datatype, execOPC, exec, use_direct_data,
631 
             store_in_tmp, data_write_tmp, ea_data)
632 
        BEGIN
633 
                OP2out(15 downto 0) <= reg_QB(15 downto 0);
634 
                OP2out(31 downto 16) <= (OTHERS => OP2out(15));
635 
                IF exec(OP2out_one)='1' THEN
636 
                        OP2out(15 downto 0) <= "1111111111111111";
637 
                ELSIF exec(opcEXT)='1' THEN
638 
                        IF exe_opcode(6)='0' OR exe_opcode(8)='1' THEN   --ext.w
639 
                                OP2out(15 downto 8) <= (OTHERS => OP2out(7));
640 
                        END IF;
641 
                ELSIF use_direct_data='1' OR (exec(exg)='1' AND execOPC='1') OR exec(get_bfoffset)='1' THEN
642 
                        OP2out <= data_write_tmp;
643 
                ELSIF (exec(ea_data_OP1)='0' AND store_in_tmp='1') OR exec(ea_data_OP2)='1' THEN
644 
                        OP2out <= ea_data;
645 
                ELSIF exec(opcMOVEQ)='1' THEN
646 
                        OP2out(7 downto 0) <= exe_opcode(7 downto 0);
647 
                        OP2out(15 downto 8) <= (OTHERS => exe_opcode(7));
648 
                ELSIF exec(opcADDQ)='1' THEN
649 
                        OP2out(2 downto 0) <= exe_opcode(11 downto 9);
650 
                        IF exe_opcode(11 downto 9)="000" THEN
651 
                                OP2out(3) <='1';
652 
                        ELSE
653 
                                OP2out(3) <='0';
654 
                        END IF;
655 
                        OP2out(15 downto 4) <= (OTHERS => '0');
656 
                ELSIF exe_datatype="10" THEN
657 
                        OP2out(31 downto 16) <= reg_QB(31 downto 16);
658 
                END IF;
659 
        END PROCESS;
660 
 
661 
 
662 
-----------------------------------------------------------------------------
663 
-- handle EA_data, data_write
664 
-----------------------------------------------------------------------------
665 
PROCESS (clk)
666 
        BEGIN
667 
        IF rising_edge(clk) THEN
668 
                        IF Reset = '1' THEN
669 
                                store_in_tmp <='0';
670 
                                exec_write_back <= '0';
671 
                                direct_data <= '0';
672 
                                use_direct_data <= '0';
673 
                                Z_error <= '0';
674 
                        ELSIF clkena_lw='1' THEN
675 
                                direct_data <= '0';
676 
                                IF state="11" THEN
677 
                                        exec_write_back <= '0';
678 
                                ELSIF setstate="10" AND write_back='1' THEN
679 
                                        exec_write_back <= '1';
680 
                                END IF;
681 
 
682 
 
683 
                                IF set_direct_data='1' THEN
684 
                                        direct_data <= '1';
685 
                                        use_direct_data <= '1';
686 
                                ELSIF endOPC='1' THEN
687 
                                        use_direct_data <= '0';
688 
                                END IF;
689 
                                exec_DIRECT <= set_exec(opcMOVE);
690 
 
691 
                                IF endOPC='1' THEN
692 
                                        store_in_tmp <='0';
693 
                                        Z_error <= '0';
694 
                                ELSE
695 
                                        IF set_Z_error='1'  THEN
696 
                                                Z_error <= '1';
697 
                                        END IF;
698 
                                        IF set_exec(opcMOVE)='1' AND state="11" THEN
699 
                                                use_direct_data <= '1';
700 
                                        END IF;
701 
 
702 
                                        IF state="10" OR exec(store_ea_packdata)='1' THEN
703 
                                                store_in_tmp <= '1';
704 
                                        END IF;
705 
                                        IF direct_data='1' AND state="00" THEN
706 
                                                store_in_tmp <= '1';
707 
                                        END IF;
708 
                                END IF;
709 
 
710 
                                IF state="10" AND exec(hold_ea_data)='0' THEN
711 
                                        ea_data <= data_read;
712 
                                ELSIF exec(get_2ndOPC)='1' THEN
713 
                                        ea_data <= addr;
714 
                                ELSIF exec(store_ea_data)='1' OR (direct_data='1' AND state="00") THEN
715 
                                        ea_data <= last_data_read;
716 
                                END IF;
717 
 
718 
                                IF writePC='1' THEN
719 
                                        data_write_tmp <= TG68_PC;
720 
                                ELSIF exec(writePC_add)='1' THEN
721 
                                        data_write_tmp <= TG68_PC_add;
722 
                                ELSIF micro_state=trap0 THEN
723 
                                        data_write_tmp(15 downto 0) <= trap_vector(15 downto 0);
724 
                                ELSIF exec(hold_dwr)='1' THEN
725 
                                        data_write_tmp <= data_write_tmp;
726 
                                ELSIF exec(exg)='1' THEN
727 
                                        data_write_tmp <= OP1out;
728 
                                ELSIF exec(get_ea_now)='1' AND ea_only='1' THEN         -- ist for pea
729 
                                        data_write_tmp <= addr;
730 
                                ELSIF execOPC='1' THEN
731 
                                        data_write_tmp <= ALUout;
732 
                                ELSIF (exec_DIRECT='1' AND state="10") THEN
733 
                                        data_write_tmp <= data_read;
734 
                                        IF  exec(movepl)='1' THEN
735 
                                                data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
736 
                                        END IF;
737 
                                ELSIF exec(movepl)='1' THEN
738 
                                        data_write_tmp(15 downto 0) <= reg_QB(31 downto 16);
739 
                                ELSIF direct_data='1' THEN
740 
                                        data_write_tmp <= last_data_read;
741 
                                ELSIF writeSR='1'THEN
742 
                                        data_write_tmp(15 downto 0) <= trap_SR(7 downto 0)& Flags(7 downto 0);
743 
                                ELSE
744 
                                        data_write_tmp <= OP2out;
745 
                                END IF;
746 
                        END IF;
747 
                END IF;
748 
        END PROCESS;
749 
 
750 
-----------------------------------------------------------------------------
751 
-- brief
752 
-----------------------------------------------------------------------------
753 
PROCESS (brief, OP1out, OP1outbrief, cpu)
754 
        BEGIN
755 
                IF brief(11)='1' THEN
756 
                        OP1outbrief <= OP1out(31 downto 16);
757 
                ELSE
758 
                        OP1outbrief <= (OTHERS=>OP1out(15));
759 
                END IF;
760 
                briefdata <= OP1outbrief&OP1out(15 downto 0);
761 
                IF extAddr_Mode=1 OR (cpu(1)='1' AND extAddr_Mode=2) THEN
762 
                        CASE brief(10 downto 9) IS
763 
                                WHEN "00" => briefdata <= OP1outbrief&OP1out(15 downto 0);
764 
                                WHEN "01" => briefdata <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
765 
                                WHEN "10" => briefdata <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
766 
                                WHEN "11" => briefdata <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
767 
                                WHEN OTHERS => NULL;
768 
                        END CASE;
769 
                END IF;
770 
        END PROCESS;
771 
 
772 
-----------------------------------------------------------------------------
773 
-- MEM_IO
774 
-----------------------------------------------------------------------------
775 
PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatype, interrupt, rIPL_nr, IPL_vec,
776 
         memaddr_reg, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu)
777 
        BEGIN
778 
 
779 
                IF rising_edge(clk) THEN
780 
                        IF clkena_lw='1' THEN
781 
                                trap_vector(31 downto 10) <= (others => '0');
782 
                                IF trap_berr='1' THEN
783 
                                        trap_vector(9 downto 0) <= "00" & X"08";
784 
                                END IF;
785 
                                IF trap_addr_error='1' THEN
786 
                                        trap_vector(9 downto 0) <= "00" & X"0C";
787 
                                END IF;
788 
                                IF trap_illegal='1' THEN
789 
                                        trap_vector(9 downto 0) <= "00" & X"10";
790 
                                END IF;
791 
                                IF z_error='1' THEN
792 
                                        trap_vector(9 downto 0) <= "00" & X"14";
793 
                                END IF;
794 
                                IF exec(trap_chk)='1' THEN
795 
                                        trap_vector(9 downto 0) <= "00" & X"18";
796 
                                END IF;
797 
                                IF trap_trapv='1' THEN
798 
                                        trap_vector(9 downto 0) <= "00" & X"1C";
799 
                                END IF;
800 
                                IF trap_priv='1' THEN
801 
                                        trap_vector(9 downto 0) <= "00" & X"20";
802 
                                END IF;
803 
                                IF trap_trace='1' THEN
804 
                                        trap_vector(9 downto 0) <= "00" & X"24";
805 
                                END IF;
806 
                                IF trap_1010='1' THEN
807 
                                        trap_vector(9 downto 0) <= "00" & X"28";
808 
                                END IF;
809 
                                IF trap_1111='1' THEN
810 
                                        trap_vector(9 downto 0) <= "00" & X"2C";
811 
                                END IF;
812 
                                IF trap_trap='1' THEN
813 
                                        trap_vector(9 downto 0) <= "0010" & opcode(3 downto 0) & "00";
814 
                                END IF;
815 
                                IF trap_interrupt='1' or set_vectoraddr = '1' THEN
816 
                                        trap_vector(9 downto 0) <= IPL_vec & "00";      --TH
817 
                                END IF;
818 
                        END IF;
819 
                END IF;
820 
                IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
821 
                        trap_vector_vbr <= trap_vector;
822 
                ELSE
823 
                        trap_vector_vbr <= trap_vector+VBR;
824 
                END IF;
825 
 
826 
                memaddr_a(4 downto 0) <= "00000";
827 
                memaddr_a(7 downto 5) <= (OTHERS=>memaddr_a(4));
828 
                memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
829 
                memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
830 
                IF setdisp='1' THEN
831 
                        IF exec(briefext)='1' THEN
832 
                                memaddr_a <= briefdata+memaddr_delta;
833 
                        ELSIF setdispbyte='1' THEN
834 
                                memaddr_a(7 downto 0) <= last_data_read(7 downto 0);
835 
                        ELSE
836 
                                memaddr_a <= last_data_read;
837 
                        END IF;
838 
                ELSIF set(presub)='1' THEN
839 
                        IF set(longaktion)='1' THEN
840 
                                memaddr_a(4 downto 0) <= "11100";
841 
                        ELSIF datatype="00" AND set(use_SP)='0' THEN
842 
                                memaddr_a(4 downto 0) <= "11111";
843 
                        ELSE
844 
                                memaddr_a(4 downto 0) <= "11110";
845 
                        END IF;
846 
                ELSIF interrupt='1' THEN
847 
                        memaddr_a(4 downto 0) <= '1'&rIPL_nr&'0';
848 
                END IF;
849 
 
850 
                IF rising_edge(clk) THEN
851 
                        IF clkena_in='1' THEN
852 
                                IF exec(get_2ndOPC)='1' OR (state="10" AND memread(0)='1') THEN
853 
                                        tmp_TG68_PC <= addr;
854 
                                END IF;
855 
                                use_base <= '0';
856 
                                IF memmaskmux(3)='0' OR exec(mem_addsub)='1' THEN
857 
                                        memaddr_delta <= addsub_q;
858 
                                ELSIF state="01" AND exec_write_back='1' THEN
859 
                                        memaddr_delta <= tmp_TG68_PC;
860 
                                ELSIF exec(direct_delta)='1' THEN
861 
                                        memaddr_delta <= data_read;
862 
                                ELSIF exec(ea_to_pc)='1' AND setstate="00" THEN
863 
                                        memaddr_delta <= addr;
864 
                                ELSIF set(addrlong)='1' THEN
865 
                                        memaddr_delta <= last_data_read;
866 
                                ELSIF setstate="00" THEN
867 
                                        memaddr_delta <= TG68_PC_add;
868 
                                ELSIF exec(dispouter)='1' THEN
869 
                                        memaddr_delta <= ea_data+memaddr_a;
870 
                                ELSIF set_vectoraddr='1' THEN
871 
                                        memaddr_delta <= trap_vector_vbr;
872 
                                ELSE
873 
                                        memaddr_delta <= memaddr_a;
874 
                                        IF interrupt='0' AND Suppress_Base='0' THEN
875 
--                                      IF interrupt='0' AND Suppress_Base='0' AND setstate(1)='1' THEN
876 
                                                use_base <= '1';
877 
                                        END IF;
878 
                                END IF;
879 
 
880 
                -- only used for movem address update
881 
--                                      IF (long_done='0' AND state(1)='1') OR movem_presub='0' THEN
882 
                                        if ((memread(0) = '1') and state(1) = '1') or movem_presub = '0' then -- fix for unaligned movem mikej
883 
                                                memaddr <= addr;
884 
                                        END IF;
885 
                        END IF;
886 
                END IF;
887 
 
888 
                -- if access done, and not aligned, don't increment
889 
                addr <= memaddr_reg+memaddr_delta;
890 
                IF use_base='0' THEN
891 
                        memaddr_reg <= (others=>'0');
892 
                ELSE
893 
                        memaddr_reg <= reg_QA;
894 
                END IF;
895 
    END PROCESS;
896 
 
897 
-----------------------------------------------------------------------------
898 
-- PC Calc + fetch opcode
899 
-----------------------------------------------------------------------------
900 
PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
901 
             PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
902 
        BEGIN
903 
 
904 
                PC_dataa <= TG68_PC;
905 
                IF TG68_PC_brw = '1' THEN
906 
                        PC_dataa <= tmp_TG68_PC;
907 
                END IF;
908 
 
909 
                PC_datab(2 downto 0) <= (others => '0');
910 
                PC_datab(3) <= PC_datab(2);
911 
                PC_datab(7 downto 4) <= (others => PC_datab(3));
912 
                PC_datab(15 downto 8) <= (others => PC_datab(7));
913 
                PC_datab(31 downto 16) <= (others => PC_datab(15));
914 
                IF interrupt='1' THEN
915 
                        PC_datab(2 downto 1) <= "11";
916 
                END IF;
917 
                IF exec(writePC_add) ='1' THEN
918 
                        IF writePCbig='1' THEN
919 
                                PC_datab(3) <= '1';
920 
                                PC_datab(1) <= '1';
921 
                        ELSE
922 
                                PC_datab(2) <= '1';
923 
                        END IF;
924 
                        IF trap_trap='1' OR trap_trapv='1' OR exec(trap_chk)='1' OR Z_error='1' THEN
925 
                                PC_datab(1) <= '1';
926 
                        END IF;
927 
                ELSIF state="00" THEN
928 
                        PC_datab(1) <= '1';
929 
                END IF;
930 
                IF TG68_PC_brw = '1' THEN
931 
                        IF TG68_PC_word='1' THEN
932 
                                PC_datab <= last_data_read;
933 
                        ELSE
934 
                                PC_datab(7 downto 0) <= opcode(7 downto 0);
935 
                        END IF;
936 
                END IF;
937 
 
938 
                TG68_PC_add <= PC_dataa+PC_datab;
939 
 
940 
                setopcode <= '0';
941 
                setendOPC <= '0';
942 
                setinterrupt <= '0';
943 
                IF setstate="00" AND next_micro_state=idle AND setnextpass='0' AND (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" AND set_exec(opcCHK)='0'THEN
944 
                        setendOPC <= '1';
945 
                        IF FlagsSR(2 downto 0)<IPL_nr OR IPL_nr="111"  OR make_trace='1' OR make_berr='1' THEN
946 
                                setinterrupt <= '1';
947 
                        ELSIF stop='0' THEN
948 
                                setopcode <= '1';
949 
                        END IF;
950 
                END IF;
951 
                setexecOPC <= '0';
952 
                IF setstate="00" AND next_micro_state=idle AND set_direct_data='0' AND (exec_write_back='0' OR state="10") THEN
953 
                        setexecOPC <= '1';
954 
                END IF;
955 
 
956 
                IPL_nr <= NOT IPL;
957 
                IF rising_edge(clk) THEN
958 
                IF Reset = '1' THEN
959 
                                state <= "01";
960 
                                opcode <= X"2E79";                                      --move $0,a7
961 
                                trap_interrupt <= '0';
962 
                                interrupt <= '0';
963 
                                last_opc_read  <= X"4EF9";                      --jmp nn.l
964 
                                TG68_PC <= X"00000004";
965 
                                decodeOPC <= '0';
966 
                                endOPC <= '0';
967 
                                TG68_PC_word <= '0';
968 
                                execOPC <= '0';
969 
                                stop <= '0';
970 
                                rot_cnt <="000001";
971 
--                              byte <= '0';
972 
--                              IPL_nr <= "000";
973 
                                trap_trace <= '0';
974 
                                trap_berr <= '0';
975 
                                writePCbig <= '0';
976 
--                              recall_last <= '0';
977 
                                Suppress_Base <= '0';
978 
                                make_berr <= '0';
979 
                                memmask <= "111111";
980 
                        ELSE
981 
--                              IPL_nr <= NOT IPL;
982 
                                IF clkena_in='1' THEN
983 
                                        memmask <= memmask(3 downto 0)&"11";
984 
                                        memread <= memread(1 downto 0)&memmaskmux(5 downto 4);
985 
--                                      IF wbmemmask(5 downto 4)="11" THEN
986 
--                                              wbmemmask <= memmask;
987 
--                                      END IF;
988 
                                        IF exec(directPC)='1' THEN
989 
                                                TG68_PC <= data_read;
990 
                                        ELSIF exec(ea_to_pc)='1' THEN
991 
                                                TG68_PC <= addr;
992 
                                        ELSIF (state ="00" OR TG68_PC_brw = '1') AND stop='0'  THEN
993 
                                                TG68_PC <= TG68_PC_add;
994 
                                        END IF;
995 
                                END IF;
996 
                                IF clkena_lw='1' THEN
997 
                                        interrupt <= setinterrupt;
998 
                                        decodeOPC <= setopcode;
999 
                                        endOPC <= setendOPC;
1000 
                                        execOPC <= setexecOPC;
1001 
 
1002 
                                        exe_datatype <= set_datatype;
1003 
                                        exe_opcode <= opcode;
1004 
 
1005 
                                        if(trap_berr='0') then
1006 
                                                make_berr <= (berr OR make_berr);
1007 
                                        else
1008 
                                                make_berr <= '0';
1009 
                                        end if;
1010 
 
1011 
                                        stop <= set_stop OR (stop AND NOT setinterrupt);
1012 
                                        IF setinterrupt='1' THEN
1013 
                                                trap_interrupt <= '0';
1014 
                                                trap_trace <= '0';
1015 
--                                              TG68_PC_word <= '0';
1016 
                                                make_berr <= '0';
1017 
                                                trap_berr <= '0';
1018 
                                                IF make_trace='1' THEN
1019 
                                                        trap_trace <= '1';
1020 
                                                ELSIF make_berr='1' THEN
1021 
                                                        trap_berr <= '1';
1022 
                                                ELSE
1023 
                                                        rIPL_nr <= IPL_nr;
1024 
                                                        IPL_vec <= "00011"&IPL_nr;            --        TH
1025 
                                                        trap_interrupt <= '1';
1026 
                                                END IF;
1027 
                                        END IF;
1028 
                                        IF micro_state=trap0 AND IPL_autovector='0' THEN
1029 
                                                IPL_vec <= last_data_read(7 downto 0);    --     TH
1030 
                                        END IF;
1031 
                                        IF state="00" THEN
1032 
                                                last_opc_read <= data_read(15 downto 0);
1033 
                                        END IF;
1034 
                                        IF setopcode='1' THEN
1035 
                                                trap_interrupt <= '0';
1036 
                                                trap_trace <= '0';
1037 
                                                TG68_PC_word <= '0';
1038 
                                                trap_berr <= '0';
1039 
                                        ELSIF opcode(7 downto 0)="00000000" OR opcode(7 downto 0)="11111111" OR data_is_source='1' THEN
1040 
                                                TG68_PC_word <= '1';
1041 
                                        END IF;
1042 
 
1043 
                                        IF exec(get_bfoffset)='1' THEN
1044 
                                                alu_width <= bf_width;
1045 
                                                alu_bf_shift <= bf_shift;
1046 
                                                alu_bf_loffset <= bf_loffset;
1047 
                                                alu_bf_ffo_offset <= bf_full_offset+bf_width+1;
1048 
--                                      ELSIF set_exec(exec_BS)='1' THEN
1049 
--
1050 
----                                                    IF set_exec(exec_BS)='1' THEN
1051 
----                                                            alu_width<="001111";
1052 
----                                                            alu_bf_loffset <= "000000";
1053 
----                                                    END IF;
1054 
--
1055 
----                                            alu_bf_shift <= set_rot_cnt;
1056 
--                                                      IF opcode(5)='1' THEN
1057 
----                                                            next_micro_state <= rota1;
1058 
----                                                            set(ld_rot_cnt) <= '1';
1059 
----                                                            setstate <= "01";
1060 
--                                                              alu_bf_shift <= OP2out(5 downto 0);
1061 
--                                                      ELSE
1062 
--                                                              alu_bf_shift(2 downto 0) <= opcode(11 downto 9);
1063 
--                                                              IF opcode(11 downto 9)="000" THEN
1064 
--                                                                      alu_bf_shift(5 downto 3) <="001";
1065 
--                                                              ELSE
1066 
--                                                                      alu_bf_shift(5 downto 3) <="000";
1067 
--                                                              END IF;
1068 
--                                                      END IF;
1069 
                                        END IF;
1070 
--                                      byte <= '0';
1071 
                                        memread <= "1111";
1072 
                                        FC(1) <= NOT setstate(1) OR (PCbase AND NOT setstate(0));
1073 
                                        FC(0) <= setstate(1) AND (NOT PCbase OR setstate(0));
1074 
                                        IF interrupt='1' THEN
1075 
                                                FC(1 downto 0) <= "11";
1076 
                                        END IF;
1077 
                                        IF (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR (stop='1' AND interrupt='0') OR set_exec(opcCHK)='1' THEN
1078 
                                                state <= "01";
1079 
                                                memmask <= "111111";
1080 
                                        ELSIF execOPC='1' AND exec_write_back='1' THEN
1081 
                                                state <= "11";
1082 
                                                FC(1 downto 0) <= "01";
1083 
                                                memmask <= wbmemmask;
1084 
--                                              IF datatype="00" THEN
1085 
--                                                      byte <= '1';
1086 
--                                              END IF;
1087 
                                        ELSE
1088 
                                                state <= setstate;
1089 
                                                IF setstate="01" THEN
1090 
                                                        memmask <= "111111";
1091 
                                                        wbmemmask <= "111111";
1092 
                                                ELSIF exec(get_bfoffset)='1' THEN
1093 
                                                        memmask <= set_memmask;
1094 
                                                        wbmemmask <= set_memmask;
1095 
                                                        oddout <= set_oddout;
1096 
                                                ELSIF set(longaktion)='1' THEN
1097 
                                                        memmask <= "100001";
1098 
                                                        wbmemmask <= "100001";
1099 
                                                        oddout <= '0';
1100 
                                                ELSIF set_datatype="00" AND setstate(1)='1' THEN
1101 
                                                        memmask <= "101111";
1102 
                                                        wbmemmask <= "101111";
1103 
                                                        IF set(mem_byte)='1' THEN
1104 
                                                                oddout <= '0';
1105 
                                                        ELSE
1106 
                                                                oddout <= '1';
1107 
                                                        END IF;
1108 
                                                ELSE
1109 
                                                        memmask <= "100111";
1110 
                                                        wbmemmask <= "100111";
1111 
                                                        oddout <= '0';
1112 
                                                END IF;
1113 
                                        END IF;
1114 
 
1115 
                                        IF decodeOPC='1' THEN
1116 
                                                rot_bits <= set_rot_bits;
1117 
                                                writePCbig <= '0';
1118 
                                        ELSE
1119 
                                                writePCbig <= set_writePCbig OR writePCbig;
1120 
                                        END IF;
1121 
                                        IF decodeOPC='1' OR exec(ld_rot_cnt)='1' OR rot_cnt/="000001" THEN
1122 
                                                rot_cnt <= set_rot_cnt;
1123 
                                        END IF;
1124 
--                                      IF setstate(1)='1' AND set_datatype="00" THEN
1125 
--                                              byte <= '1';
1126 
--                                      END IF;
1127 
 
1128 
                                        IF set_Suppress_Base='1' THEN
1129 
                                                Suppress_Base <= '1';
1130 
                                        ELSIF setstate(1)='1' OR (ea_only='1' AND set(get_ea_now)='1') THEN
1131 
                                                Suppress_Base <= '0';
1132 
                                        END IF;
1133 
                                        IF getbrief='1' THEN
1134 
                                                IF state(1)='1' THEN
1135 
                                                        brief <= last_opc_read(15 downto 0);
1136 
                                                ELSE
1137 
                                                        brief <= data_read(15 downto 0);
1138 
                                                END IF;
1139 
                                        END IF;
1140 
 
1141 
                                        IF setopcode='1' AND berr='0' THEN
1142 
                                                IF state="00" THEN
1143 
                                                        opcode <= data_read(15 downto 0);
1144 
                                                ELSE
1145 
                                                        opcode <= last_opc_read(15 downto 0);
1146 
                                                END IF;
1147 
                                                nextpass <= '0';
1148 
                                        ELSIF setinterrupt='1' OR setopcode='1' THEN
1149 
                                                opcode <= X"4E71";              --nop
1150 
                                                nextpass <= '0';
1151 
                                        ELSE
1152 
--                                              IF setnextpass='1' OR (regdirectsource='1' AND state="00") THEN
1153 
                                                IF setnextpass='1' OR regdirectsource='1' THEN
1154 
                                                        nextpass <= '1';
1155 
                                                END IF;
1156 
                                        END IF;
1157 
 
1158 
                                        IF decodeOPC='1' OR interrupt='1' THEN
1159 
                                                trap_SR <= FlagsSR;
1160 
                                        END IF;
1161 
                                END IF;
1162 
                        END IF;
1163 
                END IF;
1164 
 
1165 
                IF rising_edge(clk) THEN
1166 
                IF Reset = '1' THEN
1167 
                                PCbase <= '1';
1168 
                        ELSIF clkena_lw='1' THEN
1169 
                                PCbase <= set_PCbase OR PCbase;
1170 
                                IF setexecOPC='1' OR (state(1)='1' AND movem_run='0') THEN
1171 
                                        PCbase <= '0';
1172 
                                END IF;
1173 
                        END IF;
1174 
                        IF clkena_lw='1' THEN
1175 
                                exec <= set;
1176 
                                exec_tas <= '0';
1177 
                                exec(subidx) <= set(presub) or set(subidx);
1178 
                                IF setexecOPC='1' THEN
1179 
                                        exec <= set_exec OR set;
1180 
                                        exec_tas <= set_exec_tas;
1181 
                                END IF;
1182 
                                exec(get_2ndOPC) <= set(get_2ndOPC) OR setopcode;
1183 
                        END IF;
1184 
                END IF;
1185 
        END PROCESS;
1186 
 
1187 
------------------------------------------------------------------------------
1188 
--prepare Bitfield Parameters
1189 
------------------------------------------------------------------------------
1190 
PROCESS (clk, Reset, sndOPC, reg_QA, reg_QB, bf_width, bf_offset, bf_bhits, opcode, setstate, bf_shift)
1191 
        BEGIN
1192 
                IF sndOPC(11)='1' THEN
1193 
                        bf_offset <= '0'&reg_QA(4 downto 0);
1194 
                ELSE
1195 
                        bf_offset <= '0'&sndOPC(10 downto 6);
1196 
                END IF;
1197 
                IF sndOPC(11)='1' THEN
1198 
                        bf_full_offset <= reg_QA;
1199 
                ELSE
1200 
                        bf_full_offset <= (others => '0');
1201 
                        bf_full_offset(4 downto 0) <= sndOPC(10 downto 6);
1202 
                END IF;
1203 
 
1204 
                bf_width(5) <= '0';
1205 
                IF sndOPC(5)='1' THEN
1206 
                        bf_width(4 downto 0) <= reg_QB(4 downto 0)-1;
1207 
                ELSE
1208 
                        bf_width(4 downto 0) <= sndOPC(4 downto 0)-1;
1209 
                END IF;
1210 
                bf_bhits <= bf_width+bf_offset;
1211 
                set_oddout <= NOT bf_bhits(3);
1212 
 
1213 
                IF opcode(10 downto 8)="111" THEN --INS
1214 
                        bf_loffset <= 32-bf_shift;
1215 
                ELSE
1216 
                        bf_loffset <= bf_shift;
1217 
                END IF;
1218 
                bf_loffset(5) <= '0';
1219 
--              IF set_exec(exec_BS)='1' THEN
1220 
--                      bf_width(4 downto 0)<="01111";
1221 
--                      bf_loffset(4 downto 0) <= "00000";
1222 
--              END IF;
1223 
 
1224 
                IF opcode(4 downto 3)="00" THEN
1225 
                        IF opcode(10 downto 8)="111" THEN --INS
1226 
                                bf_shift <= bf_bhits+1;
1227 
                        ELSE
1228 
                                bf_shift <= 31-bf_bhits;
1229 
                        END IF;
1230 
                        bf_shift(5) <= '0';
1231 
                ELSE
1232 
                        IF opcode(10 downto 8)="111" THEN --INS
1233 
                                bf_shift <= "011"&("001"+bf_bhits(2 downto 0));
1234 
                        ELSE
1235 
                                bf_shift <= "000"&("111"-bf_bhits(2 downto 0));
1236 
                        END IF;
1237 
                        bf_offset(4 downto 3) <= "00";
1238 
                END IF;
1239 
 
1240 
                        CASE bf_bhits(5 downto 3) IS
1241 
                                WHEN "000" =>
1242 
                                        set_memmask <= "101111";
1243 
                                WHEN "001" =>
1244 
                                        set_memmask <= "100111";
1245 
                                WHEN "010" =>
1246 
                                        set_memmask <= "100011";
1247 
                                WHEN "011" =>
1248 
                                        set_memmask <= "100001";
1249 
                                WHEN OTHERS =>
1250 
                                        set_memmask <= "100000";
1251 
                        END CASE;
1252 
                        IF setstate="00" THEN
1253 
                                set_memmask <= "100111";
1254 
                        END IF;
1255 
        END PROCESS;
1256 
 
1257 
------------------------------------------------------------------------------
1258 
--SR op
1259 
------------------------------------------------------------------------------
1260 
PROCESS (clk, Reset, FlagsSR, last_data_read, OP2out, exec)
1261 
        BEGIN
1262 
                IF exec(andiSR)='1' THEN
1263 
                        SRin <= FlagsSR AND last_data_read(15 downto 8);
1264 
                ELSIF exec(eoriSR)='1' THEN
1265 
                        SRin <= FlagsSR XOR last_data_read(15 downto 8);
1266 
                ELSIF exec(oriSR)='1' THEN
1267 
                        SRin <= FlagsSR OR last_data_read(15 downto 8);
1268 
                ELSE
1269 
                        SRin <= OP2out(15 downto 8);
1270 
                END IF;
1271 
 
1272 
                IF rising_edge(clk) THEN
1273 
                IF Reset='1' THEN
1274 
                                FlagsSR(5) <= '1';
1275 
                                FC(2) <= '1';
1276 
                                SVmode <= '1';
1277 
                                preSVmode <= '1';
1278 
                                FlagsSR(2 downto 0) <= "111";
1279 
                                make_trace <= '0';
1280 
                        ELSIF clkena_lw = '1' THEN
1281 
                                IF setopcode='1' THEN
1282 
                                        make_trace <= FlagsSR(7);
1283 
                                        IF set(changeMode)='1' THEN
1284 
                                                SVmode <= NOT SVmode;
1285 
                                        ELSE
1286 
                                                SVmode <= preSVmode;
1287 
                                        END IF;
1288 
                                END IF;
1289 
                                IF set(changeMode)='1' THEN
1290 
                                        preSVmode <= NOT preSVmode;
1291 
                                        FlagsSR(5) <= NOT preSVmode;
1292 
                                        FC(2) <= NOT preSVmode;
1293 
                                END IF;
1294 
                                IF micro_state=trap3 THEN
1295 
                                        FlagsSR(7) <= '0';
1296 
                                END IF;
1297 
                                IF trap_trace='1' AND state="10" THEN
1298 
                                        make_trace <= '0';
1299 
                                END IF;
1300 
                                IF exec(directSR)='1' OR set_stop='1' THEN
1301 
                                        FlagsSR <= data_read(15 downto 8);
1302 
                                END IF;
1303 
                                IF interrupt='1' AND trap_interrupt='1' THEN
1304 
                                        FlagsSR(2 downto 0) <=rIPL_nr;
1305 
                                END IF;
1306 
--                              IF exec(to_CCR)='1' AND exec(to_SR)='1' THEN
1307 
                                IF exec(to_SR)='1' THEN
1308 
                                        FlagsSR(7 downto 0) <= SRin;     --SR
1309 
                                        FC(2) <= SRin(5);
1310 
--                              END IF;
1311 
                                ELSIF exec(update_FC)='1' THEN
1312 
                                        FC(2) <= FlagsSR(5);
1313 
                                END IF;
1314 
                                IF interrupt='1' THEN
1315 
                                        FC(2) <= '1';
1316 
                                END IF;
1317 
                        END IF;
1318 
                END IF;
1319 
        END PROCESS;
1320 
 
1321 
-----------------------------------------------------------------------------
1322 
-- decode opcode
1323 
-----------------------------------------------------------------------------
1324 
PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, decodeOPC, state, setexecOPC, Flags, FlagsSR, direct_data, build_logical,
1325 
                 build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt,
1326 
                 SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype,
1327 
                 datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr,
1328 
                 long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr)
1329 
        BEGIN
1330 
                TG68_PC_brw <= '0';
1331 
                setstate <= "00";
1332 
                Regwrena_now <= '0';
1333 
                movem_presub <= '0';
1334 
                setnextpass <= '0';
1335 
                regdirectsource <= '0';
1336 
                setdisp <= '0';
1337 
                setdispbyte <= '0';
1338 
                getbrief <= '0';
1339 
                dest_areg <= '0';
1340 
                source_areg <= '0';
1341 
                data_is_source <= '0';
1342 
                write_back <= '0';
1343 
                setstackaddr <= '0';
1344 
                writePC <= '0';
1345 
                ea_build_now <= '0';
1346 
--              set_rot_bits <= "00";
1347 
                set_rot_bits <= opcode(4 downto 3);
1348 
                set_rot_cnt <= "000001";
1349 
                dest_hbits <= '0';
1350 
                source_lowbits <= '0';
1351 
                source_2ndHbits <= '0';
1352 
                source_2ndLbits <= '0';
1353 
                dest_2ndHbits <= '0';
1354 
                ea_only <= '0';
1355 
                set_direct_data <= '0';
1356 
                set_exec_tas <= '0';
1357 
                trap_illegal <='0';
1358 
                trap_addr_error <= '0';
1359 
                trap_priv <='0';
1360 
                trap_1010 <='0';
1361 
                trap_1111 <='0';
1362 
                trap_trap <='0';
1363 
                trap_trapv <= '0';
1364 
                trapmake <='0';
1365 
                set_vectoraddr <='0';
1366 
                writeSR <= '0';
1367 
                set_stop <= '0';
1368 
--              illegal_write_mode <= '0';
1369 
--              illegal_read_mode <= '0';
1370 
--              illegal_byteaddr <= '0';
1371 
                set_Z_error <= '0';
1372 
 
1373 
                next_micro_state <= idle;
1374 
                build_logical <= '0';
1375 
                build_bcd <= '0';
1376 
                skipFetch <= make_berr;
1377 
                set_writePCbig <= '0';
1378 
--              set_recall_last <= '0';
1379 
                set_Suppress_Base <= '0';
1380 
                set_PCbase <= '0';
1381 
 
1382 
                IF rot_cnt/="000001" THEN
1383 
                        set_rot_cnt <= rot_cnt-1;
1384 
                END IF;
1385 
                set_datatype <= datatype;
1386 
 
1387 
                set <= (OTHERS=>'0');
1388 
                set_exec <= (OTHERS=>'0');
1389 
                set(update_ld) <= '0';
1390 
--              odd_start <= '0';
1391 
------------------------------------------------------------------------------
1392 
--Sourcepass
1393 
------------------------------------------------------------------------------
1394 
                CASE opcode(7 downto 6) IS
1395 
                        WHEN "00" => datatype <= "00";          --Byte
1396 
                        WHEN "01" => datatype <= "01";          --Word
1397 
                        WHEN OTHERS => datatype <= "10";        --Long
1398 
                END CASE;
1399 
 
1400 
                IF trapmake='1' AND trapd='0' THEN
1401 
                        next_micro_state <= trap0;
1402 
                        IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
1403 
                                set(writePC_add) <= '1';
1404 
--                              set_datatype <= "10";
1405 
                        END IF;
1406 
                        IF preSVmode='0' THEN
1407 
                                set(changeMode) <= '1';
1408 
                        END IF;
1409 
                        setstate <= "01";
1410 
                END IF;
1411 
                IF interrupt='1' AND trap_berr='1' THEN
1412 
                        next_micro_state <= trap0;
1413 
                        IF preSVmode='0' THEN
1414 
                                set(changeMode) <= '1';
1415 
                        END IF;
1416 
                        setstate <= "01";
1417 
                END IF;
1418 
                IF micro_state=int1 OR (interrupt='1' AND trap_trace='1') THEN
1419 
                        next_micro_state <= trap0;
1420 
--                      IF cpu(0)='0' THEN
1421 
--                              set_datatype <= "10";
1422 
--                      END IF;
1423 
                        IF preSVmode='0' THEN
1424 
                                set(changeMode) <= '1';
1425 
                        END IF;
1426 
                        setstate <= "01";
1427 
                END IF;
1428 
 
1429 
                IF setexecOPC='1' AND FlagsSR(5)/=preSVmode THEN
1430 
                        set(changeMode) <= '1';
1431 
--                      setstate <= "01";
1432 
--                      next_micro_state <= nop;
1433 
                END IF;
1434 
 
1435 
                IF interrupt='1' AND trap_interrupt='1'THEN
1436 
--                      skipFetch <= '1';
1437 
                        next_micro_state <= int1;
1438 
                        set(update_ld) <= '1';
1439 
                        setstate <= "10";
1440 
                END IF;
1441 
 
1442 
                IF set(changeMode)='1' THEN
1443 
                        set(to_USP) <= '1';
1444 
                        set(from_USP) <= '1';
1445 
                        setstackaddr <='1';
1446 
                END IF;
1447 
 
1448 
                IF ea_only='0' AND set(get_ea_now)='1' THEN
1449 
                        setstate <= "10";
1450 
--                      set_recall_last <= '1';
1451 
--                      set(update_ld) <= '0';
1452 
                END IF;
1453 
 
1454 
                IF setstate(1)='1' AND set_datatype(1)='1' THEN
1455 
                        set(longaktion) <= '1';
1456 
                END IF;
1457 
 
1458 
                IF (ea_build_now='1' AND decodeOPC='1') OR exec(ea_build)='1' THEN
1459 
                        CASE opcode(5 downto 3) IS              --source
1460 
                                WHEN "010"|"011"|"100" =>                                               -- -(An)+
1461 
                                        set(get_ea_now) <='1';
1462 
                                        setnextpass <= '1';
1463 
                                        IF opcode(3)='1' THEN   --(An)+
1464 
                                                set(postadd) <= '1';
1465 
                                                IF opcode(2 downto 0)="111" THEN
1466 
                                                        set(use_SP) <= '1';
1467 
                                                END IF;
1468 
                                        END IF;
1469 
                                        IF opcode(5)='1' THEN   -- -(An)
1470 
                                                set(presub) <= '1';
1471 
                                                IF opcode(2 downto 0)="111" THEN
1472 
                                                        set(use_SP) <= '1';
1473 
                                                END IF;
1474 
                                        END IF;
1475 
                                WHEN "101" =>                           --(d16,An)
1476 
                                        next_micro_state <= ld_dAn1;
1477 
                                WHEN "110" =>                           --(d8,An,Xn)
1478 
                                        next_micro_state <= ld_AnXn1;
1479 
                                        getbrief <='1';
1480 
                                WHEN "111" =>
1481 
                                        CASE opcode(2 downto 0) IS
1482 
                                                WHEN "000" =>                           --(xxxx).w
1483 
                                                        next_micro_state <= ld_nn;
1484 
                                                WHEN "001" =>                           --(xxxx).l
1485 
                                                        set(longaktion) <= '1';
1486 
                                                        next_micro_state <= ld_nn;
1487 
                                                WHEN "010" =>                           --(d16,PC)
1488 
                                                        next_micro_state <= ld_dAn1;
1489 
                                                        set(dispouter) <= '1';
1490 
                                                        set_Suppress_Base <= '1';
1491 
                                                        set_PCbase <= '1';
1492 
                                                WHEN "011" =>                           --(d8,PC,Xn)
1493 
                                                        next_micro_state <= ld_AnXn1;
1494 
                                                        getbrief <= '1';
1495 
                                                        set(dispouter) <= '1';
1496 
                                                        set_Suppress_Base <= '1';
1497 
                                                        set_PCbase <= '1';
1498 
                                                WHEN "100" =>                           --#data
1499 
                                                        setnextpass <= '1';
1500 
                                                        set_direct_data <= '1';
1501 
                                                        IF datatype="10" THEN
1502 
                                                                set(longaktion) <= '1';
1503 
                                                        END IF;
1504 
                                                WHEN OTHERS => NULL;
1505 
                                        END CASE;
1506 
                                WHEN OTHERS => NULL;
1507 
                        END CASE;
1508 
                END IF;
1509 
------------------------------------------------------------------------------
1510 
--prepere opcode
1511 
------------------------------------------------------------------------------
1512 
                CASE opcode(15 downto 12) IS
1513 
-- 0000 ----------------------------------------------------------------------------
1514 
                        WHEN "0000" =>
1515 
                        IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
1516 
                                datatype <= "00";                               --Byte
1517 
                                set(use_SP) <= '1';             --addr+2
1518 
                                set(no_Flags) <='1';
1519 
                                IF opcode(7)='0' THEN  --to register
1520 
                                        set_exec(Regwrena) <= '1';
1521 
                                        set_exec(opcMOVE) <= '1';
1522 
                                        set(movepl) <= '1';
1523 
                                END IF;
1524 
                                IF decodeOPC='1' THEN
1525 
                                        IF opcode(6)='1' THEN
1526 
                                                set(movepl) <= '1';
1527 
                                        END IF;
1528 
                                        IF opcode(7)='0' THEN
1529 
                                                set_direct_data <= '1';         -- to register
1530 
                                        END IF;
1531 
                                        next_micro_state <= movep1;
1532 
                                END IF;
1533 
                                IF setexecOPC='1' THEN
1534 
                                        dest_hbits <='1';
1535 
                                END IF;
1536 
                        ELSE
1537 
                                IF opcode(8)='1' OR opcode(11 downto 9)="100" THEN              --Bits
1538 
                                        set_exec(opcBITS) <= '1';
1539 
                                        set_exec(ea_data_OP1) <= '1';
1540 
                                        IF opcode(7 downto 6)/="00" THEN
1541 
                                                IF opcode(5 downto 4)="00" THEN
1542 
                                                        set_exec(Regwrena) <= '1';
1543 
                                                END IF;
1544 
                                                write_back <= '1';
1545 
                                        END IF;
1546 
                                        IF opcode(5 downto 4)="00" THEN
1547 
                                                datatype <= "10";                       --Long
1548 
                                        ELSE
1549 
                                                datatype <= "00";                       --Byte
1550 
                                        END IF;
1551 
                                        IF opcode(8)='0' THEN
1552 
                                                IF decodeOPC='1' THEN
1553 
                                                        next_micro_state <= nop;
1554 
                                                        set(get_2ndOPC) <= '1';
1555 
                                                        set(ea_build) <= '1';
1556 
                                                END IF;
1557 
                                        ELSE
1558 
                                                ea_build_now <= '1';
1559 
                                        END IF;
1560 
                                ELSIF opcode(11 downto 9)="111" THEN            --MOVES not in 68000
1561 
                                        trap_illegal <= '1';
1562 
--                                      trap_addr_error <= '1';
1563 
                                        trapmake <= '1';
1564 
                                ELSE                                                            --andi, ...xxxi
1565 
                                        IF opcode(11 downto 9)="000" THEN       --ORI
1566 
                                                set_exec(opcOR) <= '1';
1567 
                                        END IF;
1568 
                                        IF opcode(11 downto 9)="001" THEN       --ANDI
1569 
                                                set_exec(opcAND) <= '1';
1570 
                                        END IF;
1571 
                                        IF opcode(11 downto 9)="010" OR opcode(11 downto 9)="011" THEN  --SUBI, ADDI
1572 
                                                set_exec(opcADD) <= '1';
1573 
                                        END IF;
1574 
                                        IF opcode(11 downto 9)="101" THEN       --EORI
1575 
                                                set_exec(opcEOR) <= '1';
1576 
                                        END IF;
1577 
                                        IF opcode(11 downto 9)="110" THEN       --CMPI
1578 
                                                set_exec(opcCMP) <= '1';
1579 
                                        END IF;
1580 
                                        IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec(opcAND) OR set_exec(opcOR) OR set_exec(opcEOR))='1' THEN           --SR
1581 
                                                IF decodeOPC='1' AND SVmode='0' AND opcode(6)='1' THEN  --SR
1582 
                                                        trap_priv <= '1';
1583 
                                                        trapmake <= '1';
1584 
                                                ELSE
1585 
                                                        set(no_Flags) <= '1';
1586 
                                                        IF decodeOPC='1' THEN
1587 
                                                                IF opcode(6)='1' THEN
1588 
                                                                        set(to_SR) <= '1';
1589 
                                                                END IF;
1590 
                                                                set(to_CCR) <= '1';
1591 
                                                                set(andiSR) <= set_exec(opcAND);
1592 
                                                                set(eoriSR) <= set_exec(opcEOR);
1593 
                                                                set(oriSR) <= set_exec(opcOR);
1594 
                                                                setstate <= "01";
1595 
                                                                next_micro_state <= nopnop;
1596 
                                                        END IF;
1597 
                                                END IF;
1598 
                                        ELSE
1599 
                                                IF decodeOPC='1' THEN
1600 
                                                        next_micro_state <= andi;
1601 
                                                        set(get_2ndOPC) <='1';
1602 
                                                        set(ea_build) <= '1';
1603 
                                                        set_direct_data <= '1';
1604 
                                                        IF datatype="10" THEN
1605 
                                                                set(longaktion) <= '1';
1606 
                                                        END IF;
1607 
                                                END IF;
1608 
                                                IF opcode(5 downto 4)/="00" THEN
1609 
                                                        set_exec(ea_data_OP1) <= '1';
1610 
                                                END IF;
1611 
                                                IF opcode(11 downto 9)/="110" THEN      --CMPI
1612 
                                                        IF opcode(5 downto 4)="00" THEN
1613 
                                                                set_exec(Regwrena) <= '1';
1614 
                                                        END IF;
1615 
                                                        write_back <= '1';
1616 
                                                END IF;
1617 
                                                IF opcode(10 downto 9)="10" THEN        --CMPI, SUBI
1618 
                                                        set(addsub) <= '1';
1619 
                                                END IF;
1620 
                                        END IF;
1621 
                                END IF;
1622 
                        END IF;
1623 
 
1624 
-- 0001, 0010, 0011 -----------------------------------------------------------------
1625 
                        WHEN "0001"|"0010"|"0011" =>                            --move.b, move.l, move.w
1626 
                                set_exec(opcMOVE) <= '1';
1627 
                                ea_build_now <= '1';
1628 
                                IF opcode(8 downto 6)="001" THEN
1629 
                                        set(no_Flags) <= '1';
1630 
                                END IF;
1631 
                                IF opcode(5 downto 4)="00" THEN --Dn, An
1632 
                                        IF opcode(8 downto 7)="00" THEN
1633 
                                                set_exec(Regwrena) <= '1';
1634 
                                        END IF;
1635 
                                END IF;
1636 
                                CASE opcode(13 downto 12) IS
1637 
                                        WHEN "01" => datatype <= "00";          --Byte
1638 
                                        WHEN "10" => datatype <= "10";          --Long
1639 
                                        WHEN OTHERS => datatype <= "01";        --Word
1640 
                                END CASE;
1641 
                                source_lowbits <= '1';                                  -- Dn=>  An=>
1642 
                                IF opcode(3)='1' THEN
1643 
                                        source_areg <= '1';
1644 
                                END IF;
1645 
 
1646 
                                IF nextpass='1' OR opcode(5 downto 4)="00" THEN
1647 
                                        dest_hbits <= '1';
1648 
                                        IF opcode(8 downto 6)/="000" THEN
1649 
                                                dest_areg <= '1';
1650 
                                        END IF;
1651 
                                END IF;
1652 
--                              IF setstate="10" THEN
1653 
--                                      set(update_ld) <= '0';
1654 
--                              END IF;
1655 
--
1656 
                                IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
1657 
                                        CASE opcode(8 downto 6) IS              --destination
1658 
                                                WHEN "000"|"001" =>                                             --Dn,An
1659 
                                                                set_exec(Regwrena) <= '1';
1660 
                                                WHEN "010"|"011"|"100" =>                                       --destination -(an)+
1661 
                                                        IF opcode(6)='1' THEN   --(An)+
1662 
                                                                set(postadd) <= '1';
1663 
                                                                IF opcode(11 downto 9)="111" THEN
1664 
                                                                        set(use_SP) <= '1';
1665 
                                                                END IF;
1666 
                                                        END IF;
1667 
                                                        IF opcode(8)='1' THEN   -- -(An)
1668 
                                                                set(presub) <= '1';
1669 
                                                                IF opcode(11 downto 9)="111" THEN
1670 
                                                                        set(use_SP) <= '1';
1671 
                                                                END IF;
1672 
                                                        END IF;
1673 
                                                        setstate <= "11";
1674 
                                                        next_micro_state <= nop;
1675 
                                                        IF nextpass='0' THEN
1676 
                                                                set(write_reg) <= '1';
1677 
                                                        END IF;
1678 
                                                WHEN "101" =>                           --(d16,An)
1679 
                                                        next_micro_state <= st_dAn1;
1680 
--                                                      getbrief <= '1';
1681 
                                                WHEN "110" =>                           --(d8,An,Xn)
1682 
                                                        next_micro_state <= st_AnXn1;
1683 
                                                        getbrief <= '1';
1684 
                                                WHEN "111" =>
1685 
                                                        CASE opcode(11 downto 9) IS
1686 
                                                                WHEN "000" =>                           --(xxxx).w
1687 
                                                                        next_micro_state <= st_nn;
1688 
                                                                WHEN "001" =>                           --(xxxx).l
1689 
                                                                        set(longaktion) <= '1';
1690 
                                                                        next_micro_state <= st_nn;
1691 
                                                                WHEN OTHERS => NULL;
1692 
                                                        END CASE;
1693 
                                                WHEN OTHERS => NULL;
1694 
                                        END CASE;
1695 
                                END IF;
1696 
---- 0100 ----------------------------------------------------------------------------
1697 
                        WHEN "0100" =>                          --rts_group
1698 
                                IF opcode(8)='1' THEN           --lea
1699 
                                        IF opcode(6)='1' THEN           --lea
1700 
                                                IF opcode(7)='1' THEN
1701 
                                                        source_lowbits <= '1';
1702 
--                                                      IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN             --ext
1703 
                                                        IF opcode(5 downto 4)="00" THEN         --extb.l
1704 
                                                                set_exec(opcEXT) <= '1';
1705 
                                                                set_exec(opcMOVE) <= '1';
1706 
                                                                set_exec(Regwrena) <= '1';
1707 
--                                                              IF opcode(6)='0' THEN
1708 
--                                                                      datatype <= "01";               --WORD
1709 
--                                                              END IF;
1710 
                                                        ELSE
1711 
                                                                source_areg <= '1';
1712 
                                                                ea_only <= '1';
1713 
                                                                set_exec(Regwrena) <= '1';
1714 
                                                                set_exec(opcMOVE) <='1';
1715 
                                                                set(no_Flags) <='1';
1716 
                                                                IF opcode(5 downto 3)="010" THEN        --lea (Am),An
1717 
                                                                        dest_areg <= '1';
1718 
                                                                        dest_hbits <= '1';
1719 
                                                                ELSE
1720 
                                                                        ea_build_now <= '1';
1721 
                                                                END IF;
1722 
                                                                IF set(get_ea_now)='1' THEN
1723 
                                                                        setstate <= "01";
1724 
                                                                        set_direct_data <= '1';
1725 
                                                                END IF;
1726 
                                                                IF setexecOPC='1' THEN
1727 
                                                                        dest_areg <= '1';
1728 
                                                                        dest_hbits <= '1';
1729 
                                                                END IF;
1730 
                                                        END IF;
1731 
                                                ELSE
1732 
                                                        trap_illegal <= '1';
1733 
                                                        trapmake <= '1';
1734 
                                                END IF;
1735 
                                        ELSE                                                            --chk
1736 
                                                IF opcode(7)='1' THEN
1737 
                                                        datatype <= "01";       --Word
1738 
                                                                set(trap_chk) <= '1';
1739 
                                                        IF (c_out(1)='0' OR OP1out(15)='1' OR OP2out(15)='1') AND exec(opcCHK)='1' THEN
1740 
                                                                trapmake <= '1';
1741 
                                                        END IF;
1742 
                                                ELSIF cpu(1)='1' THEN   --chk long for 68020
1743 
                                                        datatype <= "10";       --Long
1744 
                                                                set(trap_chk) <= '1';
1745 
                                                        IF (c_out(2)='1' OR OP1out(31)='1' OR OP2out(31)='1') AND exec(opcCHK)='1' THEN
1746 
                                                                trapmake <= '1';
1747 
                                                        END IF;
1748 
                                                ELSE
1749 
                                                        trap_illegal <= '1';            -- chk long for 68020
1750 
                                                        trapmake <= '1';
1751 
                                                END IF;
1752 
                                                IF opcode(7)='1' OR cpu(1)='1' THEN
1753 
                                                        IF (nextpass='1' OR opcode(5 downto 4)="00") AND exec(opcCHK)='0' AND micro_state=idle THEN
1754 
                                                                set_exec(opcCHK) <= '1';
1755 
                                                        END IF;
1756 
                                                        ea_build_now <= '1';
1757 
                                                        set(addsub) <= '1';
1758 
                                                        IF setexecOPC='1' THEN
1759 
                                                                dest_hbits <= '1';
1760 
                                                                source_lowbits <='1';
1761 
                                                        END IF;
1762 
                                                END IF;
1763 
                                        END IF;
1764 
                                ELSE
1765 
                                        CASE opcode(11 downto 9) IS
1766 
                                                WHEN "000"=>
1767 
                                                        IF opcode(7 downto 6)="11" THEN                                 --move from SR
1768 
                                                                IF SR_Read=0 OR (cpu(0)='0' AND SR_Read=2) OR SVmode='1'  THEN
1769 
--                                                              IF SVmode='1'  THEN
1770 
                                                                        ea_build_now <= '1';
1771 
                                                                        set_exec(opcMOVESR) <= '1';
1772 
                                                                        datatype <= "01";
1773 
                                                                        write_back <='1';                                                       -- im 68000 wird auch erst gelesen
1774 
                                                                        IF cpu(0)='1' AND state="10" THEN
1775 
                                                                                skipFetch <= '1';
1776 
                                                                        END IF;
1777 
                                                                        IF opcode(5 downto 4)="00" THEN
1778 
                                                                                set_exec(Regwrena) <= '1';
1779 
                                                                        END IF;
1780 
                                                                ELSE
1781 
                                                                        trap_priv <= '1';
1782 
                                                                        trapmake <= '1';
1783 
                                                                END IF;
1784 
                                                        ELSE                                                                    --negx
1785 
                                                                ea_build_now <= '1';
1786 
                                                                set_exec(use_XZFlag) <= '1';
1787 
                                                                write_back <='1';
1788 
                                                                set_exec(opcADD) <= '1';
1789 
                                                                set(addsub) <= '1';
1790 
                                                                source_lowbits <= '1';
1791 
                                                                IF opcode(5 downto 4)="00" THEN
1792 
                                                                        set_exec(Regwrena) <= '1';
1793 
                                                                END IF;
1794 
                                                                IF setexecOPC='1' THEN
1795 
                                                                        set(OP1out_zero) <= '1';
1796 
                                                                END IF;
1797 
                                                        END IF;
1798 
                                                WHEN "001"=>
1799 
                                                        IF opcode(7 downto 6)="11" THEN                                 --move from CCR 68010
1800 
                                                                IF SR_Read=1 OR (cpu(0)='1' AND SR_Read=2) THEN
1801 
                                                                        ea_build_now <= '1';
1802 
                                                                        set_exec(opcMOVESR) <= '1';
1803 
                                                                        datatype <= "01";
1804 
                                                                        write_back <='1';                                                       -- im 68000 wird auch erst gelesen
1805 
--                                                                      IF state="10" THEN
1806 
--                                                                              skipFetch <= '1';
1807 
--                                                                      END IF;
1808 
                                                                        IF opcode(5 downto 4)="00" THEN
1809 
                                                                                set_exec(Regwrena) <= '1';
1810 
                                                                        END IF;
1811 
                                                                ELSE
1812 
                                                                        trap_illegal <= '1';
1813 
                                                                        trapmake <= '1';
1814 
                                                                END IF;
1815 
                                                        ELSE                                                                                    --clr
1816 
                                                                ea_build_now <= '1';
1817 
                                                                write_back <='1';
1818 
                                                                set_exec(opcAND) <= '1';
1819 
                                                        IF cpu(0)='1' AND state="10" THEN
1820 
                                                                skipFetch <= '1';
1821 
                                                        END IF;
1822 
                                                                IF setexecOPC='1' THEN
1823 
                                                                        set(OP1out_zero) <= '1';
1824 
                                                                END IF;
1825 
                                                                IF opcode(5 downto 4)="00" THEN
1826 
                                                                        set_exec(Regwrena) <= '1';
1827 
                                                                END IF;
1828 
                                                        END IF;
1829 
                                                WHEN "010"=>
1830 
                                                        ea_build_now <= '1';
1831 
                                                        IF opcode(7 downto 6)="11" THEN                                 --move to CCR
1832 
                                                                datatype <= "01";
1833 
                                                                source_lowbits <= '1';
1834 
                                                                IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
1835 
                                                                        set(to_CCR) <= '1';
1836 
                                                                END IF;
1837 
                                                        ELSE                                                                                    --neg
1838 
                                                                write_back <='1';
1839 
                                                                set_exec(opcADD) <= '1';
1840 
                                                                set(addsub) <= '1';
1841 
                                                                source_lowbits <= '1';
1842 
                                                                IF opcode(5 downto 4)="00" THEN
1843 
                                                                        set_exec(Regwrena) <= '1';
1844 
                                                                END IF;
1845 
                                                                IF setexecOPC='1' THEN
1846 
                                                                        set(OP1out_zero) <= '1';
1847 
                                                                END IF;
1848 
                                                        END IF;
1849 
                                                WHEN "011"=>                                                                            --not, move toSR
1850 
                                                        IF opcode(7 downto 6)="11" THEN                                 --move to SR
1851 
                                                                IF SVmode='1' THEN
1852 
                                                                        ea_build_now <= '1';
1853 
                                                                        datatype <= "01";
1854 
                                                                        source_lowbits <= '1';
1855 
                                                                        IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
1856 
                                                                                set(to_SR) <= '1';
1857 
                                                                                set(to_CCR) <= '1';
1858 
                                                                        END IF;
1859 
                                                                        IF exec(to_SR)='1' OR (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
1860 
                                                                                setstate <="01";
1861 
                                                                        END IF;
1862 
                                                                ELSE
1863 
                                                                        trap_priv <= '1';
1864 
                                                                        trapmake <= '1';
1865 
                                                                END IF;
1866 
                                                        ELSE                                                                                    --not
1867 
                                                                ea_build_now <= '1';
1868 
                                                                write_back <='1';
1869 
                                                                set_exec(opcEOR) <= '1';
1870 
                                                                set_exec(ea_data_OP1) <= '1';
1871 
                                                                IF opcode(5 downto 3)="000" THEN
1872 
                                                                        set_exec(Regwrena) <= '1';
1873 
                                                                END IF;
1874 
                                                                IF setexecOPC='1' THEN
1875 
                                                                        set(OP2out_one) <= '1';
1876 
                                                                END IF;
1877 
                                                        END IF;
1878 
                                                WHEN "100"|"110"=>
1879 
                                                        IF opcode(7)='1' THEN                   --movem, ext
1880 
                                                                IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN              --ext
1881 
                                                                        source_lowbits <= '1';
1882 
                                                                        set_exec(opcEXT) <= '1';
1883 
                                                                        set_exec(opcMOVE) <= '1';
1884 
                                                                        set_exec(Regwrena) <= '1';
1885 
                                                                        IF opcode(6)='0' THEN
1886 
                                                                                datatype <= "01";               --WORD
1887 
                                                                        END IF;
1888 
                                                                ELSE                                                                                                    --movem
1889 
--                                                              IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN      --MOVEM
1890 
                                                                        ea_only <= '1';
1891 
                                                                        set(no_Flags) <= '1';
1892 
                                                                        IF opcode(6)='0' THEN
1893 
                                                                                datatype <= "01";               --Word transfer
1894 
                                                                        END IF;
1895 
                                                                        IF (opcode(5 downto 3)="100" OR opcode(5 downto 3)="011") AND state="01" THEN   -- -(An), (An)+
1896 
                                                                                set_exec(save_memaddr) <= '1';
1897 
                                                                                set_exec(Regwrena) <= '1';
1898 
                                                                        END IF;
1899 
                                                                        IF opcode(5 downto 3)="100" THEN        -- -(An)
1900 
                                                                                movem_presub <= '1';
1901 
                                                                                set(subidx) <= '1';
1902 
                                                                        END IF;
1903 
                                                                        IF state="10" THEN
1904 
                                                                                set(Regwrena) <= '1';
1905 
                                                                                set(opcMOVE) <= '1';
1906 
                                                                        END IF;
1907 
                                                                        IF decodeOPC='1' THEN
1908 
                                                                                set(get_2ndOPC) <='1';
1909 
                                                                                IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
1910 
                                                                                        next_micro_state <= movem1;
1911 
                                                                                ELSE
1912 
                                                                                        next_micro_state <= nop;
1913 
                                                                                        set(ea_build) <= '1';
1914 
                                                                                END IF;
1915 
                                                                        END IF;
1916 
                                                                        IF set(get_ea_now)='1' THEN
1917 
                                                                                IF movem_run='1' THEN
1918 
                                                                                        set(movem_action) <= '1';
1919 
                                                                                        IF opcode(10)='0' THEN
1920 
                                                                                                setstate <="11";
1921 
                                                                                                set(write_reg) <= '1';
1922 
                                                                                        ELSE
1923 
                                                                                                setstate <="10";
1924 
                                                                                        END IF;
1925 
                                                                                        next_micro_state <= movem2;
1926 
                                                                                        set(mem_addsub) <= '1';
1927 
                                                                                ELSE
1928 
                                                                                        setstate <="01";
1929 
                                                                                END IF;
1930 
                                                                        END IF;
1931 
                                                                END IF;
1932 
                                                        ELSE
1933 
                                                                IF opcode(10)='1' THEN                                          --MUL.L, DIV.L 68020
1934 
         --FPGA Multiplier for long
1935 
                                                                        IF MUL_Hardware=1 AND (opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
1936 
                                                                                IF decodeOPC='1' THEN
1937 
                                                                                        next_micro_state <= nop;
1938 
                                                                                        set(get_2ndOPC) <= '1';
1939 
                                                                                        set(ea_build) <= '1';
1940 
                                                                                END IF;
1941 
                                                                                IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND exec(ea_build)='1') THEN
1942 
                                                                                        dest_2ndHbits <= '1';
1943 
                                                                                        datatype <= "10";
1944 
                                                                                        set(opcMULU) <= '1';
1945 
                                                                                        set(write_lowlong) <= '1';
1946 
                                                                                        IF sndOPC(10)='1' THEN
1947 
                                                                                                setstate <="01";
1948 
                                                                                                next_micro_state <= mul_end2;
1949 
                                                                                        END IF;
1950 
                                                                                        set(Regwrena) <= '1';
1951 
                                                                                END IF;
1952 
                                                                                source_lowbits <='1';
1953 
                                                                                datatype <= "10";
1954 
 
1955 
         --no FPGA Multplier
1956 
                                                                        ELSIF (opcode(6)='1' AND (DIV_Mode=1 OR (cpu(1)='1' AND DIV_Mode=2))) OR
1957 
                                                                           (opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
1958 
                                                                                IF decodeOPC='1' THEN
1959 
                                                                                        next_micro_state <= nop;
1960 
                                                                                        set(get_2ndOPC) <= '1';
1961 
                                                                                        set(ea_build) <= '1';
1962 
                                                                                END IF;
1963 
                                                                                IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND exec(ea_build)='1')THEN
1964 
                                                                                        setstate <="01";
1965 
                                                                                        dest_2ndHbits <= '1';
1966 
                                                                                        source_2ndLbits <= '1';
1967 
                                                                                        IF opcode(6)='1' THEN
1968 
                                                                                                next_micro_state <= div1;
1969 
                                                                                        ELSE
1970 
                                                                                                next_micro_state <= mul1;
1971 
                                                                                                set(ld_rot_cnt) <= '1';
1972 
                                                                                        END IF;
1973 
                                                                                END IF;
1974 
                                                                                IF z_error='0' AND set_V_Flag='0' AND set(opcDIVU)='1' THEN
1975 
                                                                                        set(Regwrena) <= '1';
1976 
                                                                                END IF;
1977 
                                                                                source_lowbits <='1';
1978 
                                                                                IF nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
1979 
                                                                                        dest_hbits <= '1';
1980 
                                                                                END IF;
1981 
                                                                                datatype <= "10";
1982 
                                                                        ELSE
1983 
                                                                                trap_illegal <= '1';
1984 
                                                                                trapmake <= '1';
1985 
                                                                        END IF;
1986 
 
1987 
                                                                ELSE                                                    --pea, swap
1988 
                                                                        IF opcode(6)='1' THEN
1989 
                                                                                datatype <= "10";
1990 
                                                                                IF opcode(5 downto 3)="000" THEN                --swap
1991 
                                                                                        set_exec(opcSWAP) <= '1';
1992 
                                                                                        set_exec(Regwrena) <= '1';
1993 
                                                                                ELSIF opcode(5 downto 3)="001" THEN             --bkpt
1994 
 
1995 
                                                                                ELSE                                                                    --pea
1996 
                                                                                        ea_only <= '1';
1997 
                                                                                        ea_build_now <= '1';
1998 
                                                                                        IF nextpass='1' AND micro_state=idle THEN
1999 
                                                                                                set(presub) <= '1';
2000 
                                                                                                setstackaddr <='1';
2001 
                                                                                                setstate <="11";
2002 
                                                                                                next_micro_state <= nop;
2003 
                                                                                        END IF;
2004 
                                                                                        IF set(get_ea_now)='1' THEN
2005 
                                                                                                setstate <="01";
2006 
                                                                                        END IF;
2007 
                                                                                END IF;
2008 
                                                                        ELSE
2009 
                                                                                IF opcode(5 downto 3)="001" THEN --link.l
2010 
                                                                                        datatype <= "10";
2011 
                                                                                        set_exec(opcADD) <= '1';                                                --for displacement
2012 
                                                                                        set_exec(Regwrena) <= '1';
2013 
                                                                                        set(no_Flags) <= '1';
2014 
                                                                                        IF decodeOPC='1' THEN
2015 
                                                                                                set(linksp) <= '1';
2016 
                                                                                                set(longaktion) <= '1';
2017 
                                                                                                next_micro_state <= link1;
2018 
                                                                                                set(presub) <= '1';
2019 
                                                                                                setstackaddr <='1';
2020 
                                                                                                set(mem_addsub) <= '1';
2021 
                                                                                                source_lowbits <= '1';
2022 
                                                                                                source_areg <= '1';
2023 
                                                                                                set(store_ea_data) <= '1';
2024 
                                                                                        END IF;
2025 
                                                                                ELSE                                            --nbcd
2026 
                                                                                        ea_build_now <= '1';
2027 
                                                                                        set_exec(use_XZFlag) <= '1';
2028 
                                                                                        write_back <='1';
2029 
                                                                                        set_exec(opcADD) <= '1';
2030 
                                                                                        set_exec(opcSBCD) <= '1';
2031 
                                                                                        set(addsub) <= '1';
2032 
                                                                                        source_lowbits <= '1';
2033 
                                                                                        IF opcode(5 downto 4)="00" THEN
2034 
                                                                                                set_exec(Regwrena) <= '1';
2035 
                                                                                        END IF;
2036 
                                                                                        IF setexecOPC='1' THEN
2037 
                                                                                                set(OP1out_zero) <= '1';
2038 
                                                                                        END IF;
2039 
                                                                                END IF;
2040 
                                                                        END IF;
2041 
                                                                END IF;
2042 
                                                        END IF;
2043 
--0x4AXX
2044 
                                                WHEN "101"=>                                            --tst, tas  4aFC - illegal
2045 
--                                                      IF opcode(7 downto 2)="111111" THEN   --illegal
2046 
                                                        IF opcode(7 downto 3)="11111" AND opcode(2 downto 1)/="00" THEN   --0x4AFC illegal  --0x4AFB BKP Sinclair QL
2047 
                                                                trap_illegal <= '1';
2048 
                                                                trapmake <= '1';
2049 
                                                        ELSE
2050 
                                                                ea_build_now <= '1';
2051 
                                                                IF setexecOPC='1' THEN
2052 
                                                                        source_lowbits <= '1';
2053 
                                                                        IF opcode(3)='1' THEN                   --MC68020...
2054 
                                                                                source_areg <= '1';
2055 
                                                                        END IF;
2056 
                                                                END IF;
2057 
                                                                set_exec(opcMOVE) <= '1';
2058 
                                                                IF opcode(7 downto 6)="11" THEN         --tas
2059 
                                                                        set_exec_tas <= '1';
2060 
                                                                        write_back <= '1';
2061 
                                                                        datatype <= "00";                               --Byte
2062 
                                                                        IF opcode(5 downto 4)="00" THEN
2063 
                                                                                set_exec(Regwrena) <= '1';
2064 
                                                                        END IF;
2065 
                                                                END IF;
2066 
                                                        END IF;
2067 
----                                            WHEN "110"=>
2068 
                                                WHEN "111"=>                                    --4EXX
2069 
--
2070 
--                                                                                      ea_only <= '1';
2071 
--                                                                                      ea_build_now <= '1';
2072 
--                                                                                      IF nextpass='1' AND micro_state=idle THEN
2073 
--                                                                                              set(presub) <= '1';
2074 
--                                                                                              setstackaddr <='1';
2075 
--                                                                                              set(mem_addsub) <= '1';
2076 
--                                                                                              setstate <="11";
2077 
--                                                                                              next_micro_state <= nop;
2078 
--                                                                                      END IF;
2079 
--                                                                                      IF set(get_ea_now)='1' THEN
2080 
--                                                                                              setstate <="01";
2081 
--                                                                                      END IF;
2082 
--
2083 
 
2084 
 
2085 
 
2086 
                                                        IF opcode(7)='1' THEN           --jsr, jmp
2087 
                                                                datatype <= "10";
2088 
                                                                ea_only <= '1';
2089 
                                                                ea_build_now <= '1';
2090 
                                                                IF exec(ea_to_pc)='1' THEN
2091 
                                                                        next_micro_state <= nop;
2092 
                                                                END IF;
2093 
                                                                IF nextpass='1' AND micro_state=idle AND opcode(6)='0' THEN
2094 
                                                                        set(presub) <= '1';
2095 
                                                                        setstackaddr <='1';
2096 
                                                                        setstate <="11";
2097 
                                                                        next_micro_state <= nopnop;
2098 
                                                                END IF;
2099 
-- achtung buggefahr
2100 
                                                                IF micro_state=ld_AnXn1 AND brief(8)='0'THEN                     --JMP/JSR n(Ax,Dn)
2101 
                                                                        skipFetch <= '1';
2102 
                                                                END IF;
2103 
                                                                IF state="00" THEN
2104 
                                                                        writePC <= '1';
2105 
                                                                END IF;
2106 
                                                                set(hold_dwr) <= '1';
2107 
                                                                IF set(get_ea_now)='1' THEN                                     --jsr
2108 
                                                                        IF exec(longaktion)='0' OR long_done='1' THEN
2109 
                                                                                skipFetch <= '1';
2110 
                                                                        END IF;
2111 
                                                                        setstate <="01";
2112 
                                                                        set(ea_to_pc) <= '1';
2113 
                                                                END IF;
2114 
                                                        ELSE                                            --
2115 
                                                                CASE opcode(6 downto 0) IS
2116 
                                                                        WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"|           --trap
2117 
                                                                             "1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" =>         --trap
2118 
                                                                                        trap_trap <='1';
2119 
                                                                                        trapmake <= '1';
2120 
                                                                        WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111"=>          --link word
2121 
                                                                                datatype <= "10";
2122 
                                                                                set_exec(opcADD) <= '1';                                                --for displacement
2123 
                                                                                set_exec(Regwrena) <= '1';
2124 
                                                                                set(no_Flags) <= '1';
2125 
                                                                                IF decodeOPC='1' THEN
2126 
                                                                                        next_micro_state <= link1;
2127 
                                                                                        set(presub) <= '1';
2128 
                                                                                        setstackaddr <='1';
2129 
                                                                                        set(mem_addsub) <= '1';
2130 
                                                                                        source_lowbits <= '1';
2131 
                                                                                        source_areg <= '1';
2132 
                                                                                        set(store_ea_data) <= '1';
2133 
                                                                                END IF;
2134 
 
2135 
                                                                        WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" =>         --unlink
2136 
                                                                                datatype <= "10";
2137 
                                                                                set_exec(Regwrena) <= '1';
2138 
                                                                                set_exec(opcMOVE) <= '1';
2139 
                                                                                set(no_Flags) <= '1';
2140 
                                                                                IF decodeOPC='1' THEN
2141 
                                                                                        setstate <= "01";
2142 
                                                                                        next_micro_state <= unlink1;
2143 
                                                                                        set(opcMOVE) <= '1';
2144 
                                                                                        set(Regwrena) <= '1';
2145 
                                                                                        setstackaddr <='1';
2146 
                                                                                        source_lowbits <= '1';
2147 
                                                                                        source_areg <= '1';
2148 
                                                                                END IF;
2149 
 
2150 
                                                                        WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" =>         --move An,USP
2151 
                                                                                IF SVmode='1' THEN
2152 
--                                                                                      set(no_Flags) <= '1';
2153 
                                                                                        set(to_USP) <= '1';
2154 
                                                                                        source_lowbits <= '1';
2155 
                                                                                        source_areg <= '1';
2156 
                                                                                        datatype <= "10";
2157 
                                                                                ELSE
2158 
                                                                                        trap_priv <= '1';
2159 
                                                                                        trapmake <= '1';
2160 
                                                                                END IF;
2161 
                                                                        WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" =>         --move USP,An
2162 
                                                                                IF SVmode='1' THEN
2163 
--                                                                                      set(no_Flags) <= '1';
2164 
                                                                                        set(from_USP) <= '1';
2165 
                                                                                        datatype <= "10";
2166 
                                                                                        set_exec(Regwrena) <= '1';
2167 
                                                                                ELSE
2168 
                                                                                        trap_priv <= '1';
2169 
                                                                                        trapmake <= '1';
2170 
                                                                                END IF;
2171 
 
2172 
                                                                        WHEN "1110000" =>                                       --reset
2173 
                                                                                IF SVmode='0' THEN
2174 
                                                                                        trap_priv <= '1';
2175 
                                                                                        trapmake <= '1';
2176 
                                                                                ELSE
2177 
                                                                                        set(opcRESET) <= '1';
2178 
                                                                                        IF decodeOPC='1' THEN
2179 
                                                                                                set(ld_rot_cnt) <= '1';
2180 
                                                                                                set_rot_cnt <= "000000";
2181 
                                                                                        END IF;
2182 
                                                                                END IF;
2183 
 
2184 
                                                                        WHEN "1110001" =>                                       --nop
2185 
 
2186 
                                                                        WHEN "1110010" =>                                       --stop
2187 
                                                                                IF SVmode='0' THEN
2188 
                                                                                        trap_priv <= '1';
2189 
                                                                                        trapmake <= '1';
2190 
                                                                                ELSE
2191 
                                                                                        IF decodeOPC='1' THEN
2192 
                                                                                                setnextpass <= '1';
2193 
                                                                                                set_stop <= '1';
2194 
                                                                                        END IF;
2195 
                                                                                        IF stop='1' THEN
2196 
                                                                                                skipFetch <= '1';
2197 
                                                                                        END IF;
2198 
 
2199 
                                                                                END IF;
2200 
 
2201 
                                                                        WHEN "1110011"|"1110111" =>                                                                     --rte/rtr
2202 
                                                                                IF SVmode='1' OR opcode(2)='1' THEN
2203 
                                                                                        IF decodeOPC='1' THEN
2204 
                                                                                                setstate <= "10";
2205 
                                                                                                set(postadd) <= '1';
2206 
                                                                                                setstackaddr <= '1';
2207 
                                                                                                IF opcode(2)='1' THEN
2208 
                                                                                                        set(directCCR) <= '1';
2209 
                                                                                                ELSE
2210 
                                                                                                        set(directSR) <= '1';
2211 
                                                                                                END IF;
2212 
                                                                                                next_micro_state <= rte1;
2213 
                                                                                        END IF;
2214 
                                                                                ELSE
2215 
                                                                                        trap_priv <= '1';
2216 
                                                                                        trapmake <= '1';
2217 
                                                                                END IF;
2218 
 
2219 
                                                                        WHEN "1110100" =>                                                                       --rtd
2220 
                                                                                datatype <= "10";
2221 
                                                                                IF decodeOPC='1' THEN
2222 
                                                                                        setstate <= "10";
2223 
                                                                                        set(postadd) <= '1';
2224 
                                                                                        setstackaddr <= '1';
2225 
                                                                                        set(direct_delta) <= '1';
2226 
                                                                                        set(directPC) <= '1';
2227 
                                                                                        set_direct_data <= '1';
2228 
                                                                                        next_micro_state <= rtd1;
2229 
                                                                                END IF;
2230 
 
2231 
 
2232 
                                                                        WHEN "1110101" =>                                                                       --rts
2233 
                                                                                datatype <= "10";
2234 
                                                                                IF decodeOPC='1' THEN
2235 
                                                                                        setstate <= "10";
2236 
                                                                                        set(postadd) <= '1';
2237 
                                                                                        setstackaddr <= '1';
2238 
                                                                                        set(direct_delta) <= '1';
2239 
                                                                                        set(directPC) <= '1';
2240 
                                                                                        next_micro_state <= nopnop;
2241 
                                                                                END IF;
2242 
 
2243 
                                                                        WHEN "1110110" =>                                                                       --trapv
2244 
                                                                                IF decodeOPC='1' THEN
2245 
                                                                                        setstate <= "01";
2246 
                                                                                END IF;
2247 
                                                                                IF Flags(1)='1' AND state="01" THEN
2248 
                                                                                        trap_trapv <= '1';
2249 
                                                                                        trapmake <= '1';
2250 
                                                                                END IF;
2251 
 
2252 
                                                                        WHEN "1111010"|"1111011" =>                                                                     --movec
2253 
                                                                                IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
2254 
                                                                                        trap_illegal <= '1';
2255 
                                                                                        trapmake <= '1';
2256 
                                                                                ELSIF SVmode='0' THEN
2257 
                                                                                        trap_priv <= '1';
2258 
                                                                                        trapmake <= '1';
2259 
                                                                                ELSE
2260 
                                                                                        datatype <= "10";       --Long
2261 
                                                                                        IF last_data_read(11 downto 0)=X"800" THEN
2262 
                                                                                                set(from_USP) <= '1';
2263 
                                                                                                IF opcode(0)='1' THEN
2264 
                                                                                                        set(to_USP) <= '1';
2265 
                                                                                                END IF;
2266 
                                                                                        END IF;
2267 
                                                                                        IF opcode(0)='0' THEN
2268 
                                                                                                set_exec(movec_rd) <= '1';
2269 
                                                                                        ELSE
2270 
                                                                                                set_exec(movec_wr) <= '1';
2271 
                                                                                        END IF;
2272 
                                                                                        IF decodeOPC='1' THEN
2273 
                                                                                                next_micro_state <= movec1;
2274 
                                                                                                getbrief <='1';
2275 
                                                                                        END IF;
2276 
                                                                                END IF;
2277 
 
2278 
                                                                        WHEN OTHERS =>
2279 
                                                                                trap_illegal <= '1';
2280 
                                                                                trapmake <= '1';
2281 
                                                                END CASE;
2282 
                                                        END IF;
2283 
                                                WHEN OTHERS => NULL;
2284 
                                        END CASE;
2285 
                                END IF;
2286 
--
2287 
---- 0101 ----------------------------------------------------------------------------
2288 
                        WHEN "0101" =>                                                          --subq, addq
2289 
 
2290 
                                        IF opcode(7 downto 6)="11" THEN --dbcc
2291 
                                                IF opcode(5 downto 3)="001" THEN --dbcc
2292 
                                                        IF decodeOPC='1' THEN
2293 
                                                                next_micro_state <= dbcc1;
2294 
                                                                set(OP2out_one) <= '1';
2295 
                                                                data_is_source <= '1';
2296 
                                                        END IF;
2297 
                                                ELSE                            --Scc
2298 
                                                        datatype <= "00";                       --Byte
2299 
                                                        ea_build_now <= '1';
2300 
                                                        write_back <= '1';
2301 
                                                        set_exec(opcScc) <= '1';
2302 
                                                        IF cpu(0)='1' AND state="10" THEN
2303 
                                                                skipFetch <= '1';
2304 
                                                        END IF;
2305 
                                                        IF opcode(5 downto 4)="00" THEN
2306 
                                                                set_exec(Regwrena) <= '1';
2307 
                                                        END IF;
2308 
                                                END IF;
2309 
                                        ELSE                                    --addq, subq
2310 
                                                ea_build_now <= '1';
2311 
                                                IF opcode(5 downto 3)="001" THEN
2312 
                                                        set(no_Flags) <= '1';
2313 
                                                END IF;
2314 
                                                IF opcode(8)='1' THEN
2315 
                                                        set(addsub) <= '1';
2316 
                                                END IF;
2317 
                                                write_back <= '1';
2318 
                                                set_exec(opcADDQ) <= '1';
2319 
                                                set_exec(opcADD) <= '1';
2320 
                                                set_exec(ea_data_OP1) <= '1';
2321 
                                                IF opcode(5 downto 4)="00" THEN
2322 
                                                        set_exec(Regwrena) <= '1';
2323 
                                                END IF;
2324 
                                        END IF;
2325 
--
2326 
---- 0110 ----------------------------------------------------------------------------
2327 
                        WHEN "0110" =>                          --bra,bsr,bcc
2328 
                                datatype <= "10";
2329 
 
2330 
                                IF micro_state=idle THEN
2331 
                                        IF opcode(11 downto 8)="0001" THEN              --bsr
2332 
                                                set(presub) <= '1';
2333 
                                                setstackaddr <='1';
2334 
                                                IF opcode(7 downto 0)="11111111" THEN
2335 
                                                        next_micro_state <= bsr2;
2336 
                                                        set(longaktion) <= '1';
2337 
                                                ELSIF opcode(7 downto 0)="00000000" THEN
2338 
                                                        next_micro_state <= bsr2;
2339 
                                                ELSE
2340 
                                                        next_micro_state <= bsr1;
2341 
                                                        setstate <= "11";
2342 
                                                        writePC <= '1';
2343 
                                                END IF;
2344 
                                        ELSE                                                                    --bra
2345 
                                                IF opcode(7 downto 0)="11111111" THEN
2346 
                                                        next_micro_state <= bra1;
2347 
                                                        set(longaktion) <= '1';
2348 
                                                ELSIF opcode(7 downto 0)="00000000" THEN
2349 
                                                        next_micro_state <= bra1;
2350 
                                                ELSE
2351 
                                                        setstate <= "01";
2352 
                                                        next_micro_state <= bra1;
2353 
                                                END IF;
2354 
                                        END IF;
2355 
                                END IF;
2356 
 
2357 
-- 0111 ----------------------------------------------------------------------------
2358 
                        WHEN "0111" =>                          --moveq
2359 
--                              IF opcode(8)='0' THEN   -- Cloanto's Amiga Forver ROMs have mangled moveq instructions with a 1 here...
2360 
                                        datatype <= "10";               --Long
2361 
                                        set_exec(Regwrena) <= '1';
2362 
                                        set_exec(opcMOVEQ) <= '1';
2363 
                                        set_exec(opcMOVE) <= '1';
2364 
                                        dest_hbits <= '1';
2365 
--                              ELSE
2366 
--                                      trap_illegal <= '1';
2367 
--                                      trapmake <= '1';
2368 
--                              END IF;
2369 
 
2370 
---- 1000 ----------------------------------------------------------------------------
2371 
                        WHEN "1000" =>                                                          --or
2372 
                                IF opcode(7 downto 6)="11" THEN --divu, divs
2373 
                                        IF DIV_Mode/=3 THEN
2374 
                                                IF opcode(5 downto 4)="00" THEN --Dn, An
2375 
                                                        regdirectsource <= '1';
2376 
                                                END IF;
2377 
                                                IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
2378 
                                                        setstate <="01";
2379 
                                                        next_micro_state <= div1;
2380 
                                                END IF;
2381 
                                                ea_build_now <= '1';
2382 
                                                IF z_error='0' AND set_V_Flag='0' THEN
2383 
                                                        set_exec(Regwrena) <= '1';
2384 
                                                END IF;
2385 
                                                        source_lowbits <='1';
2386 
                                                IF nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
2387 
                                                        dest_hbits <= '1';
2388 
                                                END IF;
2389 
                                                datatype <= "01";
2390 
                                        ELSE
2391 
                                                trap_illegal <= '1';
2392 
                                                trapmake <= '1';
2393 
                                        END IF;
2394 
 
2395 
                                ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN    --sbcd, pack , unpack
2396 
                                        IF opcode(7 downto 6)="00" THEN --sbcd
2397 
                                                build_bcd <= '1';
2398 
                                                set_exec(opcADD) <= '1';
2399 
                                                set_exec(opcSBCD) <= '1';
2400 
                                                set(addsub) <= '1';
2401 
                                        ELSIF opcode(7 downto 6)="01" OR opcode(7 downto 6)="10" THEN   --pack , unpack
2402 
                                                set_exec(ea_data_OP1) <= '1';
2403 
                                                set(no_Flags) <= '1';
2404 
                                                source_lowbits <='1';
2405 
                                                IF opcode(7 downto 6) = "01" THEN       --pack
2406 
                                                        set_exec(opcPACK) <= '1';
2407 
                                                        datatype <= "01";                               --Word
2408 
                                                ELSE                                                            --unpk
2409 
                                                        set_exec(opcUNPACK) <= '1';
2410 
                                                        datatype <= "00";                               --Byte
2411 
                                                END IF;
2412 
                                                IF opcode(3)='0' THEN
2413 
                                                        IF opcode(7 downto 6) = "01" THEN       --pack
2414 
                                                                set_datatype <= "00";           --Byte
2415 
                                                        ELSE                                                            --unpk
2416 
                                                                set_datatype <= "01";           --Word
2417 
                                                        END IF;
2418 
                                                        set_exec(Regwrena) <= '1';
2419 
                                                        dest_hbits <= '1';
2420 
                                                        IF decodeOPC='1' THEN
2421 
                                                                next_micro_state <= nop;
2422 
--                                                              set_direct_data <= '1';
2423 
                                                                set(store_ea_packdata) <= '1';
2424 
                                                                set(store_ea_data) <= '1';
2425 
                                                        END IF;
2426 
                                                ELSE                            -- pack -(Ax),-(Ay)
2427 
                                                        write_back <= '1';
2428 
                                                        IF decodeOPC='1' THEN
2429 
                                                                next_micro_state <= pack1;
2430 
                                                                set_direct_data <= '1';
2431 
                                                        END IF;
2432 
                                                END IF;
2433 
                                        ELSE
2434 
                                                trap_illegal <= '1';
2435 
                                                trapmake <= '1';
2436 
                                        END IF;
2437 
                                ELSE                                                                    --or
2438 
                                        set_exec(opcOR) <= '1';
2439 
                                        build_logical <= '1';
2440 
                                END IF;
2441 
 
2442 
---- 1001, 1101 -----------------------------------------------------------------------
2443 
                        WHEN "1001"|"1101" =>                                           --sub, add
2444 
                                set_exec(opcADD) <= '1';
2445 
                                ea_build_now <= '1';
2446 
                                IF opcode(14)='0' THEN
2447 
                                        set(addsub) <= '1';
2448 
                                END IF;
2449 
                                IF opcode(7 downto 6)="11" THEN --      --adda, suba
2450 
                                        IF opcode(8)='0' THEN    --adda.w, suba.w
2451 
                                                datatype <= "01";       --Word
2452 
                                        END IF;
2453 
                                        set_exec(Regwrena) <= '1';
2454 
                                        source_lowbits <='1';
2455 
                                        IF opcode(3)='1' THEN
2456 
                                                source_areg <= '1';
2457 
                                        END IF;
2458 
                                        set(no_Flags) <= '1';
2459 
                                        IF setexecOPC='1' THEN
2460 
                                                dest_areg <='1';
2461 
                                                dest_hbits <= '1';
2462 
                                        END IF;
2463 
                                ELSE
2464 
                                        IF opcode(8)='1' AND opcode(5 downto 4)="00" THEN               --addx, subx
2465 
                                                build_bcd <= '1';
2466 
                                        ELSE                                                    --sub, add
2467 
                                                build_logical <= '1';
2468 
                                        END IF;
2469 
                                END IF;
2470 
 
2471 
--
2472 
---- 1010 ----------------------------------------------------------------------------
2473 
                        WHEN "1010" =>                                                  --Trap 1010
2474 
                                trap_1010 <= '1';
2475 
                                trapmake <= '1';
2476 
---- 1011 ----------------------------------------------------------------------------
2477 
                        WHEN "1011" =>                                                  --eor, cmp
2478 
                                ea_build_now <= '1';
2479 
                                IF opcode(7 downto 6)="11" THEN --CMPA
2480 
                                        IF opcode(8)='0' THEN    --cmpa.w
2481 
                                                datatype <= "01";       --Word
2482 
                                                set_exec(opcCPMAW) <= '1';
2483 
                                        END IF;
2484 
                                        set_exec(opcCMP) <= '1';
2485 
                                        IF setexecOPC='1' THEN
2486 
                                                source_lowbits <='1';
2487 
                                                IF opcode(3)='1' THEN
2488 
                                                        source_areg <= '1';
2489 
                                                END IF;
2490 
                                                dest_areg <='1';
2491 
                                                dest_hbits <= '1';
2492 
                                        END IF;
2493 
                                        set(addsub) <= '1';
2494 
                                ELSE
2495 
                                        IF opcode(8)='1' THEN
2496 
                                                IF opcode(5 downto 3)="001" THEN                --cmpm
2497 
                                                        set_exec(opcCMP) <= '1';
2498 
                                                        IF decodeOPC='1' THEN
2499 
                                                                IF opcode(2 downto 0)="111" THEN
2500 
                                                                        set(use_SP) <= '1';
2501 
                                                                END IF;
2502 
                                                                setstate <= "10";
2503 
                                                                set(update_ld) <= '1';
2504 
                                                                set(postadd) <= '1';
2505 
                                                                next_micro_state <= cmpm;
2506 
                                                        END IF;
2507 
                                                        set_exec(ea_data_OP1) <= '1';
2508 
                                                        set(addsub) <= '1';
2509 
                                                ELSE                                            --EOR
2510 
                                                        build_logical <= '1';
2511 
                                                        set_exec(opcEOR) <= '1';
2512 
                                                END IF;
2513 
                                        ELSE                                                    --CMP
2514 
                                                build_logical <= '1';
2515 
                                                set_exec(opcCMP) <= '1';
2516 
                                                set(addsub) <= '1';
2517 
                                        END IF;
2518 
                                END IF;
2519 
--
2520 
---- 1100 ----------------------------------------------------------------------------
2521 
                        WHEN "1100" =>                                                          --and, exg
2522 
                                IF opcode(7 downto 6)="11" THEN --mulu, muls
2523 
                                        IF MUL_Mode/=3 THEN
2524 
                                                IF opcode(5 downto 4)="00" THEN --Dn, An
2525 
                                                        regdirectsource <= '1';
2526 
                                                END IF;
2527 
                                                IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
2528 
                                                        IF MUL_Hardware=0 THEN
2529 
                                                                setstate <="01";
2530 
                                                                set(ld_rot_cnt) <= '1';
2531 
                                                                next_micro_state <= mul1;
2532 
                                                        ELSE
2533 
                                                                set_exec(write_lowlong) <= '1';
2534 
                                                                set_exec(opcMULU) <= '1';
2535 
                                                        END IF;
2536 
                                                END IF;
2537 
                                                ea_build_now <= '1';
2538 
                                                set_exec(Regwrena) <= '1';
2539 
                                                source_lowbits <='1';
2540 
                                                IF (nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
2541 
                                                        dest_hbits <= '1';
2542 
                                                END IF;
2543 
                                                datatype <= "01";
2544 
                                                IF setexecOPC='1' THEN
2545 
                                                        datatype <= "10";
2546 
                                                END IF;
2547 
 
2548 
                                        ELSE
2549 
                                                trap_illegal <= '1';
2550 
                                                trapmake <= '1';
2551 
                                        END IF;
2552 
 
2553 
                                ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN    --exg, abcd
2554 
                                        IF opcode(7 downto 6)="00" THEN --abcd
2555 
                                                build_bcd <= '1';
2556 
                                                set_exec(opcADD) <= '1';
2557 
                                                set_exec(opcABCD) <= '1';
2558 
                                        ELSE                                                                    --exg
2559 
                                                datatype <= "10";
2560 
                                                set(Regwrena) <= '1';
2561 
                                                set(exg) <= '1';
2562 
                                                IF opcode(6)='1' AND opcode(3)='1' THEN
2563 
                                                        dest_areg <= '1';
2564 
                                                        source_areg <= '1';
2565 
                                                END IF;
2566 
                                                IF decodeOPC='1' THEN
2567 
                                                        setstate <= "01";
2568 
                                                ELSE
2569 
                                                        dest_hbits <= '1';
2570 
                                                END IF;
2571 
                                        END IF;
2572 
                                ELSE                                                                    --and
2573 
                                        set_exec(opcAND) <= '1';
2574 
                                        build_logical <= '1';
2575 
                                END IF;
2576 
--
2577 
---- 1110 ----------------------------------------------------------------------------
2578 
                        WHEN "1110" =>                                                          --rotation / bitfield
2579 
                                IF opcode(7 downto 6)="11" THEN
2580 
                                        IF opcode(11)='0' THEN
2581 
                                                IF BarrelShifter=0 THEN
2582 
                                                        set_exec(opcROT) <= '1';
2583 
                                                ELSE
2584 
                                                        set_exec(exec_BS) <='1';
2585 
                                                END IF;
2586 
                                                ea_build_now <= '1';
2587 
                                                datatype <= "01";
2588 
                                                set_rot_bits <= opcode(10 downto 9);
2589 
                                                set_exec(ea_data_OP1) <= '1';
2590 
                                                write_back <= '1';
2591 
                                        ELSE            --bitfield
2592 
                                                IF BitField=0 OR (cpu(1)='0' AND BitField=2) THEN
2593 
                                                        trap_illegal <= '1';
2594 
                                                        trapmake <= '1';
2595 
                                                ELSE
2596 
                                                        IF decodeOPC='1' THEN
2597 
                                                                next_micro_state <= nop;
2598 
                                                                set(get_2ndOPC) <= '1';
2599 
                                                                set(ea_build) <= '1';
2600 
                                                        END IF;
2601 
                                                        set_exec(opcBF) <= '1';
2602 
--              000-bftst, 001-bfextu, 010-bfchg, 011-bfexts, 100-bfclr, 101-bfff0, 110-bfset, 111-bfins
2603 
                                                        IF opcode(10)='1' OR opcode(8)='0' THEN
2604 
                                                                set_exec(opcBFwb) <= '1';                       --'1' for tst,chg,clr,ffo,set,ins    --'0' for extu,exts
2605 
                                                        END IF;
2606 
                                                        IF opcode(10 downto 8)="111" THEN       --BFINS
2607 
                                                                set_exec(ea_data_OP1) <= '1';
2608 
                                                        END IF;
2609 
 
2610 
                                                        IF opcode(10 downto 8)="010" OR opcode(10 downto 8)="100" OR opcode(10 downto 8)="110" OR opcode(10 downto 8)="111" THEN
2611 
                                                                write_back <= '1';
2612 
                                                        END IF;
2613 
                                                        ea_only <= '1';
2614 
                                                        IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN
2615 
                                                                set_exec(Regwrena) <= '1';
2616 
                                                        END IF;
2617 
                                                        IF opcode(4 downto 3)="00" THEN
2618 
                                                                IF opcode(10 downto 8)/="000" THEN
2619 
                                                                        set_exec(Regwrena) <= '1';
2620 
                                                                END IF;
2621 
                                                                IF exec(ea_build)='1' THEN
2622 
                                                                        dest_2ndHbits <= '1';
2623 
                                                                        source_2ndLbits <= '1';
2624 
                                                                        set(get_bfoffset) <='1';
2625 
                                                                        setstate <= "01";
2626 
                                                                END IF;
2627 
                                                        END IF;
2628 
                                                        IF set(get_ea_now)='1' THEN
2629 
                                                                setstate <= "01";
2630 
                                                        END IF;
2631 
                                                        IF exec(get_ea_now)='1' THEN
2632 
                                                                dest_2ndHbits <= '1';
2633 
                                                                source_2ndLbits <= '1';
2634 
                                                                set(get_bfoffset) <='1';
2635 
                                                                setstate <= "01";
2636 
                                                                set(mem_addsub) <='1';
2637 
                                                                next_micro_state <= bf1;
2638 
                                                        END IF;
2639 
 
2640 
                                                        IF setexecOPC='1' THEN
2641 
                                                                IF opcode(10 downto 8)="111" THEN       --BFINS
2642 
                                                                        source_2ndHbits <= '1';
2643 
                                                                ELSE
2644 
                                                                        source_lowbits <= '1';
2645 
                                                                END IF;
2646 
                                                                IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN     --BFEXT, BFFFO
2647 
                                                                        dest_2ndHbits <= '1';
2648 
                                                                END IF;
2649 
                                                        END IF;
2650 
                                                END IF;
2651 
                                        END IF;
2652 
                                ELSE
2653 
                                        data_is_source <= '1';
2654 
                                        IF BarrelShifter=0 OR (cpu(1)='0' AND BarrelShifter=2) THEN
2655 
 
2656 
                                                set_exec(opcROT) <= '1';
2657 
                                                set_rot_bits <= opcode(4 downto 3);
2658 
                                                set_exec(Regwrena) <= '1';
2659 
                                                IF decodeOPC='1' THEN
2660 
                                                        IF opcode(5)='1' THEN
2661 
                                                                next_micro_state <= rota1;
2662 
                                                                set(ld_rot_cnt) <= '1';
2663 
                                                                setstate <= "01";
2664 
                                                        ELSE
2665 
                                                                set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
2666 
                                                                IF opcode(11 downto 9)="000" THEN
2667 
                                                                        set_rot_cnt(3) <='1';
2668 
                                                                ELSE
2669 
                                                                        set_rot_cnt(3) <='0';
2670 
                                                                END IF;
2671 
                                                        END IF;
2672 
                                                END IF;
2673 
                                        ELSE
2674 
                                                set_exec(exec_BS) <='1';
2675 
                                                set_rot_bits <= opcode(4 downto 3);
2676 
                                                set_exec(Regwrena) <= '1';
2677 
                                        END IF;
2678 
                                END IF;
2679 
--
2680 
----      ----------------------------------------------------------------------------
2681 
                        WHEN OTHERS =>
2682 
                                trap_1111 <= '1';
2683 
                                trapmake <= '1';
2684 
 
2685 
                END CASE;
2686 
 
2687 
-- use for AND, OR, EOR, CMP
2688 
                IF build_logical='1' THEN
2689 
                        ea_build_now <= '1';
2690 
                        IF set_exec(opcCMP)='0' AND (opcode(8)='0' OR opcode(5 downto 4)="00" ) THEN
2691 
                                set_exec(Regwrena) <= '1';
2692 
                        END IF;
2693 
                        IF opcode(8)='1' THEN
2694 
                                write_back <= '1';
2695 
                                set_exec(ea_data_OP1) <= '1';
2696 
                        ELSE
2697 
                                source_lowbits <='1';
2698 
                                IF opcode(3)='1' THEN           --use for cmp
2699 
                                        source_areg <= '1';
2700 
                                END IF;
2701 
                                IF setexecOPC='1' THEN
2702 
                                        dest_hbits <= '1';
2703 
                                END IF;
2704 
                        END IF;
2705 
                END IF;
2706 
 
2707 
-- use for ABCD, SBCD
2708 
                IF build_bcd='1' THEN
2709 
                        set_exec(use_XZFlag) <= '1';
2710 
                        set_exec(ea_data_OP1) <= '1';
2711 
                        write_back <= '1';
2712 
                        source_lowbits <='1';
2713 
                        IF opcode(3)='1' THEN
2714 
                                IF decodeOPC='1' THEN
2715 
                                        IF opcode(2 downto 0)="111" THEN
2716 
                                                set(use_SP) <= '1';
2717 
                                        END IF;
2718 
                                        setstate <= "10";
2719 
                                        set(update_ld) <= '1';
2720 
                                        set(presub) <= '1';
2721 
                                        next_micro_state <= op_AxAy;
2722 
                                        dest_areg <= '1';                               --???
2723 
                                END IF;
2724 
                        ELSE
2725 
                                dest_hbits <= '1';
2726 
                                set_exec(Regwrena) <= '1';
2727 
                        END IF;
2728 
                END IF;
2729 
 
2730 
 
2731 
------------------------------------------------------------------------------
2732 
------------------------------------------------------------------------------
2733 
                IF set_Z_error='1'  THEN                -- divu by zero
2734 
                        trapmake <= '1';                        --wichtig for USP
2735 
                        IF trapd='0' THEN
2736 
                                writePC <= '1';
2737 
                        END IF;
2738 
                END IF;
2739 
 
2740 
-----------------------------------------------------------------------------
2741 
-- execute microcode
2742 
-----------------------------------------------------------------------------
2743 
                IF rising_edge(clk) THEN
2744 
                IF Reset='1' THEN
2745 
                                micro_state <= ld_nn;
2746 
                        ELSIF clkena_lw='1' THEN
2747 
                                trapd <= trapmake;
2748 
                                micro_state <= next_micro_state;
2749 
                        END IF;
2750 
                END IF;
2751 
 
2752 
                        CASE micro_state IS
2753 
                                WHEN ld_nn =>           -- (nnnn).w/l=>
2754 
                                        set(get_ea_now) <='1';
2755 
                                        setnextpass <= '1';
2756 
                                        set(addrlong) <= '1';
2757 
 
2758 
                                WHEN st_nn =>           -- =>(nnnn).w/l
2759 
                                        setstate <= "11";
2760 
                                        set(addrlong) <= '1';
2761 
                                        next_micro_state <= nop;
2762 
 
2763 
                                WHEN ld_dAn1 =>         -- d(An)=>, --d(PC)=>
2764 
                                        set(get_ea_now) <='1';
2765 
                                        setdisp <= '1';         --word
2766 
                                        setnextpass <= '1';
2767 
 
2768 
                                WHEN ld_AnXn1 =>                -- d(An,Xn)=>, --d(PC,Xn)=>
2769 
                                        IF brief(8)='0' OR extAddr_Mode=0 OR (cpu(1)='0' AND extAddr_Mode=2) THEN
2770 
                                                setdisp <= '1';         --byte
2771 
                                                setdispbyte <= '1';
2772 
                                                setstate <= "01";
2773 
                                                set(briefext) <= '1';
2774 
                                                next_micro_state <= ld_AnXn2;
2775 
                                        ELSE
2776 
                                                IF brief(7)='1'THEN             --suppress Base
2777 
                                                        set_suppress_base <= '1';
2778 
                                                ELSIF exec(dispouter)='1' THEN
2779 
                                                        set(dispouter) <= '1';
2780 
                                                END IF;
2781 
                                                IF brief(5)='0' THEN --NULL Base Displacement
2782 
                                                        setstate <= "01";
2783 
                                                ELSE  --WORD Base Displacement
2784 
                                                        IF brief(4)='1' THEN
2785 
                                                                set(longaktion) <= '1'; --LONG Base Displacement
2786 
                                                        END IF;
2787 
                                                END IF;
2788 
                                                next_micro_state <= ld_229_1;
2789 
                                        END IF;
2790 
 
2791 
                                WHEN ld_AnXn2 =>
2792 
                                        set(get_ea_now) <='1';
2793 
                                        setdisp <= '1';         --brief
2794 
                                        setnextpass <= '1';
2795 
 
2796 
-------------------------------------------------------------------------------------
2797 
 
2798 
                                WHEN ld_229_1 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
2799 
                                        IF brief(5)='1' THEN    --Base Displacement
2800 
                                                setdisp <= '1';         --add last_data_read
2801 
                                        END IF;
2802 
                                        IF brief(6)='0' AND brief(2)='0' THEN --Preindex or Index
2803 
                                                set(briefext) <= '1';
2804 
                                                setstate <= "01";
2805 
                                                IF brief(1 downto 0)="00" THEN
2806 
                                                        next_micro_state <= ld_AnXn2;
2807 
                                                ELSE
2808 
                                                        next_micro_state <= ld_229_2;
2809 
                                                END IF;
2810 
                                        ELSE
2811 
                                                IF brief(1 downto 0)="00" THEN
2812 
                                                        set(get_ea_now) <='1';
2813 
                                                        setnextpass <= '1';
2814 
                                                ELSE
2815 
                                                        setstate <= "10";
2816 
                                                        set(longaktion) <= '1';
2817 
                                                        next_micro_state <= ld_229_3;
2818 
                                                END IF;
2819 
                                        END IF;
2820 
 
2821 
                                WHEN ld_229_2 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
2822 
                                        setdisp <= '1';         -- add Index
2823 
                                        setstate <= "10";
2824 
                                        set(longaktion) <= '1';
2825 
                                        next_micro_state <= ld_229_3;
2826 
 
2827 
                                WHEN ld_229_3 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
2828 
                                        set_suppress_base <= '1';
2829 
                                        set(dispouter) <= '1';
2830 
                                        IF brief(1)='0' THEN --NULL Outer Displacement
2831 
                                                setstate <= "01";
2832 
                                        ELSE  --WORD Outer Displacement
2833 
                                                IF brief(0)='1' THEN
2834 
                                                        set(longaktion) <= '1'; --LONG Outer Displacement
2835 
                                                END IF;
2836 
                                        END IF;
2837 
                                        next_micro_state <= ld_229_4;
2838 
 
2839 
                                WHEN ld_229_4 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
2840 
                                        IF brief(1)='1' THEN  -- Outer Displacement
2841 
                                                setdisp <= '1';   --add last_data_read
2842 
                                        END IF;
2843 
                                        IF brief(6)='0' AND brief(2)='1' THEN --Postindex
2844 
                                                set(briefext) <= '1';
2845 
                                                setstate <= "01";
2846 
                                                next_micro_state <= ld_AnXn2;
2847 
                                        ELSE
2848 
                                                set(get_ea_now) <='1';
2849 
                                                setnextpass <= '1';
2850 
                                        END IF;
2851 
 
2852 
----------------------------------------------------------------------------------------
2853 
                                WHEN st_dAn1 =>         -- =>d(An)
2854 
                                        setstate <= "11";
2855 
                                        setdisp <= '1';         --word
2856 
                                        next_micro_state <= nop;
2857 
 
2858 
                                WHEN st_AnXn1 =>                -- =>d(An,Xn)
2859 
                                        IF brief(8)='0' OR extAddr_Mode=0 OR (cpu(1)='0' AND extAddr_Mode=2) THEN
2860 
                                                setdisp <= '1';         --byte
2861 
                                                setdispbyte <= '1';
2862 
                                                setstate <= "01";
2863 
                                                set(briefext) <= '1';
2864 
                                                next_micro_state <= st_AnXn2;
2865 
                                        ELSE
2866 
                                                IF brief(7)='1'THEN             --suppress Base
2867 
                                                        set_suppress_base <= '1';
2868 
--                                              ELSIF exec(dispouter)='1' THEN
2869 
--                                                      set(dispouter) <= '1';
2870 
                                                END IF;
2871 
                                                IF brief(5)='0' THEN --NULL Base Displacement
2872 
                                                        setstate <= "01";
2873 
                                                ELSE  --WORD Base Displacement
2874 
                                                        IF brief(4)='1' THEN
2875 
                                                                set(longaktion) <= '1'; --LONG Base Displacement
2876 
                                                        END IF;
2877 
                                                END IF;
2878 
                                                next_micro_state <= st_229_1;
2879 
                                        END IF;
2880 
 
2881 
                                WHEN st_AnXn2 =>
2882 
                                        setstate <= "11";
2883 
                                        setdisp <= '1';         --brief
2884 
                                        next_micro_state <= nop;
2885 
 
2886 
-------------------------------------------------------------------------------------
2887 
 
2888 
                                WHEN st_229_1 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
2889 
                                        IF brief(5)='1' THEN    --Base Displacement
2890 
                                                setdisp <= '1';         --add last_data_read
2891 
                                        END IF;
2892 
                                        IF brief(6)='0' AND brief(2)='0' THEN --Preindex or Index
2893 
                                                set(briefext) <= '1';
2894 
                                                setstate <= "01";
2895 
                                                IF brief(1 downto 0)="00" THEN
2896 
                                                        next_micro_state <= st_AnXn2;
2897 
                                                ELSE
2898 
                                                        next_micro_state <= st_229_2;
2899 
                                                END IF;
2900 
                                        ELSE
2901 
                                                IF brief(1 downto 0)="00" THEN
2902 
                                                        setstate <= "11";
2903 
                                                        next_micro_state <= nop;
2904 
                                                ELSE
2905 
                                                        set(hold_dwr) <= '1';
2906 
                                                        setstate <= "10";
2907 
                                                        set(longaktion) <= '1';
2908 
                                                        next_micro_state <= st_229_3;
2909 
                                                END IF;
2910 
                                        END IF;
2911 
 
2912 
                                WHEN st_229_2 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
2913 
                                        setdisp <= '1';         -- add Index
2914 
                                        set(hold_dwr) <= '1';
2915 
                                        setstate <= "10";
2916 
                                        set(longaktion) <= '1';
2917 
                                        next_micro_state <= st_229_3;
2918 
 
2919 
                                WHEN st_229_3 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
2920 
                                        set(hold_dwr) <= '1';
2921 
                                        set_suppress_base <= '1';
2922 
                                        set(dispouter) <= '1';
2923 
                                        IF brief(1)='0' THEN --NULL Outer Displacement
2924 
                                                setstate <= "01";
2925 
                                        ELSE  --WORD Outer Displacement
2926 
                                                IF brief(0)='1' THEN
2927 
                                                        set(longaktion) <= '1'; --LONG Outer Displacement
2928 
                                                END IF;
2929 
                                        END IF;
2930 
                                        next_micro_state <= st_229_4;
2931 
 
2932 
                                WHEN st_229_4 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
2933 
                                        set(hold_dwr) <= '1';
2934 
                                        IF brief(1)='1' THEN  -- Outer Displacement
2935 
                                                setdisp <= '1';   --add last_data_read
2936 
                                        END IF;
2937 
                                        IF brief(6)='0' AND brief(2)='1' THEN --Postindex
2938 
                                                set(briefext) <= '1';
2939 
                                                setstate <= "01";
2940 
                                                next_micro_state <= st_AnXn2;
2941 
                                        ELSE
2942 
                                                setstate <= "11";
2943 
                                                next_micro_state <= nop;
2944 
                                        END IF;
2945 
 
2946 
----------------------------------------------------------------------------------------
2947 
                                WHEN bra1 =>            --bra
2948 
                                        IF exe_condition='1' THEN
2949 
                                                TG68_PC_brw <= '1';     --pc+0000
2950 
                                                next_micro_state <= nop;
2951 
                                                skipFetch <= '1';
2952 
                                        END IF;
2953 
 
2954 
                                WHEN bsr1 =>            --bsr short
2955 
                                        TG68_PC_brw <= '1';
2956 
                                        next_micro_state <= nop;
2957 
 
2958 
                                WHEN bsr2 =>            --bsr
2959 
                                        IF long_start='0' THEN
2960 
                                                TG68_PC_brw <= '1';
2961 
                                        END IF;
2962 
                                        skipFetch <= '1';
2963 
                                        set(longaktion) <= '1';
2964 
                                        writePC <= '1';
2965 
                                        setstate <= "11";
2966 
                                        next_micro_state <= nopnop;
2967 
                                        setstackaddr <='1';
2968 
                                WHEN nopnop =>          --bsr
2969 
                                        next_micro_state <= nop;
2970 
 
2971 
                                WHEN dbcc1 =>           --dbcc
2972 
                                        IF exe_condition='0' THEN
2973 
                                                Regwrena_now <= '1';
2974 
                                                IF c_out(1)='1' THEN
2975 
                                                        skipFetch <= '1';
2976 
                                                        next_micro_state <= nop;
2977 
                                                        TG68_PC_brw <= '1';
2978 
                                                END IF;
2979 
                                        END IF;
2980 
 
2981 
                                WHEN movem1 =>          --movem
2982 
                                        IF last_data_read(15 downto 0)/=X"0000" THEN
2983 
                                                setstate <="01";
2984 
                                                IF opcode(5 downto 3)="100" THEN
2985 
                                                        set(mem_addsub) <= '1';
2986 
                                                END IF;
2987 
                                                next_micro_state <= movem2;
2988 
                                        END IF;
2989 
                                WHEN movem2 =>          --movem
2990 
                                        IF movem_run='0' THEN
2991 
                                                setstate <="01";
2992 
                                        ELSE
2993 
                                                set(movem_action) <= '1';
2994 
                                                set(mem_addsub) <= '1';
2995 
                                                next_micro_state <= movem2;
2996 
                                                IF opcode(10)='0' THEN
2997 
                                                        setstate <="11";
2998 
                                                        set(write_reg) <= '1';
2999 
                                                ELSE
3000 
                                                        setstate <="10";
3001 
                                                END IF;
3002 
                                        END IF;
3003 
 
3004 
                                WHEN andi =>            --andi
3005 
                                        IF opcode(5 downto 4)/="00" THEN
3006 
                                                setnextpass <= '1';
3007 
                                        END IF;
3008 
 
3009 
                                WHEN pack1 =>           -- pack -(Ax),-(Ay)
3010 
                                        set(hold_ea_data) <= '1';
3011 
                                        set(update_ld) <= '1';
3012 
                                        setstate <= "10";
3013 
                                        set(presub) <= '1';
3014 
                                        next_micro_state <= pack2;
3015 
                                        dest_areg <= '1';
3016 
                                WHEN pack2 =>
3017 
                                        set(hold_ea_data) <= '1';
3018 
                                        set_direct_data <= '1';
3019 
                                        IF opcode(7 downto 6) = "01" THEN       --pack
3020 
                                                datatype <= "00";               --Byte
3021 
                                        ELSE                                                            --unpk
3022 
                                                datatype <= "01";               --Word
3023 
                                        END IF;
3024 
                                        set(presub) <= '1';
3025 
                                        dest_hbits <= '1';
3026 
                                        dest_areg <= '1';
3027 
                                        setstate <= "10";
3028 
                                        next_micro_state <= pack3;
3029 
                                WHEN pack3 =>
3030 
                                        skipFetch <= '1';
3031 
 
3032 
                                WHEN op_AxAy =>         -- op -(Ax),-(Ay)
3033 
                                        IF opcode(11 downto 9)="111" THEN
3034 
                                                set(use_SP) <= '1';
3035 
                                        END IF;
3036 
                                        set_direct_data <= '1';
3037 
                                        set(presub) <= '1';
3038 
                                        dest_hbits <= '1';
3039 
                                        dest_areg <= '1';
3040 
                                        setstate <= "10";
3041 
 
3042 
                                WHEN cmpm =>            -- cmpm (Ay)+,(Ax)+
3043 
                                        IF opcode(11 downto 9)="111" THEN
3044 
                                                set(use_SP) <= '1';
3045 
                                        END IF;
3046 
                                        set_direct_data <= '1';
3047 
                                        set(postadd) <= '1';
3048 
                                        dest_hbits <= '1';
3049 
                                        dest_areg <= '1';
3050 
                                        setstate <= "10";
3051 
 
3052 
                                WHEN link1 =>           -- link
3053 
                                        setstate <="11";
3054 
                                        source_areg <= '1';
3055 
                                        set(opcMOVE) <= '1';
3056 
                                        set(Regwrena) <= '1';
3057 
                                        next_micro_state <= link2;
3058 
                                WHEN link2 =>           -- link
3059 
                                        setstackaddr <='1';
3060 
                                        set(ea_data_OP2) <= '1';
3061 
 
3062 
                                WHEN unlink1 =>         -- unlink
3063 
                                        setstate <="10";
3064 
                                        setstackaddr <='1';
3065 
                                        set(postadd) <= '1';
3066 
                                        next_micro_state <= unlink2;
3067 
                                WHEN unlink2 =>         -- unlink
3068 
                                        set(ea_data_OP2) <= '1';
3069 
 
3070 
                                WHEN trap0 =>           -- TRAP
3071 
                                        set(presub) <= '1';
3072 
                                        setstackaddr <='1';
3073 
                                        setstate <= "11";
3074 
                                        IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN    --68010
3075 
                                                set(writePC_add) <= '1';
3076 
                                                datatype <= "01";
3077 
--                                              set_datatype <= "10";
3078 
                                                next_micro_state <= trap1;
3079 
                                        ELSE
3080 
                                                IF trap_interrupt='1' OR trap_trace='1' OR trap_berr='1' THEN
3081 
                                                        writePC <= '1';
3082 
                                                END IF;
3083 
                                                datatype <= "10";
3084 
                                                next_micro_state <= trap2;
3085 
                                        END IF;
3086 
                                WHEN trap1 =>           -- TRAP
3087 
                                        IF trap_interrupt='1' OR trap_trace='1' THEN
3088 
                                                writePC <= '1';
3089 
                                        END IF;
3090 
                                        set(presub) <= '1';
3091 
                                        setstackaddr <='1';
3092 
                                        setstate <= "11";
3093 
                                        datatype <= "10";
3094 
                                        next_micro_state <= trap2;
3095 
                                WHEN trap2 =>           -- TRAP
3096 
                                        set(presub) <= '1';
3097 
                                        setstackaddr <='1';
3098 
                                        setstate <= "11";
3099 
                                        datatype <= "01";
3100 
                                        writeSR <= '1';
3101 
                                        IF trap_berr='1' THEN
3102 
                                                next_micro_state <= trap4;
3103 
                                        ELSE
3104 
                                                next_micro_state <= trap3;
3105 
                                        END IF;
3106 
                                WHEN trap3 =>           -- TRAP
3107 
                                        set_vectoraddr <= '1';
3108 
                                        datatype <= "10";
3109 
                                        set(direct_delta) <= '1';
3110 
                                        set(directPC) <= '1';
3111 
                                        setstate <= "10";
3112 
                                        next_micro_state <= nopnop;
3113 
 
3114 
                                WHEN trap4 =>           -- TRAP
3115 
                                        set(presub) <= '1';
3116 
                                        setstackaddr <='1';
3117 
                                        setstate <= "11";
3118 
                                        datatype <= "01";
3119 
                                        writeSR <= '1';
3120 
                                        next_micro_state <= trap5;
3121 
                                WHEN trap5 =>           -- TRAP
3122 
                                        set(presub) <= '1';
3123 
                                        setstackaddr <='1';
3124 
                                        setstate <= "11";
3125 
                                        datatype <= "10";
3126 
                                        writeSR <= '1';
3127 
                                        next_micro_state <= trap6;
3128 
                                WHEN trap6 =>           -- TRAP
3129 
                                        set(presub) <= '1';
3130 
                                        setstackaddr <='1';
3131 
                                        setstate <= "11";
3132 
                                        datatype <= "01";
3133 
                                        writeSR <= '1';
3134 
                                        next_micro_state <= trap3;
3135 
 
3136 
                                WHEN rte1 =>            -- RTE
3137 
                                        datatype <= "10";
3138 
                                        setstate <= "10";
3139 
                                        set(postadd) <= '1';
3140 
                                        setstackaddr <= '1';
3141 
                                        IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
3142 
                                                set(update_FC) <= '1';
3143 
                                                set(direct_delta) <= '1';
3144 
                                        END IF;
3145 
                                        set(directPC) <= '1';
3146 
                                        next_micro_state <= rte2;
3147 
                                WHEN rte2 =>            -- RTE
3148 
                                        datatype <= "01";
3149 
                                        set(update_FC) <= '1';
3150 
                                        IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN
3151 
                                                setstate <= "10";
3152 
                                                set(postadd) <= '1';
3153 
                                                setstackaddr <= '1';
3154 
                                                next_micro_state <= rte3;
3155 
                                        ELSE
3156 
                                                next_micro_state <= nop;
3157 
                                        END IF;
3158 
                                WHEN rte3 =>            -- RTE
3159 
                                        next_micro_state <= nop;
3160 
--                                      set(update_FC) <= '1';
3161 
 
3162 
 
3163 
                                WHEN rtd1 =>            -- RTD
3164 
                                        next_micro_state <= rtd2;
3165 
                                WHEN rtd2 =>            -- RTD
3166 
                                        setstackaddr <= '1';
3167 
                                        set(Regwrena) <= '1';
3168 
 
3169 
                                WHEN movec1 =>          -- MOVEC
3170 
                                        set(briefext) <= '1';
3171 
                                        set_writePCbig <='1';
3172 
                                        IF (brief(11 downto 0)=X"000" OR brief(11 downto 0)=X"001" OR brief(11 downto 0)=X"800" OR brief(11 downto 0)=X"801") OR
3173 
                                           (cpu(1)='1' AND (brief(11 downto 0)=X"002" OR brief(11 downto 0)=X"802" OR brief(11 downto 0)=X"803" OR brief(11 downto 0)=X"804")) THEN
3174 
                                                IF opcode(0)='0' THEN
3175 
                                                        set(Regwrena) <= '1';
3176 
                                                END IF;
3177 
--                                      ELSIF brief(11 downto 0)=X"800"OR brief(11 downto 0)=X"001" OR brief(11 downto 0)=X"000" THEN
3178 
--                                              trap_addr_error <= '1';
3179 
--                                              trapmake <= '1';
3180 
                                        ELSE
3181 
                                                trap_illegal <= '1';
3182 
                                                trapmake <= '1';
3183 
                                        END IF;
3184 
 
3185 
                                WHEN movep1 =>          -- MOVEP d(An)
3186 
                                        setdisp <= '1';
3187 
                                        set(mem_addsub) <= '1';
3188 
                                        set(mem_byte) <= '1';
3189 
                                        set(OP1addr) <= '1';
3190 
                                        IF opcode(6)='1' THEN
3191 
                                                set(movepl) <= '1';
3192 
                                        END IF;
3193 
                                        IF opcode(7)='0' THEN
3194 
                                                setstate <= "10";
3195 
                                        ELSE
3196 
                                                setstate <= "11";
3197 
                                        END IF;
3198 
                                        next_micro_state <= movep2;
3199 
                                WHEN movep2 =>
3200 
                                        IF opcode(6)='1' THEN
3201 
                                                set(mem_addsub) <= '1';
3202 
                                            set(OP1addr) <= '1';
3203 
                                        END IF;
3204 
                                        IF opcode(7)='0' THEN
3205 
                                                setstate <= "10";
3206 
                                        ELSE
3207 
                                                setstate <= "11";
3208 
                                        END IF;
3209 
                                        next_micro_state <= movep3;
3210 
                                WHEN movep3 =>
3211 
                                        IF opcode(6)='1' THEN
3212 
                                                set(mem_addsub) <= '1';
3213 
                                            set(OP1addr) <= '1';
3214 
                                                set(mem_byte) <= '1';
3215 
                                                IF opcode(7)='0' THEN
3216 
                                                        setstate <= "10";
3217 
                                                ELSE
3218 
                                                        setstate <= "11";
3219 
                                                END IF;
3220 
                                                next_micro_state <= movep4;
3221 
                                        ELSE
3222 
                                                datatype <= "01";               --Word
3223 
                                        END IF;
3224 
                                WHEN movep4 =>
3225 
                                        IF opcode(7)='0' THEN
3226 
                                                setstate <= "10";
3227 
                                        ELSE
3228 
                                                setstate <= "11";
3229 
                                        END IF;
3230 
                                        next_micro_state <= movep5;
3231 
                                WHEN movep5 =>
3232 
                                        datatype <= "10";               --Long
3233 
 
3234 
                                WHEN mul1       =>              -- mulu
3235 
                                        IF opcode(15)='1' OR MUL_Mode=0 THEN
3236 
                                                set_rot_cnt <= "001110";
3237 
                                        ELSE
3238 
                                                set_rot_cnt <= "011110";
3239 
                                        END IF;
3240 
                                        setstate <="01";
3241 
                                        next_micro_state <= mul2;
3242 
                                WHEN mul2       =>              -- mulu
3243 
                                        setstate <="01";
3244 
                                        IF rot_cnt="00001" THEN
3245 
                                                next_micro_state <= mul_end1;
3246 
                                        ELSE
3247 
                                                next_micro_state <= mul2;
3248 
                                        END IF;
3249 
                                WHEN mul_end1   =>              -- mulu
3250 
                                        datatype <= "10";
3251 
                                        set(opcMULU) <= '1';
3252 
                                        IF opcode(15)='0' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
3253 
                                                dest_2ndHbits <= '1';
3254 
--                                              source_2ndLbits <= '1';--???
3255 
                                                set(write_lowlong) <= '1';
3256 
                                                IF sndOPC(10)='1' THEN
3257 
                                                        setstate <="01";
3258 
                                                        next_micro_state <= mul_end2;
3259 
                                                END IF;
3260 
                                                set(Regwrena) <= '1';
3261 
                                        END IF;
3262 
                                        datatype <= "10";
3263 
                                WHEN mul_end2   =>              -- divu
3264 
                                        set(write_reminder) <= '1';
3265 
                                        set(Regwrena) <= '1';
3266 
                                        set(opcMULU) <= '1';
3267 
 
3268 
                                WHEN div1       =>              -- divu
3269 
                                        setstate <="01";
3270 
                                        next_micro_state <= div2;
3271 
                                WHEN div2       =>              -- divu
3272 
                                        IF (OP2out(31 downto 16)=x"0000" OR opcode(15)='1' OR DIV_Mode=0) AND OP2out(15 downto 0)=x"0000" THEN            --div zero
3273 
                                                set_Z_error <= '1';
3274 
                                        ELSE
3275 
                                                next_micro_state <= div3;
3276 
                                        END IF;
3277 
                                        set(ld_rot_cnt) <= '1';
3278 
                                        setstate <="01";
3279 
                                WHEN div3       =>              -- divu
3280 
                                        IF opcode(15)='1' OR DIV_Mode=0 THEN
3281 
                                                set_rot_cnt <= "001101";
3282 
                                        ELSE
3283 
                                                set_rot_cnt <= "011101";
3284 
                                        END IF;
3285 
                                        setstate <="01";
3286 
                                        next_micro_state <= div4;
3287 
                                WHEN div4       =>              -- divu
3288 
                                        setstate <="01";
3289 
                                        IF rot_cnt="00001" THEN
3290 
                                                next_micro_state <= div_end1;
3291 
                                        ELSE
3292 
                                                next_micro_state <= div4;
3293 
                                        END IF;
3294 
                                WHEN div_end1   =>              -- divu
3295 
                                        IF opcode(15)='0' AND (DIV_Mode=1 OR DIV_Mode=2) THEN
3296 
                                                set(write_reminder) <= '1';
3297 
                                                next_micro_state <= div_end2;
3298 
                                                setstate <="01";
3299 
                                        END IF;
3300 
                                        set(opcDIVU) <= '1';
3301 
                                        datatype <= "10";
3302 
                                WHEN div_end2   =>              -- divu
3303 
                                        dest_2ndHbits <= '1';
3304 
                                        source_2ndLbits <= '1';--???
3305 
                                        set(opcDIVU) <= '1';
3306 
 
3307 
                                WHEN rota1      =>
3308 
                                        IF OP2out(5 downto 0)/="000000" THEN
3309 
                                                set_rot_cnt <= OP2out(5 downto 0);
3310 
                                        ELSE
3311 
                                                set_exec(rot_nop) <= '1';
3312 
                                        END IF;
3313 
 
3314 
                                WHEN bf1 =>
3315 
                                        setstate <="10";
3316 
 
3317 
                                WHEN OTHERS => NULL;
3318 
                        END CASE;
3319 
        END PROCESS;
3320 
 
3321 
-----------------------------------------------------------------------------
3322 
-- MOVEC
3323 
-----------------------------------------------------------------------------
3324 
  process (clk, VBR, CACR, brief)
3325 
  begin
3326 
        -- all other hexa codes should give illegal isntruction exception
3327 
        if rising_edge(clk) then
3328 
          if Reset = '1' then
3329 
                VBR <= (others => '0');
3330 
                CACR <= (others => '0');
3331 
          elsif clkena_lw = '1' and exec(movec_wr) = '1' then
3332 
                case brief(11 downto 0) is
3333 
                  when X"000" => NULL; -- SFC -- 68010+
3334 
                  when X"001" => NULL; -- DFC -- 68010+
3335 
                  when X"002" => CACR <= reg_QA(3 downto 0); -- 68020+
3336 
                  when X"800" => NULL; -- USP -- 68010+
3337 
                  when X"801" => VBR <= reg_QA; -- 68010+
3338 
                  when X"802" => NULL; -- CAAR -- 68020+
3339 
                  when X"803" => NULL; -- MSP -- 68020+
3340 
                  when X"804" => NULL; -- isP -- 68020+
3341 
                  when others => NULL;
3342 
                end case;
3343 
          end if;
3344 
        end if;
3345 
 
3346 
        movec_data <= (others => '0');
3347 
        case brief(11 downto 0) is
3348 
          when X"002" => movec_data <= "0000000000000000000000000000" & (CACR AND "0011");
3349 
 
3350 
          when X"801" => --if VBR_Stackframe=1 or (cpu(0)='1' and VBR_Stackframe=2) then
3351 
                movec_data <= VBR;
3352 
                --end if;
3353 
          when others => NULL;
3354 
        end case;
3355 
  end process;
3356 
 
3357 
  CACR_out <= CACR;
3358 
  VBR_out <= VBR;
3359 
-----------------------------------------------------------------------------
3360 
-- Conditions
3361 
-----------------------------------------------------------------------------
3362 
PROCESS (exe_opcode, Flags)
3363 
        BEGIN
3364 
                CASE exe_opcode(11 downto 8) IS
3365 
                        WHEN X"0" => exe_condition <= '1';
3366 
                        WHEN X"1" => exe_condition <= '0';
3367 
                        WHEN X"2" => exe_condition <=  NOT Flags(0) AND NOT Flags(2);
3368 
                        WHEN X"3" => exe_condition <= Flags(0) OR Flags(2);
3369 
                        WHEN X"4" => exe_condition <= NOT Flags(0);
3370 
                        WHEN X"5" => exe_condition <= Flags(0);
3371 
                        WHEN X"6" => exe_condition <= NOT Flags(2);
3372 
                        WHEN X"7" => exe_condition <= Flags(2);
3373 
                        WHEN X"8" => exe_condition <= NOT Flags(1);
3374 
                        WHEN X"9" => exe_condition <= Flags(1);
3375 
                        WHEN X"a" => exe_condition <= NOT Flags(3);
3376 
                        WHEN X"b" => exe_condition <= Flags(3);
3377 
                        WHEN X"c" => exe_condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
3378 
                        WHEN X"d" => exe_condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
3379 
                        WHEN X"e" => exe_condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
3380 
                        WHEN X"f" => exe_condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
3381 
                        WHEN OTHERS => NULL;
3382 
                END CASE;
3383 
        END PROCESS;
3384 
 
3385 
-----------------------------------------------------------------------------
3386 
-- Movem
3387 
-----------------------------------------------------------------------------
3388 
PROCESS (clk)
3389 
        BEGIN
3390 
                IF rising_edge(clk) THEN
3391 
                        IF clkena_lw='1' THEN
3392 
                                movem_actiond <= exec(movem_action);
3393 
                                IF decodeOPC='1' THEN
3394 
                                        sndOPC <= data_read(15 downto 0);
3395 
                                ELSIF exec(movem_action)='1' OR set(movem_action) ='1' THEN
3396 
                                        CASE movem_regaddr IS
3397 
                                                WHEN "0000" => sndOPC(0)  <= '0';
3398 
                                                WHEN "0001" => sndOPC(1)  <= '0';
3399 
                                                WHEN "0010" => sndOPC(2)  <= '0';
3400 
                                                WHEN "0011" => sndOPC(3)  <= '0';
3401 
                                                WHEN "0100" => sndOPC(4)  <= '0';
3402 
                                                WHEN "0101" => sndOPC(5)  <= '0';
3403 
                                                WHEN "0110" => sndOPC(6)  <= '0';
3404 
                                                WHEN "0111" => sndOPC(7)  <= '0';
3405 
                                                WHEN "1000" => sndOPC(8)  <= '0';
3406 
                                                WHEN "1001" => sndOPC(9)  <= '0';
3407 
                                                WHEN "1010" => sndOPC(10) <= '0';
3408 
                                                WHEN "1011" => sndOPC(11) <= '0';
3409 
                                                WHEN "1100" => sndOPC(12) <= '0';
3410 
                                                WHEN "1101" => sndOPC(13) <= '0';
3411 
                                                WHEN "1110" => sndOPC(14) <= '0';
3412 
                                                WHEN "1111" => sndOPC(15) <= '0';
3413 
                                                WHEN OTHERS => NULL;
3414 
                                        END CASE;
3415 
                                END IF;
3416 
                        END IF;
3417 
                END IF;
3418 
        END PROCESS;
3419 
 
3420 
PROCESS (sndOPC, movem_mux)
3421 
        BEGIN
3422 
                movem_regaddr <="0000";
3423 
                movem_run <= '1';
3424 
                IF sndOPC(3 downto 0)="0000" THEN
3425 
                        IF sndOPC(7 downto 4)="0000" THEN
3426 
                                movem_regaddr(3) <= '1';
3427 
                                IF sndOPC(11 downto 8)="0000" THEN
3428 
                                        IF sndOPC(15 downto 12)="0000" THEN
3429 
                                                movem_run <= '0';
3430 
                                        END IF;
3431 
                                        movem_regaddr(2) <= '1';
3432 
                                        movem_mux <= sndOPC(15 downto 12);
3433 
                                ELSE
3434 
                                        movem_mux <= sndOPC(11 downto 8);
3435 
                                END IF;
3436 
                        ELSE
3437 
                                movem_mux <= sndOPC(7 downto 4);
3438 
                                movem_regaddr(2) <= '1';
3439 
                        END IF;
3440 
                ELSE
3441 
                        movem_mux <= sndOPC(3 downto 0);
3442 
                END IF;
3443 
                IF movem_mux(1 downto 0)="00" THEN
3444 
                        movem_regaddr(1) <= '1';
3445 
                        IF movem_mux(2)='0' THEN
3446 
                                movem_regaddr(0) <= '1';
3447 
                        END IF;
3448 
                ELSE
3449 
                        IF movem_mux(0)='0' THEN
3450 
                                movem_regaddr(0) <= '1';
3451 
                        END IF;
3452 
                END  IF;
3453 
        END PROCESS;
3454 
END;

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