Subversion Repositories tg68kc

------------------------------------------------------------------------------

------------------------------------------------------------------------------

--                                                                          --

-- Copyright (c) 2009-2019 Tobias Gubener                                   -- 

-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ...                          --

-- Subdesign fAMpIGA by TobiFlex                                            --

--                                                                          --

-- This source file is free software: you can redistribute it and/or modify --

-- it under the terms of the GNU Lesser General Public License as published --

-- by the Free Software Foundation, either version 3 of the License, or     --

-- (at your option) any later version.                                      --

--                                                                          --

-- This source file is distributed in the hope that it will be useful,      --

-- but WITHOUT ANY WARRANTY; without even the implied warranty of           --

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --

-- GNU General Public License for more details.                             --

--                                                                          --

-- You should have received a copy of the GNU General Public License        --

-- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --

--                                                                          --

------------------------------------------------------------------------------

------------------------------------------------------------------------------

-- 30.10.2019 TG bugfix RTR in 68020-mode

-- 30.10.2019 TG bugfix BFINS again

-- 19.10.2019 TG insert some bugfixes from apolkosnik

-- 05.12.2018 TG insert RTD opcode

-- 03.12.2018 TG insert barrel shifter

-- 01.11.2017 TG bugfix V-Flag for ASL/ASR - thanks Peter Graf

-- 29.05.2017 TG decode 0x4AFB as illegal, needed for QL BKP - thanks Peter Graf

-- 21.05.2017 TG insert generic for hardware multiplier for MULU & MULS

-- 04.04.2017 TG change GPL to LGPL

-- 04.04.2017 TG BCD handling with all undefined behavior! 

-- 02.04.2017 TG bugfix Bitfield Opcodes 

-- 19.03.2017 TG insert PACK/UNPACK  

-- 19.03.2017 TG bugfix CMPI ...(PC) - thanks Till Harbaum

--     ???    MJ bugfix non_aligned movem access

-- add berr handling 10.03.2013 - needed for ATARI Core

-- bugfix session 07/08.Feb.2013

-- movem ,-(an)

-- movem (an)+,          - thanks  Gerhard Suttner

-- btst dn,#data         - thanks  Peter Graf

-- movep                 - thanks  Till Harbaum

-- IPL vector            - thanks  Till Harbaum

--  

-- optimize Register file

-- to do 68010:

-- (MOVEC)

-- BKPT

-- MOVES

--

-- to do 68020:

-- (CALLM)

-- (RETM)

-- CAS, CAS2

-- CHK2

-- CMP2

-- cpXXX Coprozessor stuff

-- TRAPcc

-- done 020:

-- PACK

-- UNPK

-- Bitfields

-- address modes

-- long bra

-- DIVS.L, DIVU.L

-- LINK long

-- MULS.L, MULU.L

-- extb.l

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use work.TG68K_Pack.all;

entity TG68KdotC_Kernel is

        generic(

                SR_Read : integer:= 1;         --0=>user,   1=>privileged,      2=>switchable with CPU(0)

                VBR_Stackframe : integer:= 1;  --0=>no,     1=>yes/extended,    2=>switchable with CPU(0)

                extAddr_Mode : integer:= 1;    --0=>no,     1=>yes,    2=>switchable with CPU(1)

                MUL_Mode : integer := 1;           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no MUL,  

                MUL_Hardware : integer := 1;   --0=>no,         1=>yes,  

                DIV_Mode : integer := 1;           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no DIV,  

                BarrelShifter : integer := 2;  --0=>no,     1=>yes,    2=>switchable with CPU(1)  

                BitField : integer := 1            --0=>no,     1=>yes,    2=>switchable with CPU(1)  

--              SR_Read : integer:= 0;         --0=>user,   1=>privileged,      2=>switchable with CPU(0)

--              VBR_Stackframe : integer:= 0;  --0=>no,     1=>yes/extended,    2=>switchable with CPU(0)

--              extAddr_Mode : integer:= 0;    --0=>no,     1=>yes,    2=>switchable with CPU(1)

--              MUL_Mode : integer := 0;           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no MUL,  

--              MUL_Hardware : integer := 1;   --0=>no,         1=>yes,  

--              DIV_Mode : integer := 0;           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no DIV,  

--              BarrelShifter : integer := 0;  --0=>no,     1=>yes,    2=>switchable with CPU(1)  

--              BitField : integer := 0            --0=>no,     1=>yes,    2=>switchable with CPU(1)  

                );

        port(clk                : in std_logic;

                nReset                  : in std_logic;                 --low active

                clkena_in               : in std_logic:='1';

                data_in                 : in std_logic_vector(15 downto 0);

                IPL                                     : in std_logic_vector(2 downto 0):="111";

                IPL_autovector          : in std_logic:='0';

                berr                            : in std_logic:='0';                                     -- only 68000 Stackpointer dummy

                CPU                     : in std_logic_vector(1 downto 0):="00";  -- 00->68000  01->68010  11->68020(only some parts - yet)

                addr_out                : out std_logic_vector(31 downto 0);

                data_write              : out std_logic_vector(15 downto 0);

                nWr                                     : out std_logic;

                nUDS, nLDS                      : out std_logic;

                busstate                        : out std_logic_vector(1 downto 0);      -- 00-> fetch code 10->read data 11->write data 01->no memaccess

                nResetOut                       : out std_logic;

                FC                      : out std_logic_vector(2 downto 0);

--         

                clr_berr                        : out std_logic;

-- for debug            

                skipFetch                       : out std_logic;

--              regin                   : buffer std_logic_vector(31 downto 0)

                regin_out      : out std_logic_vector(31 downto 0);

                CACR_out       : out std_logic_vector( 3 downto 0);

                VBR_out        : out std_logic_vector(31 downto 0)

                );

end TG68KdotC_Kernel;

architecture logic of TG68KdotC_Kernel is

        signal syncReset                        : std_logic_vector(3 downto 0);

        signal Reset                            : std_logic;

        signal clkena_lw                        : std_logic;

        signal TG68_PC                          : std_logic_vector(31 downto 0);

        signal tmp_TG68_PC              : std_logic_vector(31 downto 0);

        signal TG68_PC_add              : std_logic_vector(31 downto 0);

        signal PC_dataa                 : std_logic_vector(31 downto 0);

        signal PC_datab                 : std_logic_vector(31 downto 0);

        signal memaddr                          : std_logic_vector(31 downto 0);

        signal state                            : std_logic_vector(1 downto 0);

        signal datatype                 : std_logic_vector(1 downto 0);

        signal set_datatype             : std_logic_vector(1 downto 0);

        signal exe_datatype             : std_logic_vector(1 downto 0);

        signal setstate                 : std_logic_vector(1 downto 0);

        signal opcode                           : std_logic_vector(15 downto 0);

        signal exe_opcode                       : std_logic_vector(15 downto 0);

        signal sndOPC                           : std_logic_vector(15 downto 0);

        signal last_opc_read            : std_logic_vector(15 downto 0);

        signal registerin                       : std_logic_vector(31 downto 0);

        signal reg_QA                           : std_logic_vector(31 downto 0);

        signal reg_QB                           : std_logic_vector(31 downto 0);

        signal Wwrena,Lwrena            : bit;

        signal Bwrena                           : bit;

        signal Regwrena_now             : bit;

        signal rf_dest_addr             : std_logic_vector(3 downto 0);

        signal rf_source_addr   : std_logic_vector(3 downto 0);

        signal rf_source_addrd  : std_logic_vector(3 downto 0);

        signal regin                            : std_logic_vector(31 downto 0);

        type   regfile_t is array(0 to 15) of std_logic_vector(31 downto 0);

        signal regfile                          : regfile_t := (OTHERS => (OTHERS => '0')); -- mikej stops sim X issues;

        signal RDindex_A                        : integer range 0 to 15;

        signal RDindex_B                        : integer range 0 to 15;

        signal WR_AReg                          : std_logic;

        signal addr                                     : std_logic_vector(31 downto 0);

        signal memaddr_reg              : std_logic_vector(31 downto 0);

        signal memaddr_delta            : std_logic_vector(31 downto 0);

        signal use_base                 : bit;

        signal ea_data                          : std_logic_vector(31 downto 0);

        signal OP1out                           : std_logic_vector(31 downto 0);

        signal OP2out                           : std_logic_vector(31 downto 0);

        signal OP1outbrief              : std_logic_vector(15 downto 0);

        signal OP1in                            : std_logic_vector(31 downto 0);

        signal ALUout   : std_logic_vector(31 downto 0);

        signal data_write_tmp   : std_logic_vector(31 downto 0);

        signal data_write_muxin : std_logic_vector(31 downto 0);

        signal data_write_mux   : std_logic_vector(47 downto 0);

        signal nextpass                 : bit;

        signal setnextpass              : bit;

        signal setdispbyte              : bit;

        signal setdisp                          : bit;

        signal regdirectsource  :bit;           -- checken !!!

        signal addsub_q                 : std_logic_vector(31 downto 0);

        signal briefdata                        : std_logic_vector(31 downto 0);

--      signal c_in                             : std_logic_vector(3 downto 0);

        signal c_out                            : std_logic_vector(2 downto 0);

        signal mem_address              : std_logic_vector(31 downto 0);

        signal memaddr_a                        : std_logic_vector(31 downto 0);

        signal TG68_PC_brw              : bit;

        signal TG68_PC_word             : bit;

        signal getbrief                 : bit;

        signal brief                            : std_logic_vector(15 downto 0);

        signal dest_areg                        : std_logic;

        signal source_areg              : std_logic;

        signal data_is_source   : bit;

        signal store_in_tmp             : bit;

        signal write_back                       : bit;

        signal exec_write_back  : bit;

        signal setstackaddr             : bit;

        signal writePC                          : bit;

        signal writePCbig                       : bit;

        signal set_writePCbig   : bit;

        signal setopcode                        : bit;

        signal decodeOPC                        : bit;

        signal execOPC                          : bit;

        signal setexecOPC                       : bit;

        signal endOPC                           : bit;

        signal setendOPC                        : bit;

        signal Flags                            : std_logic_vector(7 downto 0);  -- ...XNZVC

        signal FlagsSR                          : std_logic_vector(7 downto 0);  -- T.S.0III

        signal SRin                                     : std_logic_vector(7 downto 0);

        signal exec_DIRECT              : bit;

        signal exec_tas                 : std_logic;

        signal set_exec_tas             : std_logic;

        signal exe_condition            : std_logic;

        signal ea_only                          : bit;

        signal source_lowbits   : bit;

        signal source_2ndHbits  : bit;

        signal source_2ndLbits  : bit;

        signal dest_2ndHbits            : bit;

        signal dest_hbits                       : bit;

        signal rot_bits                 : std_logic_vector(1 downto 0);

        signal set_rot_bits             : std_logic_vector(1 downto 0);

        signal rot_cnt                          : std_logic_vector(5 downto 0);

        signal set_rot_cnt              : std_logic_vector(5 downto 0);

        signal movem_actiond            : bit;

        signal movem_regaddr            : std_logic_vector(3 downto 0);

        signal movem_mux                        : std_logic_vector(3 downto 0);

        signal movem_presub             : bit;

        signal movem_run                        : bit;

        signal ea_calc_b                        : std_logic_vector(31 downto 0);

        signal set_direct_data  : bit;

        signal use_direct_data  : bit;

        signal direct_data              : bit;

        signal set_V_Flag                       : bit;

        signal set_vectoraddr   : bit;

        signal writeSR                          : bit;

        signal trap_berr                        : bit;

        signal trap_illegal             : bit;

        signal trap_addr_error  : bit;

        signal trap_priv                        : bit;

        signal trap_trace                       : bit;

        signal trap_1010                        : bit;

        signal trap_1111                        : bit;

        signal trap_trap                        : bit;

        signal trap_trapv                       : bit;

        signal trap_interrupt   : bit;

        signal trapmake                 : bit;

        signal trapd                            : bit;

        signal trap_SR                          : std_logic_vector(7 downto 0);

        signal make_trace                       : std_logic;

        signal make_berr                        : std_logic;

        signal set_stop                 : bit;

        signal stop                                     : bit;

        signal trap_vector              : std_logic_vector(31 downto 0);

        signal trap_vector_vbr  : std_logic_vector(31 downto 0);

        signal USP                                      : std_logic_vector(31 downto 0);

--      signal illegal_write_mode       : bit;

--      signal illegal_read_mode        : bit;

--      signal illegal_byteaddr         : bit;

        signal IPL_nr                           : std_logic_vector(2 downto 0);

        signal rIPL_nr                          : std_logic_vector(2 downto 0);

        signal IPL_vec                          : std_logic_vector(7 downto 0);

        signal interrupt                        : bit;

        signal setinterrupt             : bit;

        signal SVmode                           : std_logic;

        signal preSVmode                        : std_logic;

        signal Suppress_Base            : bit;

        signal set_Suppress_Base: bit;

        signal set_Z_error              : bit;

        signal Z_error                  : bit;

        signal ea_build_now             : bit;

        signal build_logical            : bit;

        signal build_bcd                        : bit;

        signal data_read                        : std_logic_vector(31 downto 0);

        signal bf_ext_in                        : std_logic_vector(7 downto 0);

        signal bf_ext_out                       : std_logic_vector(7 downto 0);

--      signal byte                                     : bit;

        signal long_start                       : bit;

        signal long_start_alu   : bit;

        signal non_aligned              : std_logic;

        signal long_done                        : bit;

        signal memmask                          : std_logic_vector(5 downto 0);

        signal set_memmask              : std_logic_vector(5 downto 0);

        signal memread                          : std_logic_vector(3 downto 0);

        signal wbmemmask                        : std_logic_vector(5 downto 0);

        signal memmaskmux                       : std_logic_vector(5 downto 0);

        signal oddout                           : std_logic;

        signal set_oddout                       : std_logic;

        signal PCbase                           : std_logic;

        signal set_PCbase                       : std_logic;

        signal last_data_read   : std_logic_vector(31 downto 0);

        signal last_data_in             : std_logic_vector(31 downto 0);

        signal bf_offset                        : std_logic_vector(5 downto 0);

        signal bf_width                 : std_logic_vector(5 downto 0);

        signal bf_bhits                 : std_logic_vector(5 downto 0);

        signal bf_shift                 : std_logic_vector(5 downto 0);

        signal alu_width                        : std_logic_vector(5 downto 0);

        signal alu_bf_shift             : std_logic_vector(5 downto 0);

        signal bf_loffset                       : std_logic_vector(5 downto 0);

        signal bf_full_offset   : std_logic_vector(31 downto 0);

        signal alu_bf_ffo_offset: std_logic_vector(31 downto 0);

        signal alu_bf_loffset   : std_logic_vector(5 downto 0);

        signal movec_data                       : std_logic_vector(31 downto 0);

        signal VBR                                      : std_logic_vector(31 downto 0);

        signal CACR                                     : std_logic_vector(3 downto 0);

        signal DFC                                      : std_logic_vector(2 downto 0);

        signal SFC                                      : std_logic_vector(2 downto 0);

        signal set                                      : bit_vector(lastOpcBit downto 0);

        signal set_exec                 : bit_vector(lastOpcBit downto 0);

        signal exec                                     : bit_vector(lastOpcBit downto 0);

        signal micro_state              : micro_states;

        signal next_micro_state : micro_states;

BEGIN

ALU: TG68K_ALU

        generic map(

                MUL_Mode => MUL_Mode,                           --0=>16Bit,     1=>32Bit,       2=>switchable with CPU(1),              3=>no MUL,

                MUL_Hardware => MUL_Hardware,           --0=>no,                1=>yes,

                DIV_Mode => DIV_Mode,                           --0=>16Bit,     1=>32Bit,       2=>switchable with CPU(1),              3=>no DIV,

                BarrelShifter => BarrelShifter  --0=>no,                1=>yes,         2=>switchable with CPU(1)  

                )

    port map(

        clk => clk,                             --: in std_logic;

        Reset => Reset,                         --: in std_logic;

        clkena_lw => clkena_lw,         --: in std_logic:='1';

        execOPC => execOPC,             --: in bit;

        decodeOPC => decodeOPC,         --: in bit;

        exe_condition => exe_condition, --: in std_logic;

        exec_tas => exec_tas,                   --: in std_logic;

        long_start => long_start_alu,   --: in bit;

        non_aligned => non_aligned,

        movem_presub => movem_presub,   --: in bit;

        set_stop => set_stop,                   --: in bit;

        Z_error => Z_error,             --: in bit;

        rot_bits => rot_bits,           --: in std_logic_vector(1 downto 0);

        exec => exec,                   --: in bit_vector(lastOpcBit downto 0);

        OP1out => OP1out,                       --: in std_logic_vector(31 downto 0);

        OP2out => OP2out,                       --: in std_logic_vector(31 downto 0);

        reg_QA => reg_QA,                       --: in std_logic_vector(31 downto 0);

        reg_QB => reg_QB,                       --: in std_logic_vector(31 downto 0);

        opcode => opcode,                       --: in std_logic_vector(15 downto 0);

--        datatype => datatype,                 --: in std_logic_vector(1 downto 0);

        exe_opcode => exe_opcode,       --: in std_logic_vector(15 downto 0);

        exe_datatype => exe_datatype,   --: in std_logic_vector(1 downto 0);

        sndOPC => sndOPC,                       --: in std_logic_vector(15 downto 0);

        last_data_read => last_data_read(15 downto 0),   --: in std_logic_vector(31 downto 0);

        data_read => data_read(15 downto 0),                     --: in std_logic_vector(31 downto 0);

        FlagsSR => FlagsSR,             --: in std_logic_vector(7 downto 0);

        micro_state => micro_state,             --: in micro_states;  

        bf_ext_in => bf_ext_in,

        bf_ext_out => bf_ext_out,

        bf_shift => alu_bf_shift,

        bf_width => alu_width,

        bf_ffo_offset => alu_bf_ffo_offset,

        bf_loffset => alu_bf_loffset(4 downto 0),

        set_V_Flag => set_V_Flag,           --: buffer bit;

        Flags => Flags,                         --: buffer std_logic_vector(8 downto 0);

        c_out => c_out,                         --: buffer std_logic_vector(2 downto 0);

        addsub_q => addsub_q,           --: buffer std_logic_vector(31 downto 0);

        ALUout => ALUout                        --: buffer std_logic_vector(31 downto 0)

    );

   long_start_alu <= to_bit(NOT memmaskmux(3));

   process (memmaskmux)

   begin

      non_aligned <= '0';

      if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then

         non_aligned <= '1';

      end if;

    end process;

-----------------------------------------------------------------------------

-- Bus control

-----------------------------------------------------------------------------

   regin_out <= regin;

        nWr <= '0' WHEN state="11" ELSE '1';

        busstate <= state;

        nResetOut <= '0' WHEN exec(opcRESET)='1' ELSE '1';

   -- does shift for byte access. note active low me

   -- should produce address error on 68000

   memmaskmux <= memmask when addr(0) = '1' else memmask(4 downto 0) & '1';

        nUDS <= memmaskmux(5);

        nLDS <= memmaskmux(4);

        clkena_lw <= '1' WHEN clkena_in='1' AND memmaskmux(3)='1' ELSE '0';

        clr_berr <= '1' WHEN setopcode='1' AND trap_berr='1' ELSE '0';

        PROCESS (clk, nReset)

        BEGIN

                IF nReset='0' THEN

                        syncReset <= "0000";

                        Reset <= '1';

                ELSIF rising_edge(clk) THEN

                        IF clkena_in='1' THEN

                                syncReset <= syncReset(2 downto 0)&'1';

                                Reset <= NOT syncReset(3);

                        END IF;

                END IF;

        END PROCESS;

PROCESS (clk, long_done, last_data_in, data_in, addr, long_start, memmaskmux, memread, memmask, data_read)

        BEGIN

                IF memmaskmux(4)='0' THEN

                        data_read <= last_data_in(15 downto 0)&data_in;

                ELSE

                        data_read <= last_data_in(23 downto 0)&data_in(15 downto 8);

                END IF;

                IF memread(0)='1' OR (memread(1 downto 0)="10" AND memmaskmux(4)='1')THEN

                        data_read(31 downto 16) <= (OTHERS=>data_read(15));

                END IF;

                IF rising_edge(clk) THEN

                        IF clkena_lw='1' AND state="10" THEN

                                IF memmaskmux(4)='0' THEN

                                        bf_ext_in <= last_data_in(23 downto 16);

                                ELSE

                                        bf_ext_in <= last_data_in(31 downto 24);

                                END IF;

                        END IF;

                        IF Reset='1' THEN

                                last_data_read <= (OTHERS => '0');

                        ELSIF clkena_in='1' THEN

                                IF state="00" OR exec(update_ld)='1' THEN

                                        last_data_read <= data_read;

                                        IF state(1)='0' AND memmask(1)='0' THEN

                                                last_data_read(31 downto 16) <= last_opc_read;

                                        ELSIF state(1)='0' OR memread(1)='1' THEN

                                                last_data_read(31 downto 16) <= (OTHERS=>data_in(15));

                                        END IF;

                                END IF;

                                last_data_in <= last_data_in(15 downto 0)&data_in(15 downto 0);

                        END IF;

                END IF;

                                long_start <= to_bit(NOT memmask(1));

                                long_done <= to_bit(NOT memread(1));

        END PROCESS;

PROCESS (long_start, reg_QB, data_write_tmp, exec, data_read, data_write_mux, memmaskmux, bf_ext_out,

                 data_write_muxin, memmask, oddout, addr)

        BEGIN

                IF exec(write_reg)='1' THEN

                        data_write_muxin <= reg_QB;

                ELSE

                        data_write_muxin <= data_write_tmp;

                END IF;

                IF BitField=0 THEN

                        IF oddout=addr(0) THEN

                                data_write_mux <= "--------"&"--------"&data_write_muxin;

                        ELSE

                                data_write_mux <= "--------"&data_write_muxin&"--------";

                        END IF;

                ELSE

                        IF oddout=addr(0) THEN

                                data_write_mux <= "--------"&bf_ext_out&data_write_muxin;

                        ELSE

                                data_write_mux <= bf_ext_out&data_write_muxin&"--------";

                        END IF;

                END IF;

                IF memmaskmux(1)='0' THEN

                        data_write <= data_write_mux(47 downto 32);

                ELSIF memmaskmux(3)='0' THEN

                        data_write <= data_write_mux(31 downto 16);

                ELSE

                        data_write <= data_write_mux(15 downto 0);

                END IF;

                IF exec(mem_byte)='1' THEN      --movep

                        data_write(7 downto 0) <= data_write_tmp(15 downto 8);

                END IF;

        END PROCESS;

-----------------------------------------------------------------------------

-- Registerfile

-----------------------------------------------------------------------------

PROCESS (clk, regfile, RDindex_A, RDindex_B, exec)

        BEGIN

                reg_QA <= regfile(RDindex_A);

                reg_QB <= regfile(RDindex_B);

                IF rising_edge(clk) THEN

                    IF clkena_lw='1' THEN

                                rf_source_addrd <= rf_source_addr;

                                WR_AReg <= rf_dest_addr(3);

                                RDindex_A <= conv_integer(rf_dest_addr(3 downto 0));

                                RDindex_B <= conv_integer(rf_source_addr(3 downto 0));

                                IF Wwrena='1' THEN

                                        regfile(RDindex_A) <= regin;

                                END IF;

                                IF exec(to_USP)='1' THEN

                                        USP <= reg_QA;

                                END IF;

                        END IF;

                END IF;

        END PROCESS;

-----------------------------------------------------------------------------

-- Write Reg

-----------------------------------------------------------------------------

PROCESS (OP1in, reg_QA, Regwrena_now, Bwrena, Lwrena, exe_datatype, WR_AReg, movem_actiond, exec, ALUout, memaddr, memaddr_a, ea_only, USP, movec_data)

        BEGIN

                regin <= ALUout;

                IF exec(save_memaddr)='1' THEN

                        regin <= memaddr;

                ELSIF exec(get_ea_now)='1' AND ea_only='1' THEN

                        regin <= memaddr_a;

                ELSIF exec(from_USP)='1' THEN

                        regin <= USP;

                ELSIF exec(movec_rd)='1' THEN

                        regin <= movec_data;

                END IF;

                IF Bwrena='1' THEN

                        regin(15 downto 8) <= reg_QA(15 downto 8);

                END IF;

                IF Lwrena='0' THEN

                        regin(31 downto 16) <= reg_QA(31 downto 16);

                END IF;

                Bwrena <= '0';

                Wwrena <= '0';

                Lwrena <= '0';

                IF exec(presub)='1' OR exec(postadd)='1' OR exec(changeMode)='1' THEN           -- -(An)+

                        Wwrena <= '1';

                        Lwrena <= '1';

                ELSIF Regwrena_now='1' THEN             --dbcc  

                        Wwrena <= '1';

                ELSIF exec(Regwrena)='1' THEN           --read (mem)

                        Wwrena <= '1';

                        CASE exe_datatype IS

                                WHEN "00" =>            --BYTE

                                        Bwrena <= '1';

                                WHEN "01" =>            --WORD

                                        IF WR_AReg='1' OR movem_actiond='1' THEN

                                                Lwrena <='1';

                                        END IF;

                                WHEN OTHERS =>          --LONG

                                        Lwrena <= '1';

                        END CASE;

                END IF;

        END PROCESS;

-----------------------------------------------------------------------------

-- set dest regaddr

-----------------------------------------------------------------------------

PROCESS (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, data_is_source, sndOPC, exec, set, dest_2ndHbits)

        BEGIN

                IF exec(movem_action) ='1' THEN

                        rf_dest_addr <= rf_source_addrd;

                ELSIF set(briefext)='1' THEN

                        rf_dest_addr <= brief(15 downto 12);

                ELSIF set(get_bfoffset)='1' THEN

                        IF opcode(15 downto 12)="1110" THEN

                                rf_dest_addr <= '0'&sndOPC(8 downto 6);

                        ELSE

                                rf_dest_addr <= sndOPC(9 downto 6);

                        END IF;

                ELSIF dest_2ndHbits='1' THEN

                        rf_dest_addr <= '0'&sndOPC(14 downto 12);