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//----------------------------------------------------------------------------

// User entered comments

//----------------------------------------------------------------------------

// None

//

//----------------------------------------------------------------------------

//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase

//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)

//----------------------------------------------------------------------------

// __clk100___100.000______0.000______50.0______144.719____114.212

// __clk400___400.000______0.000______50.0______111.164____114.212

// ___clk80____80.000______0.000______50.0______151.652____114.212

// ___clk50____25.000______0.000______50.0______191.696____114.212

// __clk200___100.000______0.000______50.0______144.719____114.212

//

//----------------------------------------------------------------------------

// Input Clock   Freq (MHz)    Input Jitter (UI)

//----------------------------------------------------------------------------

// __primary_________100.000____________0.010

// The following must be inserted into your Verilog file for this

// core to be instantiated. Change the instance name and port connections

// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

  NexysVideoClkgen instance_name

   (

    // Clock out ports

    .clk100(clk100),     // output clk100

    .clk400(clk400),     // output clk400

    .clk80(clk80),     // output clk80

    .clk50(clk50),     // output clk50

    .clk200(clk200),     // output clk200

    // Status and control signals

    .reset(reset), // input reset

    .locked(locked),       // output locked

   // Clock in ports

    .clk_in1(clk_in1));      // input clk_in1

// INST_TAG_END ------ End INSTANTIATION Template ---------