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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [CardMemory.v] - Blame information for rev 48

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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      CardMemory.v
//              
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
// ============================================================================
//
module CardMemory(clk_i, cs_i, ack_o, wr_i, adr_i, dat_i, dat_o, stp, mapno);
input clk_i;
input cs_i;
output reg ack_o;               // acknowledge
input wr_i;
input [31:0] adr_i;
input [63:0] dat_i;
output reg [63:0] dat_o;
input stp;                              // store pointer
input [5:0] mapno;
 
parameter IDLE = 3'd0;
parameter ACC  = 3'd1;
parameter STP1a = 3'd2;
parameter STP1b = 3'd3;
parameter STP1c = 3'd4;
parameter STP2a = 3'd5;
parameter STP2b = 3'd6;
 
reg [2:0] state = IDLE;
reg wcm;
reg [13:0] ma;
reg  [5:0] bn;
reg [63:0] da;
wire [63:0] memo;
reg [63:0] mem [0:16383];
 
reg [19:0] stpa, stpb;
reg [1:0] sf;
 
always @(posedge clk_i)
begin
        case(state)
        IDLE:
                begin
                        wcm <= 1'b0;
                        ack_o <= 1'b0;
                        if (cs_i) begin
                                ma <= {mapno,adr_i[10:3]};
                                da <= dat_i;
                                wcm <= wr_i;
                                if (!wr_i)
                                        state <= ACC;
                                else
                                        ack_o <= 1'b1;
                        end
                        else if (stp) begin
                                ma <= {mapno,adr_i[18:11]};
                                bn <= adr_i[10:5];
                                state <= STP1a;
                        end
                end
        ACC:
                begin
                        dat_o <= memo;
                        ack_o <= 1'b1;
                        state <= IDLE;
                end
        STP1a:
                begin
                        da <= memo;
                        state <= STP1b;
                end
        STP1b:
                begin
                        da <= da | (64'd1 << bn);
                        wcm <= 1'b1;
                        state <= STP1c;
                end
        STP1c:
                begin
                        wcm <= 1'b0;
                        ma <= {mapno,6'd0,adr_i[18:17]};
                        bn <= adr_i[16:11];
                        state <= STP2a;
                end
        STP2a:
                begin
                        da <= memo;
                        state <= STP2b;
                end
        STP2b:
                begin
                        da <= da | (64'd1 << bn);
                        wcm <= 1'b1;
                        state <= IDLE;
                end
        default:
                state <= IDLE;
        endcase
end
 
always @(posedge clk_i)
        if (wcm)
                mem[ma] <= da;
 
assign memo = mem[ma];
 
endmodule

Line No.	Rev	Author	Line
1	48	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@finitron.ca`
7			`// \|\|`
8			`//`
9			`// CardMemory.v`
10			`//`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`//`
26			`// ============================================================================`
27			`//`
28			`module CardMemory(clk_i, cs_i, ack_o, wr_i, adr_i, dat_i, dat_o, stp, mapno);`
29			`input clk_i;`
30			`input cs_i;`
31			`output reg ack_o; // acknowledge`
32			`input wr_i;`
33			`input [31:0] adr_i;`
34			`input [63:0] dat_i;`
35			`output reg [63:0] dat_o;`
36			`input stp; // store pointer`
37			`input [5:0] mapno;`
38
39			`parameter IDLE = 3'd0;`
40			`parameter ACC = 3'd1;`
41			`parameter STP1a = 3'd2;`
42			`parameter STP1b = 3'd3;`
43			`parameter STP1c = 3'd4;`
44			`parameter STP2a = 3'd5;`
45			`parameter STP2b = 3'd6;`
46
47			`reg [2:0] state = IDLE;`
48			`reg wcm;`
49			`reg [13:0] ma;`
50			`reg [5:0] bn;`
51			`reg [63:0] da;`
52			`wire [63:0] memo;`
53			`reg [63:0] mem [0:16383];`
54
55			`reg [19:0] stpa, stpb;`
56			`reg [1:0] sf;`
57
58			`always @(posedge clk_i)`
59			`begin`
60			`case(state)`
61			`IDLE:`
62			`begin`
63			`wcm <= 1'b0;`
64			`ack_o <= 1'b0;`
65			`if (cs_i) begin`
66			`ma <= {mapno,adr_i[10:3]};`
67			`da <= dat_i;`
68			`wcm <= wr_i;`
69			`if (!wr_i)`
70			`state <= ACC;`
71			`else`
72			`ack_o <= 1'b1;`
73			`end`
74			`else if (stp) begin`
75			`ma <= {mapno,adr_i[18:11]};`
76			`bn <= adr_i[10:5];`
77			`state <= STP1a;`
78			`end`
79			`end`
80			`ACC:`
81			`begin`
82			`dat_o <= memo;`
83			`ack_o <= 1'b1;`
84			`state <= IDLE;`
85			`end`
86			`STP1a:`
87			`begin`
88			`da <= memo;`
89			`state <= STP1b;`
90			`end`
91			`STP1b:`
92			`begin`
93			`da <= da \| (64'd1 << bn);`
94			`wcm <= 1'b1;`
95			`state <= STP1c;`
96			`end`
97			`STP1c:`
98			`begin`
99			`wcm <= 1'b0;`
100			`ma <= {mapno,6'd0,adr_i[18:17]};`
101			`bn <= adr_i[16:11];`
102			`state <= STP2a;`
103			`end`
104			`STP2a:`
105			`begin`
106			`da <= memo;`
107			`state <= STP2b;`
108			`end`
109			`STP2b:`
110			`begin`
111			`da <= da \| (64'd1 << bn);`
112			`wcm <= 1'b1;`
113			`state <= IDLE;`
114			`end`
115			`default:`
116			`state <= IDLE;`
117			`endcase`
118			`end`
119
120			`always @(posedge clk_i)`
121			`if (wcm)`
122			`mem[ma] <= da;`
123
124			`assign memo = mem[ma];`
125
126			`endmodule`

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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [CardMemory.v] - Blame information for rev 48