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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_FCU_Calc.v] - Blame information for rev 48

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1 48 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// FT64_FCU_Calc.v
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// - FT64 flow control calcs
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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// ============================================================================
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//
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`include ".\FT64_defines.vh"
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module FT64_FCU_Calc(ol, instr, tvec, a, i, pc, im, waitctr, bus);
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parameter WID = 64;
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parameter AMSB = 31;
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input [1:0] ol;
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input [47:0] instr;
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input [WID-1:0] tvec;
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input [WID-1:0] a;
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input [WID-1:0] i;
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input [AMSB:0] pc;
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input [2:0] im;
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input [WID-1:0] waitctr;
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output reg [WID-1:0] bus;
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always @*
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begin
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  casez(instr[`INSTRUCTION_OP])
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  `BRK:   bus <= {{56{1'b0}},instr[15:8]};
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  `BBc:
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    case(instr[20:19])
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                `IBNE:  bus <=  a + 64'd1;
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                `DBNZ:  bus <=  a - 64'd1;
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                default:        bus <= 64'hCCCCCCCCCCCCCCCC;
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                endcase
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  `JAL:   bus <= pc + (instr[6] ? 32'd6 : 32'd4);
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  `CALL:        bus <= pc + (instr[6] ? 32'd6 : 32'd4);
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  `RET: bus <= a + i;
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  `REX:
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    case(ol)
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    `OL_USER:   bus <= 64'hCCCCCCCCCCCCCCCC;
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    // ToDo: fix im test
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    default:    bus <= (im < ~ol) ? tvec : pc + 32'd4;
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    endcase
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  `WAIT:  bus = waitctr==64'd1;
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  default:    bus <= 64'hCCCCCCCCCCCCCCCC;
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  endcase
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end
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endmodule
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