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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_RSB.v] - Blame information for rev 49

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// ============================================================================
//        __
//   \\__/ o\    (C) 2018  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      FT64_RSB.v
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
// ============================================================================
//
`include "FT64_defines.vh"
 
// Return address stack predictor is updated during the fetch stage on the 
// assumption that previous flow controls (branches) predicted correctly.
// Otherwise many small routines wouldn't predict the return address
// correctly because they hit the RET before the CALL reaches the 
// commit stage.
 
module FT64_RSB(rst, clk, regLR, queued1, queued2,
        fetchbuf0_v, fetchbuf0_pc, fetchbuf0_instr,
        fetchbuf1_v, fetchbuf1_pc, fetchbuf1_instr,
        stompedRets, stompedRet,
        pc
);
parameter AMSB = 31;
parameter DEPTH = 16;
input rst;
input clk;
input [4:0] regLR;
input queued1;
input queued2;
input fetchbuf0_v;
input [47:0] fetchbuf0_instr;
input [AMSB:0] fetchbuf0_pc;
input fetchbuf1_v;
input [47:0] fetchbuf1_instr;
input [AMSB:0] fetchbuf1_pc;
input [3:0] stompedRets;
input stompedRet;
output [AMSB:0] pc;
 
parameter RSTPC = 32'hFFFC0100;
integer n;
reg [AMSB:0] ras [0:DEPTH-1];
reg [3:0] rasp;
assign pc = ras[rasp];
reg [47:0] lasti0, lasti1;
 
always @(posedge clk)
if (rst) begin
        lasti0 <= `NOP_INSN;
        lasti1 <= `NOP_INSN;
  for (n = 0; n < DEPTH; n = n + 1)
     ras[n] <= RSTPC;
  rasp <= 4'd0;
end
else begin
        if (fetchbuf0_v && fetchbuf1_v && (queued1 || queued2)) begin
                // Make sure the instruction changed between clock cycles.
                lasti0 <= fetchbuf0_instr;
                lasti1 <= fetchbuf1_instr;
                if (fetchbuf0_instr != lasti0 || fetchbuf1_instr != lasti1) begin
        case(fetchbuf0_instr[`INSTRUCTION_OP])
        `JAL:
                begin
                        // JAL LR,xxxx  assume call
                        if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
                        ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
                        rasp <= rasp - 4'd1;
                        end
                        // JAL r0,[r29] assume a ret
                        else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
                                         fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
                                rasp <= rasp + 4'd1;
                        end
                end
        `CALL:
            begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
            end
        `RET:   begin
                        $display("RSP: Added 1");
                        rasp <= rasp + 4'd1;
                        end
        default:        ;
        endcase
    end
        end
    else if (fetchbuf1_v && queued1)
        lasti1 <= fetchbuf1_instr;
        if (fetchbuf1_instr != lasti1) begin
        case(fetchbuf1_instr[`INSTRUCTION_OP])
        `JAL:
                if (fetchbuf1_instr[`INSTRUCTION_RB]==regLR) begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + (fetchbuf1_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
                end
                else if (fetchbuf1_instr[`INSTRUCTION_RB]==5'd00 &&
                                 fetchbuf1_instr[`INSTRUCTION_RA]==regLR) begin
                        rasp <= rasp + 4'd1;
                end
        `CALL:
            begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + (fetchbuf1_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
            end
        `RET:   begin
                        rasp <= rasp + 4'd1;
                        $display("RSP: Added 1");
                        end
        default:        ;
        endcase
      end
    else if (fetchbuf0_v && queued1)
        lasti0 <= fetchbuf0_instr;
        if (lasti0 != fetchbuf0_instr) begin
        case(fetchbuf0_instr[`INSTRUCTION_OP])
        `JAL:
                if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
                end
                else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
                                 fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
                        rasp <= rasp + 4'd1;
                end
        `CALL:
            begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
            end
        `RET:   begin
                        $display("RSP: Added 1");
                        rasp <= rasp + 4'd1;
                        end
        default:        ;
        endcase
      end
/*
    if (stompedRets > 4'd0) begin
        $display("Stomped Rets: %d", stompedRets);
        rasp <= rasp - stompedRets;
    end
    else if (stompedRet) begin
        $display("Stomped Ret");
        rasp <= rasp - 5'd1;
    end
*/
end
 
endmodule

Line No.	Rev	Author	Line
1	48	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2018 Robert Finch, Waterloo`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@finitron.ca`
6			`// \|\|`
7			`//`
8			`// FT64_RSB.v`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`// ============================================================================`
24			`//`
25			`include "FT64_defines.vh"
26
27			`// Return address stack predictor is updated during the fetch stage on the`
28			`// assumption that previous flow controls (branches) predicted correctly.`
29			`// Otherwise many small routines wouldn't predict the return address`
30			`// correctly because they hit the RET before the CALL reaches the`
31			`// commit stage.`
32
33			`module FT64_RSB(rst, clk, regLR, queued1, queued2,`
34			`fetchbuf0_v, fetchbuf0_pc, fetchbuf0_instr,`
35			`fetchbuf1_v, fetchbuf1_pc, fetchbuf1_instr,`
36			`stompedRets, stompedRet,`
37			`pc`
38			`);`
39			`parameter AMSB = 31;`
40			`parameter DEPTH = 16;`
41			`input rst;`
42			`input clk;`
43			`input [4:0] regLR;`
44			`input queued1;`
45			`input queued2;`
46			`input fetchbuf0_v;`
47			`input [47:0] fetchbuf0_instr;`
48			`input [AMSB:0] fetchbuf0_pc;`
49			`input fetchbuf1_v;`
50			`input [47:0] fetchbuf1_instr;`
51			`input [AMSB:0] fetchbuf1_pc;`
52			`input [3:0] stompedRets;`
53			`input stompedRet;`
54			`output [AMSB:0] pc;`
55
56			`parameter RSTPC = 32'hFFFC0100;`
57			`integer n;`
58			`reg [AMSB:0] ras [0:DEPTH-1];`
59	49	robfinch	`reg [3:0] rasp;`
60	48	robfinch	`assign pc = ras[rasp];`
61	49	robfinch	`reg [47:0] lasti0, lasti1;`
62	48	robfinch
63			`always @(posedge clk)`
64			`if (rst) begin`
65	49	robfinch	lasti0 <= `NOP_INSN;
66			lasti1 <= `NOP_INSN;
67			`for (n = 0; n < DEPTH; n = n + 1)`
68			`ras[n] <= RSTPC;`
69			`rasp <= 4'd0;`
70	48	robfinch	`end`
71			`else begin`
72			`if (fetchbuf0_v && fetchbuf1_v && (queued1 \|\| queued2)) begin`
73	49	robfinch	`// Make sure the instruction changed between clock cycles.`
74			`lasti0 <= fetchbuf0_instr;`
75			`lasti1 <= fetchbuf1_instr;`
76			`if (fetchbuf0_instr != lasti0 \|\| fetchbuf1_instr != lasti1) begin`
77	48	robfinch	case(fetchbuf0_instr[`INSTRUCTION_OP])
78			`JAL:
79			`begin`
80			`// JAL LR,xxxx assume call`
81			if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
82	49	robfinch	`ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);`
83	48	robfinch	`rasp <= rasp - 4'd1;`
84			`end`
85			`// JAL r0,[r29] assume a ret`
86			else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
87			fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
88			`rasp <= rasp + 4'd1;`
89			`end`
90			`end`
91			`CALL:
92			`begin`
93	49	robfinch	`ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);`
94	48	robfinch	`rasp <= rasp - 4'd1;`
95			`end`
96			`RET: begin
97			`$display("RSP: Added 1");`
98			`rasp <= rasp + 4'd1;`
99			`end`
100			`default: ;`
101			`endcase`
102	49	robfinch	`end`
103	48	robfinch	`end`
104			`else if (fetchbuf1_v && queued1)`
105	49	robfinch	`lasti1 <= fetchbuf1_instr;`
106			`if (fetchbuf1_instr != lasti1) begin`
107	48	robfinch	case(fetchbuf1_instr[`INSTRUCTION_OP])
108			`JAL:
109			if (fetchbuf1_instr[`INSTRUCTION_RB]==regLR) begin
110	49	robfinch	`ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + (fetchbuf1_instr[6] ? 32'd6 : 32'd4);`
111	48	robfinch	`rasp <= rasp - 4'd1;`
112			`end`
113			else if (fetchbuf1_instr[`INSTRUCTION_RB]==5'd00 &&
114			fetchbuf1_instr[`INSTRUCTION_RA]==regLR) begin
115			`rasp <= rasp + 4'd1;`
116			`end`
117			`CALL:
118			`begin`
119	49	robfinch	`ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + (fetchbuf1_instr[6] ? 32'd6 : 32'd4);`
120	48	robfinch	`rasp <= rasp - 4'd1;`
121			`end`
122			`RET: begin
123			`rasp <= rasp + 4'd1;`
124			`$display("RSP: Added 1");`
125			`end`
126			`default: ;`
127			`endcase`
128	49	robfinch	`end`
129	48	robfinch	`else if (fetchbuf0_v && queued1)`
130	49	robfinch	`lasti0 <= fetchbuf0_instr;`
131			`if (lasti0 != fetchbuf0_instr) begin`
132	48	robfinch	case(fetchbuf0_instr[`INSTRUCTION_OP])
133			`JAL:
134			if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
135	49	robfinch	`ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);`
136	48	robfinch	`rasp <= rasp - 4'd1;`
137			`end`
138			else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
139			fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
140			`rasp <= rasp + 4'd1;`
141			`end`
142			`CALL:
143			`begin`
144	49	robfinch	`ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);`
145	48	robfinch	`rasp <= rasp - 4'd1;`
146			`end`
147			`RET: begin
148			`$display("RSP: Added 1");`
149			`rasp <= rasp + 4'd1;`
150			`end`
151			`default: ;`
152			`endcase`
153	49	robfinch	`end`
154	48	robfinch	`/*`
155			`if (stompedRets > 4'd0) begin`
156			`$display("Stomped Rets: %d", stompedRets);`
157			`rasp <= rasp - stompedRets;`
158			`end`
159			`else if (stompedRet) begin`
160			`$display("Stomped Ret");`
161			`rasp <= rasp - 5'd1;`
162			`end`
163			`*/`
164			`end`
165
166			`endmodule`

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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_RSB.v] - Blame information for rev 49