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// ============================================================================
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT64_idecoder.v
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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robfinch |
`include ".\FT64_config.vh"
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robfinch |
`include ".\FT64_defines.vh"
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module FT64_idecoder(clk,idv_i,id_i,instr,vl,ven,thrd,predict_taken,Rt,bus,id_o,idv_o);
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input clk;
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input idv_i;
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input [4:0] id_i;
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input [47:0] instr;
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input [7:0] vl;
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input [5:0] ven;
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input thrd;
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input predict_taken;
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input [4:0] Rt;
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output reg [143:0] bus;
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output reg [4:0] id_o;
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output reg idv_o;
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parameter TRUE = 1'b1;
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parameter FALSE = 1'b0;
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// Memory access sizes
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parameter byt = 3'd0;
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parameter wyde = 3'd1;
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parameter tetra = 3'd2;
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parameter octa = 3'd3;
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robfinch |
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// Really IsPredictableBranch
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// Does not include BccR's
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//function IsBranch;
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//input [47:0] isn;
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//casez(isn[`INSTRUCTION_OP])
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//`Bcc: IsBranch = TRUE;
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//`BBc: IsBranch = TRUE;
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//`BEQI: IsBranch = TRUE;
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//`CHK: IsBranch = TRUE;
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//default: IsBranch = FALSE;
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//endcase
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//endfunction
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wire [10:0] brdisp = instr[31:21];
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wire iAlu;
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mIsALU uialu1
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(
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.instr(instr),
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.IsALU(iAlu)
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);
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reg IsALU;
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always @*
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case(instr[`INSTRUCTION_OP])
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`R2:
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if (instr[`INSTRUCTION_L2]==2'b00)
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case(instr[`INSTRUCTION_S2])
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`VMOV: IsALU = TRUE;
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`RTI: IsALU = FALSE;
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default: IsALU = TRUE;
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endcase
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else
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IsALU = TRUE;
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`BRK: IsALU = FALSE;
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`Bcc: IsALU = FALSE;
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`BBc: IsALU = FALSE;
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`BEQI: IsALU = FALSE;
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`CHK: IsALU = FALSE;
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`JAL: IsALU = FALSE;
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`JMP: IsALU = FALSE;
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`CALL: IsALU = FALSE;
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`RET: IsALU = FALSE;
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`FVECTOR:
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case(instr[`INSTRUCTION_S2])
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`VSHL,`VSHR,`VASR: IsALU = TRUE;
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default: IsALU = FALSE; // Integer
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endcase
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`IVECTOR:
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case(instr[`INSTRUCTION_S2])
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`VSHL,`VSHR,`VASR: IsALU = TRUE;
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default: IsALU = TRUE; // Integer
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endcase
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`FLOAT: IsALU = FALSE;
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default: IsALU = TRUE;
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endcase
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function IsAlu0Only;
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input [47:0] isn;
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begin
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case(isn[`INSTRUCTION_OP])
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`R2:
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if (isn[`INSTRUCTION_L2]==2'b00)
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case(isn[`INSTRUCTION_S2])
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`R1: IsAlu0Only = TRUE;
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`SHIFTR,`SHIFT31,`SHIFT63:
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IsAlu0Only = !(instr[25:23]==`SHL || instr[25:23]==`ASL);
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`MULU,`MULSU,`MUL,
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`MULUH,`MULSUH,`MULH,
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`MODU,`MODSU,`MOD: IsAlu0Only = TRUE;
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`DIVU,`DIVSU,`DIV: IsAlu0Only = TRUE;
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`MIN,`MAX: IsAlu0Only = TRUE;
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default: IsAlu0Only = FALSE;
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endcase
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else
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IsAlu0Only = FALSE;
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`MEMNDX: IsAlu0Only = TRUE;
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`IVECTOR,`FVECTOR:
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case(isn[`INSTRUCTION_S2])
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`VSHL,`VSHR,`VASR: IsAlu0Only = TRUE;
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default: IsAlu0Only = FALSE;
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endcase
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`BITFIELD: IsAlu0Only = TRUE;
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`MULUI,`MULI,
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`DIVUI,`DIVI,
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`MODI: IsAlu0Only = TRUE;
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`CSRRW: IsAlu0Only = TRUE;
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default: IsAlu0Only = FALSE;
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endcase
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end
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endfunction
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function IsFPU;
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input [47:0] isn;
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begin
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case(isn[`INSTRUCTION_OP])
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`FLOAT: IsFPU = TRUE;
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`FVECTOR:
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case(isn[`INSTRUCTION_S2])
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`VSHL,`VSHR,`VASR: IsFPU = FALSE;
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default: IsFPU = TRUE;
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endcase
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default: IsFPU = FALSE;
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endcase
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end
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endfunction
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reg IsFlowCtrl;
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always @*
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case(instr[`INSTRUCTION_OP])
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`BRK: IsFlowCtrl <= TRUE;
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robfinch |
`R2: case(instr[`INSTRUCTION_S2])
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`RTI: IsFlowCtrl <= TRUE;
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default: IsFlowCtrl <= FALSE;
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endcase
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`Bcc: IsFlowCtrl <= TRUE;
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`BBc: IsFlowCtrl <= TRUE;
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`BEQI: IsFlowCtrl <= TRUE;
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`CHK: IsFlowCtrl <= TRUE;
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`JAL: IsFlowCtrl <= TRUE;
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`JMP: IsFlowCtrl <= TRUE;
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`CALL: IsFlowCtrl <= TRUE;
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`RET: IsFlowCtrl <= TRUE;
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default: IsFlowCtrl <= FALSE;
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endcase
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//function IsFlowCtrl;
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//input [47:0] isn;
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//begin
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//case(isn[`INSTRUCTION_OP])
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//`BRK: IsFlowCtrl = TRUE;
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//`RR: case(isn[`INSTRUCTION_S2])
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// `RTI: IsFlowCtrl = TRUE;
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// default: IsFlowCtrl = FALSE;
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// endcase
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//`Bcc: IsFlowCtrl = TRUE;
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//`BBc: IsFlowCtrl = TRUE;
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//`BEQI: IsFlowCtrl = TRUE;
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//`CHK: IsFlowCtrl = TRUE;
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//`JAL: IsFlowCtrl = TRUE;
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//`JMP: IsFlowCtrl = TRUE;
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//`CALL: IsFlowCtrl = TRUE;
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//`RET: IsFlowCtrl = TRUE;
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//default: IsFlowCtrl = FALSE;
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//endcase
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//end
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//endfunction
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// fnCanException
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//
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// Used by memory issue logic (stores).
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// Returns TRUE if the instruction can cause an exception.
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// In debug mode any instruction could potentially cause a breakpoint exception.
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// Rather than check all the addresses for potential debug exceptions it's
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// simpler to just have it so that all instructions could exception. This will
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// slow processing down somewhat as stores will only be done at the head of the
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// instruction queue, but it's debug mode so we probably don't care.
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//
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function fnCanException;
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input [47:0] isn;
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begin
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// ToDo add debug_on as input
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`ifdef SUPPORT_DBG
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if (debug_on)
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fnCanException = `TRUE;
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else
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`endif
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case(isn[`INSTRUCTION_OP])
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`FLOAT:
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case(isn[`INSTRUCTION_S2])
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`FDIV,`FMUL,`FADD,`FSUB,`FTX:
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fnCanException = `TRUE;
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default: fnCanException = `FALSE;
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endcase
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robfinch |
`DIVI,`MODI,`MULI:
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fnCanException = `TRUE;
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`R2:
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case(isn[`INSTRUCTION_S2])
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robfinch |
`MUL,
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`DIV,`MULSU,`DIVSU,
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`MOD,`MODSU:
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fnCanException = TRUE;
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`RTI: fnCanException = TRUE;
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default: fnCanException = FALSE;
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endcase
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// Had branches that could exception if looping to self. But in a tight loop
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// it affects store performance.
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// -> A branch may only exception if it loops back to itself.
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`Bcc,`BBc,`BEQI: fnCanException = isn[7] ? brdisp == 11'h7FF : brdisp == 11'h7FE;
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`CHK: fnCanException = TRUE;
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default:
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// Stores can stil exception if there is a write buffer, but we allow following
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// stores to be issued by ignoring the fact they can exception because the stores
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// can be undone by invalidating the write buffer.
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`ifdef HAS_WB
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fnCanException = IsMem(isn) && !IsStore(isn);
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`else
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fnCanException = IsMem(isn);
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`endif
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endcase
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end
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endfunction
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function IsLoad;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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`MEMNDX:
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if (isn[`INSTRUCTION_L2]==2'b00)
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case(isn[`INSTRUCTION_S2])
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`LBX: IsLoad = TRUE;
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`LBUX: IsLoad = TRUE;
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`LCX: IsLoad = TRUE;
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`LCUX: IsLoad = TRUE;
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`LHX: IsLoad = TRUE;
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`LHUX: IsLoad = TRUE;
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`LWX: IsLoad = TRUE;
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`LVBX: IsLoad = TRUE;
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`LVBUX: IsLoad = TRUE;
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`LVCX: IsLoad = TRUE;
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`LVCUX: IsLoad = TRUE;
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`LVHX: IsLoad = TRUE;
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`LVHUX: IsLoad = TRUE;
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`LVWX: IsLoad = TRUE;
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`LWRX: IsLoad = TRUE;
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`LVX: IsLoad = TRUE;
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default: IsLoad = FALSE;
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endcase
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robfinch |
else
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IsLoad = FALSE;
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`LB: IsLoad = TRUE;
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`LBU: IsLoad = TRUE;
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`Lx: IsLoad = TRUE;
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`LxU: IsLoad = TRUE;
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`LWR: IsLoad = TRUE;
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`LV: IsLoad = TRUE;
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`LVx: IsLoad = TRUE;
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default: IsLoad = FALSE;
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endcase
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endfunction
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robfinch |
function IsVolatileLoad;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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`MEMNDX:
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if (isn[`INSTRUCTION_L2]==2'b00)
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case(isn[`INSTRUCTION_S2])
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`LWRX: IsVolatileLoad = TRUE;
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`LVBX: IsVolatileLoad = TRUE;
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`LVBUX: IsVolatileLoad = TRUE;
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`LVCX: IsVolatileLoad = TRUE;
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`LVCUX: IsVolatileLoad = TRUE;
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`LVHX: IsVolatileLoad = TRUE;
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`LVHUX: IsVolatileLoad = TRUE;
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`LVWX: IsVolatileLoad = TRUE;
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default: IsVolatileLoad = FALSE;
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endcase
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else
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IsVolatileLoad = FALSE;
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`LWR: IsVolatileLoad = TRUE;
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`LVx: IsVolatileLoad = TRUE;
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default: IsVolatileLoad = FALSE;
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endcase
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endfunction
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function IsStore;
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input [47:0] isn;
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case(isn[`INSTRUCTION_OP])
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`MEMNDX:
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if (isn[`INSTRUCTION_L2]==2'b00)
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case(isn[`INSTRUCTION_S2])
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`SBX: IsStore = TRUE;
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`SCX: IsStore = TRUE;
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`SHX: IsStore = TRUE;
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`SWX: IsStore = TRUE;
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`SWCX: IsStore = TRUE;
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`SVX: IsStore = TRUE;
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`CASX: IsStore = TRUE;
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`INC: IsStore = TRUE;
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default: IsStore = FALSE;
|
| 331 |
|
|
endcase
|
| 332 |
|
|
else
|
| 333 |
|
|
IsStore = FALSE;
|
| 334 |
|
|
`SB: IsStore = TRUE;
|
| 335 |
|
|
`Sx: IsStore = TRUE;
|
| 336 |
|
|
`SWC: IsStore = TRUE;
|
| 337 |
|
|
`INC: IsStore = TRUE;
|
| 338 |
|
|
`SV: IsStore = TRUE;
|
| 339 |
|
|
`CAS: IsStore = TRUE;
|
| 340 |
|
|
`AMO: IsStore = TRUE;
|
| 341 |
|
|
default: IsStore = FALSE;
|
| 342 |
|
|
endcase
|
| 343 |
|
|
endfunction
|
| 344 |
|
|
|
| 345 |
48 |
robfinch |
function [0:0] IsMem;
|
| 346 |
|
|
input [47:0] isn;
|
| 347 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 348 |
|
|
`MEMNDX: IsMem = TRUE;
|
| 349 |
|
|
`AMO: IsMem = TRUE;
|
| 350 |
|
|
`LB: IsMem = TRUE;
|
| 351 |
|
|
`LBU: IsMem = TRUE;
|
| 352 |
|
|
`Lx: IsMem = TRUE;
|
| 353 |
|
|
`LxU: IsMem = TRUE;
|
| 354 |
|
|
`LWR: IsMem = TRUE;
|
| 355 |
|
|
`LV,`SV: IsMem = TRUE;
|
| 356 |
|
|
`INC: IsMem = TRUE;
|
| 357 |
|
|
`SB: IsMem = TRUE;
|
| 358 |
|
|
`Sx: IsMem = TRUE;
|
| 359 |
|
|
`SWC: IsMem = TRUE;
|
| 360 |
|
|
`CAS: IsMem = TRUE;
|
| 361 |
|
|
`LVx: IsMem = TRUE;
|
| 362 |
|
|
default: IsMem = FALSE;
|
| 363 |
|
|
endcase
|
| 364 |
|
|
endfunction
|
| 365 |
|
|
|
| 366 |
|
|
function IsMemNdx;
|
| 367 |
|
|
input [47:0] isn;
|
| 368 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 369 |
|
|
`MEMNDX: IsMemNdx = TRUE;
|
| 370 |
|
|
default: IsMemNdx = FALSE;
|
| 371 |
|
|
endcase
|
| 372 |
|
|
endfunction
|
| 373 |
|
|
|
| 374 |
50 |
robfinch |
function [2:0] MemSize;
|
| 375 |
|
|
input [47:0] isn;
|
| 376 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 377 |
|
|
`MEMNDX:
|
| 378 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| 379 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 380 |
|
|
`LVBX,`LVBUX: MemSize = byt;
|
| 381 |
|
|
`LBX,`LBUX,`SBX: MemSize = byt;
|
| 382 |
|
|
`LVCX,`LVCUX: MemSize = wyde;
|
| 383 |
|
|
`LCX,`LCUX,`SCX: MemSize = wyde;
|
| 384 |
|
|
`LVHX,`LVHUX: MemSize = tetra;
|
| 385 |
|
|
`LHX,`SHX: MemSize = tetra;
|
| 386 |
|
|
`LHUX: MemSize = tetra;
|
| 387 |
|
|
`LVWX: MemSize = octa;
|
| 388 |
|
|
`LWX,`SWX: MemSize = octa;
|
| 389 |
|
|
`LWRX,`SWCX: MemSize = octa;
|
| 390 |
|
|
`LVX,`SVX: MemSize = octa;
|
| 391 |
|
|
`LVx:
|
| 392 |
|
|
case(isn[25:23])
|
| 393 |
|
|
3'd0,3'd1: MemSize = byt;
|
| 394 |
|
|
3'd2,3'd3: MemSize = wyde;
|
| 395 |
|
|
3'd4,3'd5: MemSize = tetra;
|
| 396 |
|
|
default: MemSize = octa;
|
| 397 |
|
|
endcase
|
| 398 |
|
|
default: MemSize = octa;
|
| 399 |
|
|
endcase
|
| 400 |
|
|
else
|
| 401 |
|
|
MemSize = octa;
|
| 402 |
|
|
`LB,`LBU,`SB: MemSize = byt;
|
| 403 |
|
|
`Lx,`LxU,`Sx,`LVx:
|
| 404 |
|
|
casez(isn[20:18])
|
| 405 |
|
|
3'b100: MemSize = octa;
|
| 406 |
|
|
3'b?10: MemSize = tetra;
|
| 407 |
|
|
3'b??1: MemSize = wyde;
|
| 408 |
|
|
default: MemSize = octa;
|
| 409 |
|
|
endcase
|
| 410 |
|
|
`LWR,`SWC: MemSize = octa;
|
| 411 |
|
|
`LV,`SV: MemSize = octa;
|
| 412 |
|
|
`AMO:
|
| 413 |
|
|
case(isn[23:21])
|
| 414 |
|
|
3'd0: MemSize = byt;
|
| 415 |
|
|
3'd1: MemSize = wyde;
|
| 416 |
|
|
3'd2: MemSize = tetra;
|
| 417 |
|
|
3'd3: MemSize = octa;
|
| 418 |
|
|
default: MemSize = octa;
|
| 419 |
|
|
endcase
|
| 420 |
|
|
default: MemSize = octa;
|
| 421 |
|
|
endcase
|
| 422 |
|
|
endfunction
|
| 423 |
|
|
|
| 424 |
48 |
robfinch |
function IsCAS;
|
| 425 |
|
|
input [47:0] isn;
|
| 426 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 427 |
|
|
`MEMNDX:
|
| 428 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| 429 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 430 |
|
|
`CASX: IsCAS = TRUE;
|
| 431 |
|
|
default: IsCAS = FALSE;
|
| 432 |
|
|
endcase
|
| 433 |
|
|
else
|
| 434 |
|
|
IsCAS = FALSE;
|
| 435 |
|
|
`CAS: IsCAS = TRUE;
|
| 436 |
|
|
default: IsCAS = FALSE;
|
| 437 |
|
|
endcase
|
| 438 |
|
|
endfunction
|
| 439 |
|
|
|
| 440 |
|
|
function IsAMO;
|
| 441 |
|
|
input [47:0] isn;
|
| 442 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 443 |
|
|
`AMO: IsAMO = TRUE;
|
| 444 |
|
|
default: IsAMO = FALSE;
|
| 445 |
|
|
endcase
|
| 446 |
|
|
endfunction
|
| 447 |
|
|
|
| 448 |
|
|
function IsInc;
|
| 449 |
|
|
input [47:0] isn;
|
| 450 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 451 |
|
|
`MEMNDX:
|
| 452 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| 453 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 454 |
|
|
`INC: IsInc = TRUE;
|
| 455 |
|
|
default: IsInc = FALSE;
|
| 456 |
|
|
endcase
|
| 457 |
|
|
else
|
| 458 |
|
|
IsInc = FALSE;
|
| 459 |
|
|
`INC: IsInc = TRUE;
|
| 460 |
|
|
default: IsInc = FALSE;
|
| 461 |
|
|
endcase
|
| 462 |
|
|
endfunction
|
| 463 |
|
|
|
| 464 |
|
|
function IsSync;
|
| 465 |
|
|
input [47:0] isn;
|
| 466 |
|
|
IsSync = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`SYNC);
|
| 467 |
|
|
endfunction
|
| 468 |
|
|
|
| 469 |
|
|
function IsFSync;
|
| 470 |
|
|
input [47:0] isn;
|
| 471 |
|
|
IsFSync = (isn[`INSTRUCTION_OP]==`FLOAT && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`FSYNC);
|
| 472 |
|
|
endfunction
|
| 473 |
|
|
|
| 474 |
|
|
function IsMemdb;
|
| 475 |
|
|
input [47:0] isn;
|
| 476 |
|
|
IsMemdb = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMDB);
|
| 477 |
|
|
endfunction
|
| 478 |
|
|
|
| 479 |
|
|
function IsMemsb;
|
| 480 |
|
|
input [47:0] isn;
|
| 481 |
|
|
IsMemsb = (isn[`INSTRUCTION_OP]==`RR && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`R1 && isn[22:18]==`MEMSB);
|
| 482 |
|
|
endfunction
|
| 483 |
|
|
|
| 484 |
|
|
function IsSEI;
|
| 485 |
|
|
input [47:0] isn;
|
| 486 |
|
|
IsSEI = (isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_L2]==2'b00 && isn[`INSTRUCTION_S2]==`SEI);
|
| 487 |
|
|
endfunction
|
| 488 |
|
|
|
| 489 |
|
|
function IsShift48;
|
| 490 |
|
|
input [47:0] isn;
|
| 491 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 492 |
|
|
`R2:
|
| 493 |
|
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
| 494 |
|
|
case(isn[47:42])
|
| 495 |
|
|
`SHIFTR: IsShift48 = TRUE;
|
| 496 |
|
|
default: IsShift48 = FALSE;
|
| 497 |
|
|
endcase
|
| 498 |
|
|
else
|
| 499 |
|
|
IsShift48 = FALSE;
|
| 500 |
|
|
default: IsShift48 = FALSE;
|
| 501 |
|
|
endcase
|
| 502 |
|
|
endfunction
|
| 503 |
|
|
|
| 504 |
|
|
function IsLWRX;
|
| 505 |
|
|
input [47:0] isn;
|
| 506 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 507 |
|
|
`MEMNDX:
|
| 508 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| 509 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 510 |
|
|
`LWRX: IsLWRX = TRUE;
|
| 511 |
|
|
default: IsLWRX = FALSE;
|
| 512 |
|
|
endcase
|
| 513 |
|
|
else
|
| 514 |
|
|
IsLWRX = FALSE;
|
| 515 |
|
|
default: IsLWRX = FALSE;
|
| 516 |
|
|
endcase
|
| 517 |
|
|
endfunction
|
| 518 |
|
|
|
| 519 |
|
|
// Aquire / release bits are only available on indexed SWC / LWR
|
| 520 |
|
|
function IsSWCX;
|
| 521 |
|
|
input [47:0] isn;
|
| 522 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 523 |
|
|
`MEMNDX:
|
| 524 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| 525 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 526 |
|
|
`SWCX: IsSWCX = TRUE;
|
| 527 |
|
|
default: IsSWCX = FALSE;
|
| 528 |
|
|
endcase
|
| 529 |
|
|
else
|
| 530 |
|
|
IsSWCX = FALSE;
|
| 531 |
|
|
default: IsSWCX = FALSE;
|
| 532 |
|
|
endcase
|
| 533 |
|
|
endfunction
|
| 534 |
|
|
|
| 535 |
|
|
function IsJmp;
|
| 536 |
|
|
input [47:0] isn;
|
| 537 |
51 |
robfinch |
IsJmp = isn[`INSTRUCTION_OP]==`JMP;// && isn[7]==1'b0;
|
| 538 |
48 |
robfinch |
endfunction
|
| 539 |
|
|
|
| 540 |
|
|
// Really IsPredictableBranch
|
| 541 |
|
|
// Does not include BccR's
|
| 542 |
|
|
function IsBranch;
|
| 543 |
|
|
input [47:0] isn;
|
| 544 |
|
|
casez(isn[`INSTRUCTION_OP])
|
| 545 |
|
|
`Bcc: IsBranch = TRUE;
|
| 546 |
|
|
`BBc: IsBranch = TRUE;
|
| 547 |
|
|
`BEQI: IsBranch = TRUE;
|
| 548 |
|
|
`CHK: IsBranch = TRUE;
|
| 549 |
|
|
default: IsBranch = FALSE;
|
| 550 |
|
|
endcase
|
| 551 |
|
|
endfunction
|
| 552 |
|
|
|
| 553 |
51 |
robfinch |
function IsJAL;
|
| 554 |
|
|
input [47:0] isn;
|
| 555 |
|
|
IsJAL = isn[`INSTRUCTION_OP]==`JAL;// && isn[7]==1'b0;
|
| 556 |
|
|
endfunction
|
| 557 |
|
|
|
| 558 |
|
|
function IsRet;
|
| 559 |
|
|
input [47:0] isn;
|
| 560 |
|
|
IsRet = isn[`INSTRUCTION_OP]==`RET;// && isn[7]==1'b0;
|
| 561 |
|
|
endfunction
|
| 562 |
|
|
|
| 563 |
|
|
function IsIrq;
|
| 564 |
|
|
input [47:0] isn;
|
| 565 |
|
|
IsIrq = isn[`INSTRUCTION_OP]==`BRK /*&& isn[`INSTRUCTION_L2]==2'b00*/ && isn[23:20]==4'h0;
|
| 566 |
|
|
endfunction
|
| 567 |
|
|
|
| 568 |
48 |
robfinch |
function IsBrk;
|
| 569 |
|
|
input [47:0] isn;
|
| 570 |
51 |
robfinch |
IsBrk = isn[`INSTRUCTION_OP]==`BRK;// && isn[`INSTRUCTION_L2]==2'b00;
|
| 571 |
48 |
robfinch |
endfunction
|
| 572 |
|
|
|
| 573 |
|
|
function IsRti;
|
| 574 |
|
|
input [47:0] isn;
|
| 575 |
51 |
robfinch |
IsRti = isn[`INSTRUCTION_OP]==`RR /*&& isn[`INSTRUCTION_L2]==2'b00*/ && isn[`INSTRUCTION_S2]==`RTI;
|
| 576 |
48 |
robfinch |
endfunction
|
| 577 |
|
|
|
| 578 |
|
|
// Has an extendable 14-bit constant
|
| 579 |
|
|
function HasConst;
|
| 580 |
|
|
input [47:0] isn;
|
| 581 |
|
|
casez(isn[`INSTRUCTION_OP])
|
| 582 |
|
|
`ADDI: HasConst = TRUE;
|
| 583 |
|
|
`SLTI: HasConst = TRUE;
|
| 584 |
|
|
`SLTUI: HasConst = TRUE;
|
| 585 |
|
|
`SGTI: HasConst = TRUE;
|
| 586 |
|
|
`SGTUI: HasConst = TRUE;
|
| 587 |
|
|
`ANDI: HasConst = TRUE;
|
| 588 |
|
|
`ORI: HasConst = TRUE;
|
| 589 |
|
|
`XORI: HasConst = TRUE;
|
| 590 |
|
|
`XNORI: HasConst = TRUE;
|
| 591 |
|
|
`MULUI: HasConst = TRUE;
|
| 592 |
|
|
`MULI: HasConst = TRUE;
|
| 593 |
|
|
`DIVUI: HasConst = TRUE;
|
| 594 |
|
|
`DIVI: HasConst = TRUE;
|
| 595 |
|
|
`MODI: HasConst = TRUE;
|
| 596 |
|
|
`LB: HasConst = TRUE;
|
| 597 |
|
|
`LBU: HasConst = TRUE;
|
| 598 |
|
|
`Lx: HasConst = TRUE;
|
| 599 |
|
|
`LWR: HasConst = TRUE;
|
| 600 |
|
|
`LV: HasConst = TRUE;
|
| 601 |
|
|
`SB: HasConst = TRUE;
|
| 602 |
|
|
`Sx: HasConst = TRUE;
|
| 603 |
|
|
`SWC: HasConst = TRUE;
|
| 604 |
|
|
`INC: HasConst = TRUE;
|
| 605 |
|
|
`SV: HasConst = TRUE;
|
| 606 |
|
|
`CAS: HasConst = TRUE;
|
| 607 |
|
|
`JAL: HasConst = TRUE;
|
| 608 |
|
|
`CALL: HasConst = TRUE;
|
| 609 |
|
|
`RET: HasConst = TRUE;
|
| 610 |
|
|
`LVx: HasConst = TRUE;
|
| 611 |
|
|
default: HasConst = FALSE;
|
| 612 |
|
|
endcase
|
| 613 |
|
|
endfunction
|
| 614 |
|
|
|
| 615 |
50 |
robfinch |
function IsOddball;
|
| 616 |
|
|
input [47:0] instr;
|
| 617 |
|
|
//if (|iqentry_exc[head])
|
| 618 |
|
|
// IsOddball = TRUE;
|
| 619 |
|
|
//else
|
| 620 |
|
|
case(instr[`INSTRUCTION_OP])
|
| 621 |
|
|
`BRK: IsOddball = TRUE;
|
| 622 |
|
|
`IVECTOR:
|
| 623 |
|
|
case(instr[`INSTRUCTION_S2])
|
| 624 |
|
|
`VSxx: IsOddball = TRUE;
|
| 625 |
|
|
default: IsOddball = FALSE;
|
| 626 |
|
|
endcase
|
| 627 |
|
|
`RR:
|
| 628 |
|
|
case(instr[`INSTRUCTION_S2])
|
| 629 |
|
|
`VMOV: IsOddball = TRUE;
|
| 630 |
|
|
`SEI,`RTI: IsOddball = TRUE;
|
| 631 |
|
|
default: IsOddball = FALSE;
|
| 632 |
|
|
endcase
|
| 633 |
|
|
`MEMNDX:
|
| 634 |
|
|
case(instr[`INSTRUCTION_S2])
|
| 635 |
|
|
`CACHEX: IsOddball = TRUE;
|
| 636 |
|
|
default: IsOddball = FALSE;
|
| 637 |
|
|
endcase
|
| 638 |
|
|
`CSRRW,`REX,`CACHE,`FLOAT: IsOddball = TRUE;
|
| 639 |
|
|
default: IsOddball = FALSE;
|
| 640 |
|
|
endcase
|
| 641 |
|
|
endfunction
|
| 642 |
|
|
|
| 643 |
48 |
robfinch |
function IsRFW;
|
| 644 |
|
|
input [47:0] isn;
|
| 645 |
|
|
casez(isn[`INSTRUCTION_OP])
|
| 646 |
|
|
`IVECTOR: IsRFW = TRUE;
|
| 647 |
|
|
`FVECTOR: IsRFW = TRUE;
|
| 648 |
|
|
`R2:
|
| 649 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| 650 |
50 |
robfinch |
case(isn[`INSTRUCTION_S2])
|
| 651 |
|
|
`R1: IsRFW = TRUE;
|
| 652 |
|
|
`ADD: IsRFW = TRUE;
|
| 653 |
|
|
`SUB: IsRFW = TRUE;
|
| 654 |
|
|
`SLT: IsRFW = TRUE;
|
| 655 |
|
|
`SLTU: IsRFW = TRUE;
|
| 656 |
|
|
`SLE: IsRFW = TRUE;
|
| 657 |
|
|
`SLEU: IsRFW = TRUE;
|
| 658 |
|
|
`AND: IsRFW = TRUE;
|
| 659 |
|
|
`OR: IsRFW = TRUE;
|
| 660 |
|
|
`XOR: IsRFW = TRUE;
|
| 661 |
|
|
`MULU: IsRFW = TRUE;
|
| 662 |
|
|
`MULSU: IsRFW = TRUE;
|
| 663 |
|
|
`MUL: IsRFW = TRUE;
|
| 664 |
|
|
`MULUH: IsRFW = TRUE;
|
| 665 |
|
|
`MULSUH: IsRFW = TRUE;
|
| 666 |
|
|
`MULH: IsRFW = TRUE;
|
| 667 |
|
|
`DIVU: IsRFW = TRUE;
|
| 668 |
|
|
`DIVSU: IsRFW = TRUE;
|
| 669 |
|
|
`DIV:IsRFW = TRUE;
|
| 670 |
|
|
`MODU: IsRFW = TRUE;
|
| 671 |
|
|
`MODSU: IsRFW = TRUE;
|
| 672 |
|
|
`MOD:IsRFW = TRUE;
|
| 673 |
|
|
`MOV: IsRFW = TRUE;
|
| 674 |
|
|
`VMOV: IsRFW = TRUE;
|
| 675 |
|
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
| 676 |
|
|
IsRFW = TRUE;
|
| 677 |
|
|
`MIN,`MAX: IsRFW = TRUE;
|
| 678 |
|
|
`SEI: IsRFW = TRUE;
|
| 679 |
|
|
default: IsRFW = FALSE;
|
| 680 |
|
|
endcase
|
| 681 |
48 |
robfinch |
else
|
| 682 |
|
|
IsRFW = FALSE;
|
| 683 |
|
|
`MEMNDX:
|
| 684 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| 685 |
50 |
robfinch |
case(isn[`INSTRUCTION_S2])
|
| 686 |
|
|
`LBX: IsRFW = TRUE;
|
| 687 |
|
|
`LBUX: IsRFW = TRUE;
|
| 688 |
|
|
`LCX: IsRFW = TRUE;
|
| 689 |
|
|
`LCUX: IsRFW = TRUE;
|
| 690 |
|
|
`LHX: IsRFW = TRUE;
|
| 691 |
|
|
`LHUX: IsRFW = TRUE;
|
| 692 |
|
|
`LWX: IsRFW = TRUE;
|
| 693 |
|
|
`LVBX: IsRFW = TRUE;
|
| 694 |
|
|
`LVBUX: IsRFW = TRUE;
|
| 695 |
|
|
`LVCX: IsRFW = TRUE;
|
| 696 |
|
|
`LVCUX: IsRFW = TRUE;
|
| 697 |
|
|
`LVHX: IsRFW = TRUE;
|
| 698 |
|
|
`LVHUX: IsRFW = TRUE;
|
| 699 |
|
|
`LVWX: IsRFW = TRUE;
|
| 700 |
|
|
`LWX: IsRFW = TRUE;
|
| 701 |
|
|
`LWRX: IsRFW = TRUE;
|
| 702 |
|
|
`LVX: IsRFW = TRUE;
|
| 703 |
|
|
`CASX: IsRFW = TRUE;
|
| 704 |
|
|
default: IsRFW = FALSE;
|
| 705 |
|
|
endcase
|
| 706 |
48 |
robfinch |
else
|
| 707 |
|
|
IsRFW = FALSE;
|
| 708 |
|
|
`BBc:
|
| 709 |
|
|
case(isn[20:19])
|
| 710 |
|
|
`IBNE: IsRFW = TRUE;
|
| 711 |
|
|
`DBNZ: IsRFW = TRUE;
|
| 712 |
|
|
default: IsRFW = FALSE;
|
| 713 |
|
|
endcase
|
| 714 |
|
|
`BITFIELD: IsRFW = TRUE;
|
| 715 |
|
|
`ADDI: IsRFW = TRUE;
|
| 716 |
|
|
`SLTI: IsRFW = TRUE;
|
| 717 |
|
|
`SLTUI: IsRFW = TRUE;
|
| 718 |
|
|
`SGTI: IsRFW = TRUE;
|
| 719 |
|
|
`SGTUI: IsRFW = TRUE;
|
| 720 |
|
|
`ANDI: IsRFW = TRUE;
|
| 721 |
|
|
`ORI: IsRFW = TRUE;
|
| 722 |
|
|
`XORI: IsRFW = TRUE;
|
| 723 |
|
|
`MULUI: IsRFW = TRUE;
|
| 724 |
|
|
`MULI: IsRFW = TRUE;
|
| 725 |
|
|
`DIVUI: IsRFW = TRUE;
|
| 726 |
|
|
`DIVI: IsRFW = TRUE;
|
| 727 |
|
|
`MODI: IsRFW = TRUE;
|
| 728 |
|
|
`JAL: IsRFW = TRUE;
|
| 729 |
|
|
`CALL: IsRFW = TRUE;
|
| 730 |
|
|
`RET: IsRFW = TRUE;
|
| 731 |
|
|
`LB: IsRFW = TRUE;
|
| 732 |
|
|
`LBU: IsRFW = TRUE;
|
| 733 |
|
|
`Lx: IsRFW = TRUE;
|
| 734 |
|
|
`LWR: IsRFW = TRUE;
|
| 735 |
|
|
`LV: IsRFW = TRUE;
|
| 736 |
|
|
`LVx: IsRFW = TRUE;
|
| 737 |
|
|
`CAS: IsRFW = TRUE;
|
| 738 |
|
|
`AMO: IsRFW = TRUE;
|
| 739 |
|
|
`CSRRW: IsRFW = TRUE;
|
| 740 |
|
|
default: IsRFW = FALSE;
|
| 741 |
|
|
endcase
|
| 742 |
|
|
endfunction
|
| 743 |
|
|
|
| 744 |
|
|
// Determines which lanes of the target register get updated.
|
| 745 |
|
|
function [7:0] fnWe;
|
| 746 |
|
|
input [47:0] isn;
|
| 747 |
|
|
casez(isn[`INSTRUCTION_OP])
|
| 748 |
|
|
`R2:
|
| 749 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 750 |
|
|
`R1:
|
| 751 |
|
|
case(isn[22:18])
|
| 752 |
|
|
`ABS,`CNTLZ,`CNTLO,`CNTPOP:
|
| 753 |
|
|
case(isn[25:23])
|
| 754 |
|
|
3'b000: fnWe = 8'h01;
|
| 755 |
|
|
3'b001: fnWe = 8'h03;
|
| 756 |
|
|
3'b010: fnWe = 8'h0F;
|
| 757 |
|
|
3'b011: fnWe = 8'hFF;
|
| 758 |
|
|
default: fnWe = 8'hFF;
|
| 759 |
|
|
endcase
|
| 760 |
|
|
default: fnWe = 8'hFF;
|
| 761 |
|
|
endcase
|
| 762 |
|
|
`SHIFT31: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
| 763 |
|
|
`SHIFT63: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
| 764 |
|
|
`SLT,`SLTU,`SLE,`SLEU,
|
| 765 |
|
|
`ADD,`SUB,
|
| 766 |
|
|
`AND,`OR,`XOR,
|
| 767 |
|
|
`NAND,`NOR,`XNOR,
|
| 768 |
50 |
robfinch |
`DIV,`DIVU,`DIVSU,
|
| 769 |
|
|
`MOD,`MODU,`MODSU,
|
| 770 |
|
|
`MUL,`MULU,`MULSU,
|
| 771 |
|
|
`MULH,`MULUH,`MULSUH:
|
| 772 |
48 |
robfinch |
case(isn[25:23])
|
| 773 |
|
|
3'b000: fnWe = 8'h01;
|
| 774 |
|
|
3'b001: fnWe = 8'h03;
|
| 775 |
|
|
3'b010: fnWe = 8'h0F;
|
| 776 |
|
|
3'b011: fnWe = 8'hFF;
|
| 777 |
|
|
default: fnWe = 8'hFF;
|
| 778 |
|
|
endcase
|
| 779 |
|
|
default: fnWe = 8'hFF;
|
| 780 |
|
|
endcase
|
| 781 |
|
|
default: fnWe = 8'hFF;
|
| 782 |
|
|
endcase
|
| 783 |
|
|
endfunction
|
| 784 |
|
|
|
| 785 |
|
|
// Detect if a source is automatically valid
|
| 786 |
|
|
function Source1Valid;
|
| 787 |
|
|
input [47:0] isn;
|
| 788 |
|
|
casez(isn[`INSTRUCTION_OP])
|
| 789 |
|
|
`BRK: Source1Valid = TRUE;
|
| 790 |
|
|
`Bcc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 791 |
|
|
`BBc: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 792 |
|
|
`BEQI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 793 |
|
|
`CHK: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 794 |
|
|
`R2: case(isn[`INSTRUCTION_S2])
|
| 795 |
|
|
`SHIFT31: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 796 |
|
|
`SHIFT63: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 797 |
|
|
`SHIFTR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 798 |
|
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 799 |
|
|
endcase
|
| 800 |
|
|
`MEMNDX: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 801 |
|
|
`ADDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 802 |
|
|
`SLTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 803 |
|
|
`SLTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 804 |
|
|
`SGTI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 805 |
|
|
`SGTUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 806 |
|
|
`ANDI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 807 |
|
|
`ORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 808 |
|
|
`XORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 809 |
|
|
`XNORI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 810 |
|
|
`MULUI: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 811 |
|
|
`AMO: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 812 |
|
|
`LB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 813 |
|
|
`LBU: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 814 |
|
|
`Lx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 815 |
|
|
`LxU: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 816 |
|
|
`LWR: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 817 |
|
|
`LV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 818 |
|
|
`LVx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 819 |
|
|
`SB: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 820 |
|
|
`Sx: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 821 |
|
|
`SWC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 822 |
|
|
`SV: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 823 |
|
|
`INC: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 824 |
|
|
`CAS: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 825 |
|
|
`JAL: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 826 |
|
|
`RET: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 827 |
|
|
`CSRRW: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 828 |
|
|
`BITFIELD: case(isn[31:28])
|
| 829 |
|
|
`BFINSI: Source1Valid = TRUE;
|
| 830 |
|
|
default: Source1Valid = isn[`INSTRUCTION_RA]==5'd0;
|
| 831 |
|
|
endcase
|
| 832 |
|
|
`IVECTOR:
|
| 833 |
|
|
Source1Valid = FALSE;
|
| 834 |
|
|
default: Source1Valid = TRUE;
|
| 835 |
|
|
endcase
|
| 836 |
|
|
endfunction
|
| 837 |
|
|
|
| 838 |
|
|
function Source2Valid;
|
| 839 |
|
|
input [47:0] isn;
|
| 840 |
|
|
casez(isn[`INSTRUCTION_OP])
|
| 841 |
|
|
`BRK: Source2Valid = TRUE;
|
| 842 |
|
|
`Bcc: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 843 |
|
|
`BBc: Source2Valid = TRUE;
|
| 844 |
|
|
`BEQI: Source2Valid = TRUE;
|
| 845 |
|
|
`CHK: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 846 |
|
|
`R2: case(isn[`INSTRUCTION_S2])
|
| 847 |
|
|
`R1: Source2Valid = TRUE;
|
| 848 |
|
|
`SHIFTR: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
| 849 |
|
|
`SHIFT31: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
| 850 |
|
|
`SHIFT63: Source2Valid = isn[25] ? 1'b1 : isn[`INSTRUCTION_RB]==5'd0;
|
| 851 |
|
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 852 |
|
|
endcase
|
| 853 |
|
|
`MEMNDX: case(isn[`INSTRUCTION_S2])
|
| 854 |
|
|
`LVX,`SVX: Source2Valid = FALSE;
|
| 855 |
|
|
default: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 856 |
|
|
endcase
|
| 857 |
|
|
`ADDI: Source2Valid = TRUE;
|
| 858 |
|
|
`SLTI: Source2Valid = TRUE;
|
| 859 |
|
|
`SLTUI: Source2Valid = TRUE;
|
| 860 |
|
|
`SGTI: Source2Valid = TRUE;
|
| 861 |
|
|
`SGTUI: Source2Valid = TRUE;
|
| 862 |
|
|
`ANDI: Source2Valid = TRUE;
|
| 863 |
|
|
`ORI: Source2Valid = TRUE;
|
| 864 |
|
|
`XORI: Source2Valid = TRUE;
|
| 865 |
|
|
`XNORI: Source2Valid = TRUE;
|
| 866 |
|
|
`MULUI: Source2Valid = TRUE;
|
| 867 |
|
|
`LB: Source2Valid = TRUE;
|
| 868 |
|
|
`LBU: Source2Valid = TRUE;
|
| 869 |
|
|
`Lx: Source2Valid = TRUE;
|
| 870 |
|
|
`LxU: Source2Valid = TRUE;
|
| 871 |
|
|
`LWR: Source2Valid = TRUE;
|
| 872 |
|
|
`LVx: Source2Valid = TRUE;
|
| 873 |
|
|
`INC: Source2Valid = TRUE;
|
| 874 |
|
|
`SB: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 875 |
|
|
`Sx: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 876 |
|
|
`SWC: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 877 |
|
|
`CAS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 878 |
|
|
`JAL: Source2Valid = TRUE;
|
| 879 |
|
|
`RET: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 880 |
|
|
`IVECTOR:
|
| 881 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 882 |
|
|
`VABS: Source2Valid = TRUE;
|
| 883 |
|
|
`VMAND,`VMOR,`VMXOR,`VMXNOR,`VMPOP:
|
| 884 |
|
|
Source2Valid = FALSE;
|
| 885 |
|
|
`VADDS,`VSUBS,`VANDS,`VORS,`VXORS:
|
| 886 |
|
|
Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 887 |
|
|
`VBITS2V: Source2Valid = TRUE;
|
| 888 |
|
|
`V2BITS: Source2Valid = isn[`INSTRUCTION_RB]==5'd0;
|
| 889 |
|
|
`VSHL,`VSHR,`VASR: Source2Valid = isn[22:21]==2'd2;
|
| 890 |
|
|
default: Source2Valid = FALSE;
|
| 891 |
|
|
endcase
|
| 892 |
|
|
`LV: Source2Valid = TRUE;
|
| 893 |
|
|
`SV: Source2Valid = FALSE;
|
| 894 |
|
|
`AMO: Source2Valid = isn[31] || isn[`INSTRUCTION_RB]==5'd0;
|
| 895 |
|
|
default: Source2Valid = TRUE;
|
| 896 |
|
|
endcase
|
| 897 |
|
|
endfunction
|
| 898 |
|
|
|
| 899 |
|
|
function Source3Valid;
|
| 900 |
|
|
input [47:0] isn;
|
| 901 |
|
|
case(isn[`INSTRUCTION_OP])
|
| 902 |
|
|
`IVECTOR:
|
| 903 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 904 |
|
|
`VEX: Source3Valid = TRUE;
|
| 905 |
|
|
default: Source3Valid = TRUE;
|
| 906 |
|
|
endcase
|
| 907 |
|
|
`CHK: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
| 908 |
|
|
`R2:
|
| 909 |
|
|
if (isn[`INSTRUCTION_L2]==2'b01)
|
| 910 |
|
|
case(isn[47:42])
|
| 911 |
|
|
`CMOVEZ,`CMOVNZ: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
| 912 |
|
|
default: Source3Valid = TRUE;
|
| 913 |
|
|
endcase
|
| 914 |
|
|
else
|
| 915 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 916 |
|
|
`MAJ: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
| 917 |
|
|
default: Source3Valid = TRUE;
|
| 918 |
|
|
endcase
|
| 919 |
|
|
`MEMNDX:
|
| 920 |
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| 921 |
|
|
case(isn[`INSTRUCTION_S2])
|
| 922 |
|
|
`SBX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
| 923 |
|
|
`SCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
| 924 |
|
|
`SHX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
| 925 |
|
|
`SWX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
| 926 |
|
|
`SWCX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
| 927 |
|
|
`CASX: Source3Valid = isn[`INSTRUCTION_RC]==5'd0;
|
| 928 |
|
|
default: Source3Valid = TRUE;
|
| 929 |
|
|
endcase
|
| 930 |
|
|
default: Source3Valid = TRUE;
|
| 931 |
|
|
endcase
|
| 932 |
|
|
endfunction
|
| 933 |
|
|
|
| 934 |
52 |
robfinch |
`ifdef REGISTER_DECODE
|
| 935 |
48 |
robfinch |
always @(posedge clk)
|
| 936 |
52 |
robfinch |
`else
|
| 937 |
|
|
always @*
|
| 938 |
|
|
`endif
|
| 939 |
48 |
robfinch |
begin
|
| 940 |
51 |
robfinch |
bus <= 144'h0;
|
| 941 |
|
|
bus[`IB_CONST] <= instr[6]==1'b1 ? {{34{instr[47]}},instr[47:18]} :
|
| 942 |
|
|
{{50{instr[31]}},instr[31:18]};
|
| 943 |
48 |
robfinch |
case(instr[7:6])
|
| 944 |
|
|
2'b00: bus[`IB_LN] <= 3'd4;
|
| 945 |
|
|
2'b01: bus[`IB_LN] <= 3'd6;
|
| 946 |
|
|
default: bus[`IB_LN] <= 3'd2;
|
| 947 |
|
|
endcase
|
| 948 |
|
|
// bus[`IB_RT] <= fnRt(instr,ven,vl,thrd) | {thrd,7'b0};
|
| 949 |
|
|
// bus[`IB_RC] <= fnRc(instr,ven,thrd) | {thrd,7'b0};
|
| 950 |
|
|
// bus[`IB_RA] <= fnRa(instr,ven,vl,thrd) | {thrd,7'b0};
|
| 951 |
|
|
bus[`IB_IMM] <= HasConst(instr);
|
| 952 |
50 |
robfinch |
// bus[`IB_A3V] <= Source3Valid(instr);
|
| 953 |
|
|
// bus[`IB_A2V] <= Source2Valid(instr);
|
| 954 |
|
|
// bus[`IB_A1V] <= Source1Valid(instr);
|
| 955 |
51 |
robfinch |
bus[`IB_IRQ] <= IsIrq(instr);
|
| 956 |
|
|
bus[`IB_BRK] <= IsBrk(instr);
|
| 957 |
|
|
bus[`IB_RTI] <= IsRti(instr);
|
| 958 |
|
|
bus[`IB_RET] <= IsRet(instr);
|
| 959 |
|
|
bus[`IB_JAL] <= IsJAL(instr);
|
| 960 |
48 |
robfinch |
bus[`IB_BT] <= (IsBranch(instr) && predict_taken);
|
| 961 |
|
|
bus[`IB_ALU] <= IsALU;
|
| 962 |
|
|
bus[`IB_ALU0] <= IsAlu0Only(instr);
|
| 963 |
|
|
bus[`IB_FPU] <= IsFPU(instr);
|
| 964 |
|
|
bus[`IB_FC] <= IsFlowCtrl;
|
| 965 |
|
|
bus[`IB_CANEX] <= fnCanException(instr);
|
| 966 |
50 |
robfinch |
bus[`IB_LOADV] <= IsVolatileLoad(instr);
|
| 967 |
48 |
robfinch |
bus[`IB_LOAD] <= IsLoad(instr);
|
| 968 |
|
|
bus[`IB_PRELOAD] <= IsLoad(instr) && Rt==5'd0;
|
| 969 |
50 |
robfinch |
bus[`IB_STORE] <= IsStore(instr);
|
| 970 |
|
|
bus[`IB_ODDBALL] <= IsOddball(instr);
|
| 971 |
|
|
bus[`IB_MEMSZ] <= MemSize(instr);
|
| 972 |
48 |
robfinch |
bus[`IB_MEM] <= IsMem(instr);
|
| 973 |
|
|
bus[`IB_MEMNDX] <= IsMemNdx(instr);
|
| 974 |
|
|
bus[`IB_RMW] <= IsCAS(instr) || IsAMO(instr) || IsInc(instr);
|
| 975 |
|
|
bus[`IB_MEMDB] <= IsMemdb(instr);
|
| 976 |
|
|
bus[`IB_MEMSB] <= IsMemsb(instr);
|
| 977 |
|
|
bus[`IB_SHFT48] <= IsShift48(instr);
|
| 978 |
|
|
bus[`IB_SEI] <= IsSEI(instr);
|
| 979 |
|
|
bus[`IB_AQ] <= (IsAMO(instr)|IsLWRX(instr)|IsSWCX(instr)) & instr[25];
|
| 980 |
|
|
bus[`IB_RL] <= (IsAMO(instr)|IsLWRX(instr)|IsSWCX(instr)) & instr[24];
|
| 981 |
|
|
bus[`IB_JMP] <= IsJmp(instr);
|
| 982 |
|
|
bus[`IB_BR] <= IsBranch(instr);
|
| 983 |
|
|
bus[`IB_SYNC] <= IsSync(instr)||IsBrk(instr)||IsRti(instr);
|
| 984 |
|
|
bus[`IB_FSYNC] <= IsFSync(instr);
|
| 985 |
|
|
bus[`IB_RFW] <= Rt==5'd0 ? 1'b0 : IsRFW(instr);
|
| 986 |
|
|
bus[`IB_WE] <= fnWe(instr);
|
| 987 |
|
|
id_o <= id_i;
|
| 988 |
|
|
idv_o <= idv_i;
|
| 989 |
|
|
end
|
| 990 |
|
|
|
| 991 |
|
|
endmodule
|
| 992 |
|
|
|
| 993 |
|
|
module mIsALU(instr, IsALU);
|
| 994 |
|
|
input [47:0] instr;
|
| 995 |
|
|
output reg IsALU;
|
| 996 |
|
|
parameter TRUE = 1'b1;
|
| 997 |
|
|
parameter FALSE = 1'b0;
|
| 998 |
|
|
|
| 999 |
|
|
always @*
|
| 1000 |
|
|
casez(instr[`INSTRUCTION_OP])
|
| 1001 |
50 |
robfinch |
`R2:
|
| 1002 |
|
|
if (instr[`INSTRUCTION_L2]==2'b00)
|
| 1003 |
|
|
case(instr[`INSTRUCTION_S2])
|
| 1004 |
|
|
`VMOV: IsALU = TRUE;
|
| 1005 |
|
|
`RTI: IsALU = FALSE;
|
| 1006 |
|
|
default: IsALU = TRUE;
|
| 1007 |
|
|
endcase
|
| 1008 |
|
|
else
|
| 1009 |
|
|
IsALU = TRUE;
|
| 1010 |
48 |
robfinch |
`BRK: IsALU = FALSE;
|
| 1011 |
|
|
`Bcc: IsALU = FALSE;
|
| 1012 |
|
|
`BBc: IsALU = FALSE;
|
| 1013 |
|
|
`BEQI: IsALU = FALSE;
|
| 1014 |
|
|
`CHK: IsALU = FALSE;
|
| 1015 |
|
|
`JAL: IsALU = FALSE;
|
| 1016 |
|
|
`JMP: IsALU = FALSE;
|
| 1017 |
|
|
`CALL: IsALU = FALSE;
|
| 1018 |
|
|
`RET: IsALU = FALSE;
|
| 1019 |
|
|
`FVECTOR:
|
| 1020 |
50 |
robfinch |
case(instr[`INSTRUCTION_S2])
|
| 1021 |
|
|
`VSHL,`VSHR,`VASR: IsALU = TRUE;
|
| 1022 |
|
|
default: IsALU = FALSE; // Integer
|
| 1023 |
|
|
endcase
|
| 1024 |
48 |
robfinch |
`IVECTOR:
|
| 1025 |
50 |
robfinch |
case(instr[`INSTRUCTION_S2])
|
| 1026 |
|
|
`VSHL,`VSHR,`VASR: IsALU = TRUE;
|
| 1027 |
|
|
default: IsALU = TRUE; // Integer
|
| 1028 |
|
|
endcase
|
| 1029 |
48 |
robfinch |
`FLOAT: IsALU = FALSE;
|
| 1030 |
|
|
default: IsALU = TRUE;
|
| 1031 |
|
|
endcase
|
| 1032 |
|
|
|
| 1033 |
|
|
endmodule
|
