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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// FT64_pit.v
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// - programmable interval timer
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Reg Description
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// 00 current count (read only)
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// 04 max count (read-write)
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// 08 on time (read-write)
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// 0C control
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// byte 0 for counter 0, byte 1 for counter 1, byte 2 for counter 2
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// bit in byte
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// 0 = 1 = load, automatically clears
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// 1 = 1 = enable counting, 0 = disable counting
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// 2 = 1 = auto-reload on terminal count, 0 = no reload
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// 3 = 1 = use external clock, 0 = internal clk_i
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// 4 = 1 = use gate to enable count, 0 = ignore gate
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// 10 current count 1
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// 14 max count 1
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// 18 on time 1
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// 20 current count 2
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// 24 max count 2
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// 28 on time 2
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//
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// - all three counter controls can be written at the same time with a
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// single instruction allowing synchronization of the counters.
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// ============================================================================
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//
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module FT64_pit(rst_i, clk_i, cs_i, cyc_i, stb_i, ack_o, sel_i, we_i, adr_i, dat_i, dat_o,
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clk0, gate0, out0, clk1, gate1, out1, clk2, gate2, out2
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);
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input rst_i;
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input clk_i;
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input cs_i;
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input cyc_i;
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input stb_i;
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output ack_o;
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input [3:0] sel_i;
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input we_i;
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input [5:0] adr_i;
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input [31:0] dat_i;
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output reg [31:0] dat_o;
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input clk0;
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input gate0;
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output out0;
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input clk1;
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input gate1;
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output out1;
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input clk2;
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input gate2;
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output out2;
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integer n;
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reg [31:0] maxcount [0:2];
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reg [31:0] count [0:2];
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reg [31:0] ont [0:2];
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wire [2:0] gate;
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wire [2:0] pulse;
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reg ld [0:2];
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reg ce [0:2];
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reg ar [0:2];
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reg ge [0:2];
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reg xc [0:2];
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reg out [0:2];
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wire cs = cyc_i & stb_i & cs_i;
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reg rdy;
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always @(posedge clk_i)
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rdy <= cs;
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assign ack_o = cs ? (we_i ? 1'b1 : rdy) : 1'b0;
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assign out0 = out[0];
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assign out1 = out[1];
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assign out2 = out[2];
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assign gate[0] = gate0;
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assign gate[1] = gate1;
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assign gate[2] = gate2;
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edge_det ued0 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(clk0), .pe(pulse[0]), .ne());
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edge_det ued1 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(clk1), .pe(pulse[1]), .ne());
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edge_det ued2 (.rst(rst_i), .clk(clk_i), .ce(1'b1), .i(clk2), .pe(pulse[2]), .ne());
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always @(posedge clk_i)
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if (rst_i) begin
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for (n = 0; n < 3; n = n + 1) begin
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ld[n] <= 1'b0;
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ce[n] <= 1'b0;
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ar[n] <= 1'b1;
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ge[n] <= 1'b0;
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out[n] <= 1'b0;
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end
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end
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else begin
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for (n = 0; n < 3; n = n + 1) begin
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ld[n] <= 1'b0;
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if (cs && we_i && adr_i[5:4]==n)
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case(adr_i[3:2])
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2'd1: maxcount[n] <= dat_i;
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2'd2: ont[n] <= dat_i;
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2'd3: begin
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if (sel_i[0]) begin
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ld[0] <= dat_i[0];
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ce[0] <= dat_i[1];
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ar[0] <= dat_i[2];
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xc[0] <= dat_i[3];
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ge[0] <= dat_i[4];
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end
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if (sel_i[1]) begin
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ld[1] <= dat_i[8];
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ce[1] <= dat_i[9];
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ar[1] <= dat_i[10];
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xc[1] <= dat_i[11];
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ge[1] <= dat_i[12];
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end
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if (sel_i[2]) begin
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ld[2] <= dat_i[16];
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ce[2] <= dat_i[17];
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ar[2] <= dat_i[18];
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xc[2] <= dat_i[19];
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ge[2] <= dat_i[20];
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end
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end
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endcase
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if (adr_i[5:4]==n)
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case(adr_i[3:2])
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2'd0: dat_o <= count[n];
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2'd1: dat_o <= maxcount[n];
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2'd2: dat_o <= ont[n];
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2'd3: dat_o <= {ge[2],xc[2],ar[2],ce[2],4'b0,ge[1],xc[1],ar[1],ce[1],4'b0,ge[0],xc[0],ar[0],ce[0],1'b0};
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endcase
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if (ld[n])
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count[n] <= maxcount[n];
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else if ((xc[n] ? pulse[n] & ce[n] : ce[n]) & (ge[n] ? gate[n] : 1'b1)) begin
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count[n] <= count[n] - 32'd1;
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if (count[n]==ont[n])
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out[n] <= 1'b1;
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else if (count[n]==32'd0) begin
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out[n] <= 1'b0;
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if (ar[n])
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count[n] <= maxcount[n];
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else
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ce[n] <= 1'b0;
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end
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end
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end
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end
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endmodule
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