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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_shift.v] - Blame information for rev 48

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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2016-2018  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      FT64_shift.v
//              
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
// ============================================================================
//
//`ifndef SHL
`define IVECTOR  6'h01
`define VSHL        6'h0C
`define VSHR        6'h0D
`define VASR        6'h0E
`define RR      6'h02
`define SHIFTR  6'h2F
`define SHIFT31 6'h0F
`define SHIFT63 6'h1F
`define AMO             6'h2F
`define AMOSHL          6'h0C
`define AMOSHR          6'h0D
`define AMOASR          6'h0E
`define AMOROL          6'h0F
`define AMOSHLI         6'h2C
`define AMOSHRI         6'h2D
`define AMOASRI         6'h2E
`define AMOROLI         6'h2F
`define SHL     3'h0
`define SHR     3'h1
`define ASL     3'h2
`define ASR     3'h3
`define ROL     3'h4
`define ROR     3'h5
//`endif
`define HIGHWORD    127:64
 
module FT64_shift(instr, a, b, res, ov);
parameter DMSB=63;
parameter SUP_VECTOR = 1;
input [47:0] instr;
input [DMSB:0] a;
input [DMSB:0] b;
output [DMSB:0] res;
reg [DMSB:0] res;
output ov;
parameter ROTATE_INSN = 1;
 
wire [5:0] opcode = instr[5:0];
wire [5:0] func = instr[31:26];
wire [2:0] shiftop = instr[25:23];
 
wire [127:0] shl = {64'd0,a} << b[5:0];
wire [127:0] shr = {a,64'd0} >> b[5:0];
 
assign ov = shl[127:64] != {64{a[63]}};
 
always @*
case(opcode)
`IVECTOR:
    if (SUP_VECTOR)
        case(func)
        `VSHL:      res <= shl[DMSB:0];
        `VSHR:      res <= shr[`HIGHWORD];
        `VASR:      if (a[DMSB])
                        res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
                    else
                        res <= shr[`HIGHWORD];
        default:    res <= 64'd0;
        endcase
    else
        res <= 64'd0;
`RR:
    case(func)
    `SHIFTR:
        case(shiftop)
        `SHL,`ASL:      res <= shl[DMSB:0];
        `SHR:   res <= shr[`HIGHWORD];
        `ASR:   if (a[DMSB])
                    res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
                else
                    res <= shr[`HIGHWORD];
        `ROL:   res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
        `ROR:   res <= ROTATE_INSN ? shr[63:0]|shr[`HIGHWORD] : 64'hDEADDEADDEAD;
        default: res <= 64'd0;
        endcase
    `SHIFT31,
    `SHIFT63:
        case(shiftop)
        `SHL,`ASL:res <= shl[DMSB:0];
        `SHR:   res <= shr[`HIGHWORD];
        `ASR:   if (a[DMSB])
                    res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
                else
                    res <= shr[`HIGHWORD];
        `ROL:   res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
        `ROR:   res <= ROTATE_INSN ? shr[63:0]|shr[`HIGHWORD] : 64'hDEADDEADDEAD;
        default: res <= 64'd0;
        endcase
    default:    res <= 64'd0;
    endcase
`AMO:
        case(func)
        `AMOSHL,`AMOSHLI:       res <= shl[DMSB:0];
        `AMOSHR,`AMOSHRI:       res <= shr[`HIGHWORD];
        `AMOASR,`AMOASRI:       if (a[DMSB])
                                res <= (shr[`HIGHWORD]) | ~({64{1'b1}} >> b[5:0]);
                                else
                                res <= shr[`HIGHWORD];
    `AMOROL:    res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
    `AMOROLI:   res <= ROTATE_INSN ? shl[63:0]|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
        default:        res <= 64'd0;
        endcase
default:        res <= 64'd0;
endcase
 
endmodule
 

Line No.	Rev	Author	Line
1	48	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2016-2018 Robert Finch, Waterloo`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@finitron.ca`
7			`// \|\|`
8			`//`
9			`// FT64_shift.v`
10			`//`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`//`
26			`// ============================================================================`
27			`//`
28			//`ifndef SHL
29			`define IVECTOR 6'h01
30			`define VSHL 6'h0C
31			`define VSHR 6'h0D
32			`define VASR 6'h0E
33			`define RR 6'h02
34			`define SHIFTR 6'h2F
35			`define SHIFT31 6'h0F
36			`define SHIFT63 6'h1F
37			`define AMO 6'h2F
38			`define AMOSHL 6'h0C
39			`define AMOSHR 6'h0D
40			`define AMOASR 6'h0E
41			`define AMOROL 6'h0F
42			`define AMOSHLI 6'h2C
43			`define AMOSHRI 6'h2D
44			`define AMOASRI 6'h2E
45			`define AMOROLI 6'h2F
46			`define SHL 3'h0
47			`define SHR 3'h1
48			`define ASL 3'h2
49			`define ASR 3'h3
50			`define ROL 3'h4
51			`define ROR 3'h5
52			//`endif
53			`define HIGHWORD 127:64
54
55			`module FT64_shift(instr, a, b, res, ov);`
56			`parameter DMSB=63;`
57			`parameter SUP_VECTOR = 1;`
58			`input [47:0] instr;`
59			`input [DMSB:0] a;`
60			`input [DMSB:0] b;`
61			`output [DMSB:0] res;`
62			`reg [DMSB:0] res;`
63			`output ov;`
64			`parameter ROTATE_INSN = 1;`
65
66			`wire [5:0] opcode = instr[5:0];`
67			`wire [5:0] func = instr[31:26];`
68			`wire [2:0] shiftop = instr[25:23];`
69
70			`wire [127:0] shl = {64'd0,a} << b[5:0];`
71			`wire [127:0] shr = {a,64'd0} >> b[5:0];`
72
73			`assign ov = shl[127:64] != {64{a[63]}};`
74
75			`always @*`
76			`case(opcode)`
77			`IVECTOR:
78			`if (SUP_VECTOR)`
79			`case(func)`
80			`VSHL: res <= shl[DMSB:0];
81			`VSHR: res <= shr[`HIGHWORD];
82			`VASR: if (a[DMSB])
83			res <= (shr[`HIGHWORD]) \| ~({64{1'b1}} >> b[5:0]);
84			`else`
85			res <= shr[`HIGHWORD];
86			`default: res <= 64'd0;`
87			`endcase`
88			`else`
89			`res <= 64'd0;`
90			`RR:
91			`case(func)`
92			`SHIFTR:
93			`case(shiftop)`
94			`SHL,`ASL: res <= shl[DMSB:0];
95			`SHR: res <= shr[`HIGHWORD];
96			`ASR: if (a[DMSB])
97			res <= (shr[`HIGHWORD]) \| ~({64{1'b1}} >> b[5:0]);
98			`else`
99			res <= shr[`HIGHWORD];
100			`ROL: res <= ROTATE_INSN ? shl[63:0]\|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
101			`ROR: res <= ROTATE_INSN ? shr[63:0]\|shr[`HIGHWORD] : 64'hDEADDEADDEAD;
102			`default: res <= 64'd0;`
103			`endcase`
104			`SHIFT31,
105			`SHIFT63:
106			`case(shiftop)`
107			`SHL,`ASL:res <= shl[DMSB:0];
108			`SHR: res <= shr[`HIGHWORD];
109			`ASR: if (a[DMSB])
110			res <= (shr[`HIGHWORD]) \| ~({64{1'b1}} >> b[5:0]);
111			`else`
112			res <= shr[`HIGHWORD];
113			`ROL: res <= ROTATE_INSN ? shl[63:0]\|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
114			`ROR: res <= ROTATE_INSN ? shr[63:0]\|shr[`HIGHWORD] : 64'hDEADDEADDEAD;
115			`default: res <= 64'd0;`
116			`endcase`
117			`default: res <= 64'd0;`
118			`endcase`
119			`AMO:
120			`case(func)`
121			`AMOSHL,`AMOSHLI: res <= shl[DMSB:0];
122			`AMOSHR,`AMOSHRI: res <= shr[`HIGHWORD];
123			`AMOASR,`AMOASRI: if (a[DMSB])
124			res <= (shr[`HIGHWORD]) \| ~({64{1'b1}} >> b[5:0]);
125			`else`
126			res <= shr[`HIGHWORD];
127			`AMOROL: res <= ROTATE_INSN ? shl[63:0]\|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
128			`AMOROLI: res <= ROTATE_INSN ? shl[63:0]\|shl[`HIGHWORD] : 64'hDEADDEADDEAD;
129			`default: res <= 64'd0;`
130			`endcase`
131			`default: res <= 64'd0;`
132			`endcase`
133
134			`endmodule`
135

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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_shift.v] - Blame information for rev 48