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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_shiftc.v] - Blame information for rev 48

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`timescale 1ns / 1ps
// ============================================================================
//        __
//   \\__/ o\    (C) 2016-2018  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      FT64_shiftc.v
//              
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
//
// ============================================================================
//
//`ifndef SHL
`define R2      6'h02
`define SHL     3'h0
`define SHR     3'h1
`define ASL     3'h2
`define ASR     3'h3
`define ROL     3'h4
`define ROR     3'h5
//`endif
`define HIGHWORDC    31:16
 
module FT64_shiftc(instr, a, b, res, ov);
parameter DMSB=15;
input [47:0] instr;
input [DMSB:0] a;
input [DMSB:0] b;
output [DMSB:0] res;
reg [DMSB:0] res;
output ov;
parameter ROTATE_INSN = 1;
 
wire [5:0] opcode = instr[5:0];
wire [5:0] func = instr[31:26];
wire [3:0] shiftop = instr[35:33];
wire [3:0] bb = instr[29] ? instr[16:13] : b[3:0];
wire [31:0] shl = {16'd0,a} << bb;
wire [31:0] shr = {a,16'd0} >> bb;
 
assign ov = 1'b0;
 
always @*
case(opcode)
`RR:
  case(shiftop)
  `SHL,`ASL:    res <= shl[DMSB:0];
  `SHR: res <= shr[`HIGHWORDC];
  `ASR: if (a[DMSB])
              res <= (shr[`HIGHWORDC]) | ~({16{1'b1}} >> bb);
          else
              res <= shr[`HIGHWORDC];
  `ROL: res <= ROTATE_INSN ? shl[DMSB:0]|shl[`HIGHWORDC] : 16'hDEAD;
  `ROR: res <= ROTATE_INSN ? shr[DMSB:0]|shr[`HIGHWORDC] : 16'hDEAD;
  default: res <= 16'd0;
  endcase
default:        res <= 16'd0;
endcase
 
endmodule
 

Line No.	Rev	Author	Line
1	48	robfinch	`timescale 1ns / 1ps
2			`// ============================================================================`
3			`// __`
4			`// \\__/ o\ (C) 2016-2018 Robert Finch, Waterloo`
5			`// \ __ / All rights reserved.`
6			`// \/_// robfinch<remove>@finitron.ca`
7			`// \|\|`
8			`//`
9			`// FT64_shiftc.v`
10			`//`
11			`//`
12			`// This source file is free software: you can redistribute it and/or modify`
13			`// it under the terms of the GNU Lesser General Public License as published`
14			`// by the Free Software Foundation, either version 3 of the License, or`
15			`// (at your option) any later version.`
16			`//`
17			`// This source file is distributed in the hope that it will be useful,`
18			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
19			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
20			`// GNU General Public License for more details.`
21			`//`
22			`// You should have received a copy of the GNU General Public License`
23			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
24			`//`
25			`//`
26			`// ============================================================================`
27			`//`
28			//`ifndef SHL
29			`define R2 6'h02
30			`define SHL 3'h0
31			`define SHR 3'h1
32			`define ASL 3'h2
33			`define ASR 3'h3
34			`define ROL 3'h4
35			`define ROR 3'h5
36			//`endif
37			`define HIGHWORDC 31:16
38
39			`module FT64_shiftc(instr, a, b, res, ov);`
40			`parameter DMSB=15;`
41			`input [47:0] instr;`
42			`input [DMSB:0] a;`
43			`input [DMSB:0] b;`
44			`output [DMSB:0] res;`
45			`reg [DMSB:0] res;`
46			`output ov;`
47			`parameter ROTATE_INSN = 1;`
48
49			`wire [5:0] opcode = instr[5:0];`
50			`wire [5:0] func = instr[31:26];`
51			`wire [3:0] shiftop = instr[35:33];`
52			`wire [3:0] bb = instr[29] ? instr[16:13] : b[3:0];`
53			`wire [31:0] shl = {16'd0,a} << bb;`
54			`wire [31:0] shr = {a,16'd0} >> bb;`
55
56			`assign ov = 1'b0;`
57
58			`always @*`
59			`case(opcode)`
60			`RR:
61			`case(shiftop)`
62			`SHL,`ASL: res <= shl[DMSB:0];
63			`SHR: res <= shr[`HIGHWORDC];
64			`ASR: if (a[DMSB])
65			res <= (shr[`HIGHWORDC]) \| ~({16{1'b1}} >> bb);
66			`else`
67			res <= shr[`HIGHWORDC];
68			`ROL: res <= ROTATE_INSN ? shl[DMSB:0]\|shl[`HIGHWORDC] : 16'hDEAD;
69			`ROR: res <= ROTATE_INSN ? shr[DMSB:0]\|shr[`HIGHWORDC] : 16'hDEAD;
70			`default: res <= 16'd0;`
71			`endcase`
72			`default: res <= 16'd0;`
73			`endcase`
74
75			`endmodule`
76

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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_shiftc.v] - Blame information for rev 48