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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [fpUnit/] [fcvtsq.v] - Blame information for rev 51

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// ============================================================================
//        __
//   \\__/ o\    (C) 2006-2016  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      fcvtsq.v
//              - convert single precision to quad precision
//              - zero latency
//              - IEEE 754 representation
//
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//                                                                          
// ============================================================================
 
module fcvtsq(a, o);
parameter WID = 128;
localparam MSB = WID-1;
localparam EMSB = WID==128 ? 14 :
                  WID==96 ? 14 :
                  WID==80 ? 14 :
                  WID==64 ? 10 :
                                  WID==52 ? 10 :
                                  WID==48 ? 11 :
                                  WID==44 ? 10 :
                                  WID==42 ? 10 :
                                  WID==40 ?  9 :
                                  WID==32 ?  7 :
                                  WID==24 ?  6 : 4;
localparam FMSB = WID==128 ? 111 :
                  WID==96 ? 79 :
                  WID==80 ? 63 :
                  WID==64 ? 51 :
                                  WID==52 ? 39 :
                                  WID==48 ? 34 :
                                  WID==44 ? 31 :
                                  WID==42 ? 29 :
                                  WID==40 ? 28 :
                                  WID==32 ? 22 :
                                  WID==24 ? 15 : 9;
input [31:0] a;
output reg [WID-1:0] o;
wire sa;
wire [7:0] xa;
wire [22:0] ma;
wire [23:0] fracta;
wire adn;
wire az;
wire xaInf;
wire xInf;
wire aNan;
 
fpDecomp #(32) u1a (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );
 
 
 
always @*
begin
    o[127] <= a[31];    // sign bit
casex({aNan,aInf,az,adn})
// NaN in, NaN out
4'b1xxx:
    begin
        o[126:111] <= 16'hFFFF;
        o[110:103] <= a[22:15];
        o[14:0] <= a[14:0];
    end
// Infinity in, infinity out
4'bx1xx:
    begin
        o[126:111] <= 16'hFFFF;
        o[110:0] <= 111'b0;
    end
// Zero in, zero out
4'bxx1x:
        o[126:0] <= 127'b0;
// Denormal
4'bxxx1:
    begin
        o[126:111] <= 16'h0000;
        o[110:88] <= ma;
    end
default:
    begin
        o[126:111] <= xa + 16256;
        o[110:88] <= ma;
    end
endcase
end
 
endmodule

Line No.	Rev	Author	Line
1	51	robfinch	`// ============================================================================`
2			`// __`
3			`// \\__/ o\ (C) 2006-2016 Robert Finch, Waterloo`
4			`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@finitron.ca`
6			`// \|\|`
7			`//`
8			`// fcvtsq.v`
9			`// - convert single precision to quad precision`
10			`// - zero latency`
11			`// - IEEE 754 representation`
12			`//`
13			`//`
14			`// This source file is free software: you can redistribute it and/or modify`
15			`// it under the terms of the GNU Lesser General Public License as published`
16			`// by the Free Software Foundation, either version 3 of the License, or`
17			`// (at your option) any later version.`
18			`//`
19			`// This source file is distributed in the hope that it will be useful,`
20			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
21			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
22			`// GNU General Public License for more details.`
23			`//`
24			`// You should have received a copy of the GNU General Public License`
25			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
26			`//`
27			`// ============================================================================`
28
29			`module fcvtsq(a, o);`
30			`parameter WID = 128;`
31			`localparam MSB = WID-1;`
32			`localparam EMSB = WID==128 ? 14 :`
33			`WID==96 ? 14 :`
34			`WID==80 ? 14 :`
35			`WID==64 ? 10 :`
36			`WID==52 ? 10 :`
37			`WID==48 ? 11 :`
38			`WID==44 ? 10 :`
39			`WID==42 ? 10 :`
40			`WID==40 ? 9 :`
41			`WID==32 ? 7 :`
42			`WID==24 ? 6 : 4;`
43			`localparam FMSB = WID==128 ? 111 :`
44			`WID==96 ? 79 :`
45			`WID==80 ? 63 :`
46			`WID==64 ? 51 :`
47			`WID==52 ? 39 :`
48			`WID==48 ? 34 :`
49			`WID==44 ? 31 :`
50			`WID==42 ? 29 :`
51			`WID==40 ? 28 :`
52			`WID==32 ? 22 :`
53			`WID==24 ? 15 : 9;`
54			`input [31:0] a;`
55			`output reg [WID-1:0] o;`
56			`wire sa;`
57			`wire [7:0] xa;`
58			`wire [22:0] ma;`
59			`wire [23:0] fracta;`
60			`wire adn;`
61			`wire az;`
62			`wire xaInf;`
63			`wire xInf;`
64			`wire aNan;`
65
66			`fpDecomp #(32) u1a (.i(a), .sgn(sa), .exp(xa), .man(ma), .fract(fracta), .xz(adn), .vz(az), .xinf(xaInf), .inf(aInf), .nan(aNan) );`
67
68
69
70			`always @*`
71			`begin`
72			`o[127] <= a[31]; // sign bit`
73			`casex({aNan,aInf,az,adn})`
74			`// NaN in, NaN out`
75			`4'b1xxx:`
76			`begin`
77			`o[126:111] <= 16'hFFFF;`
78			`o[110:103] <= a[22:15];`
79			`o[14:0] <= a[14:0];`
80			`end`
81			`// Infinity in, infinity out`
82			`4'bx1xx:`
83			`begin`
84			`o[126:111] <= 16'hFFFF;`
85			`o[110:0] <= 111'b0;`
86			`end`
87			`// Zero in, zero out`
88			`4'bxx1x:`
89			`o[126:0] <= 127'b0;`
90			`// Denormal`
91			`4'bxxx1:`
92			`begin`
93			`o[126:111] <= 16'h0000;`
94			`o[110:88] <= ma;`
95			`end`
96			`default:`
97			`begin`
98			`o[126:111] <= xa + 16256;`
99			`o[110:88] <= ma;`
100			`end`
101			`endcase`
102			`end`
103
104			`endmodule`

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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [fpUnit/] [fcvtsq.v] - Blame information for rev 51