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robfinch |
`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2007-2016 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// fp_cmp_unit.v
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// - floating point comparison unit
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// - parameterized width
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// - IEEE 754 representation
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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module fp_cmp_unit(a, b, o, nanx);
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parameter WID = 32;
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localparam MSB = WID-1;
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localparam EMSB = WID==128 ? 14 :
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WID==96 ? 14 :
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WID==80 ? 14 :
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WID==64 ? 10 :
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WID==52 ? 10 :
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WID==48 ? 11 :
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WID==44 ? 10 :
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WID==42 ? 10 :
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WID==40 ? 9 :
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WID==32 ? 7 :
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WID==24 ? 6 : 4;
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localparam FMSB = WID==128 ? 111 :
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WID==96 ? 79 :
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WID==80 ? 63 :
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WID==64 ? 51 :
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WID==52 ? 39 :
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WID==48 ? 34 :
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WID==44 ? 31 :
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WID==42 ? 29 :
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WID==40 ? 28 :
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WID==32 ? 22 :
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WID==24 ? 15 : 9;
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input [WID-1:0] a, b;
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output [4:0] o;
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reg [4:0] o;
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output nanx;
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// Decompose the operands
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wire sa;
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wire sb;
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wire [EMSB:0] xa;
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wire [EMSB:0] xb;
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wire [FMSB:0] ma;
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wire [FMSB:0] mb;
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wire az, bz;
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wire nan_a, nan_b;
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fp_decomp #(WID) u1(.i(a), .sgn(sa), .exp(xa), .man(ma), .vz(az), .qnan(), .snan(), .nan(nan_a) );
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fp_decomp #(WID) u2(.i(b), .sgn(sb), .exp(xb), .man(mb), .vz(bz), .qnan(), .snan(), .nan(nan_b) );
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wire unordered = nan_a | nan_b;
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wire eq = (az & bz) || (a==b); // special test for zero
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wire gt1 = {xa,ma} > {xb,mb};
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wire lt1 = {xa,ma} < {xb,mb};
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wire lt = sa ^ sb ? sa & !(az & bz): sa ? gt1 : lt1;
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always @(unordered or eq or lt or lt1)
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begin
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o[0] = eq;
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o[1] = lt;
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o[2] = lt|eq;
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o[3] = lt1;
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o[4] = unordered;
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end
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// an unorder comparison will signal a nan exception
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//assign nanx = op!=`FCOR && op!=`FCUN && unordered;
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assign nanx = 1'b0;
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endmodule
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