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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [fpUnit/] [fpdivr2.v] - Blame information for rev 51

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1 51 robfinch 
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      fpdivr2.v
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//    Radix 2 floating point divider primitive
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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module fpdivr2(clk4x, ld, a, b, q, r, done, lzcnt);
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parameter WID = 112;
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parameter RADIX = 2;
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localparam WID1 = WID;//((WID+2)/3)*3;    // make width a multiple of three
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localparam DMSB = WID1-1;
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input clk4x;
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input ld;
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input [WID1-1:0] a;
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input [WID1-1:0] b;
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output reg [WID1*2-1:0] q = 0;
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output reg [WID1-1:0] r = 0;
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output reg done = 1'b0;
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output reg [7:0] lzcnt;
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reg [8:0] cnt;                           // iteration count
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reg [WID1*2-1:0] qi = 0;
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reg [DMSB+1:0] ri = 0;
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wire b0;
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reg gotnz;                                      // got a non-zero bit
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reg done1;
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wire [7:0] maxcnt;
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assign b0 = b <= ri;
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wire [DMSB+1:0] r1 = b0 ? ri - b : ri;
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assign maxcnt = WID1*2;
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// Done pulse for external circuit. Must span over 1 1x clock so that it's
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// recognized.
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always @(posedge clk4x)
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if (ld)
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        done <= 1'b0;
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else if (cnt==9'h1FE)
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        done <= 1'b1;
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else if (cnt==9'h1F7)
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        done <= 1'b0;
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// Internal done pulse
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always @(posedge clk4x)
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begin
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        done1 <= 1'b0;
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        if (ld)
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                done1 <= 1'b0;
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        else if (cnt==9'h1FF)
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                done1 <= 1'b1;
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end
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always @(posedge clk4x)
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if (ld)
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        cnt <= maxcnt;
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else if (cnt != 9'h1F7)
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        cnt <= cnt - 8'd1;
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always @(posedge clk4x)
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if (ld)
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        gotnz <= 1'b0;
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else if (!cnt[8]) begin
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        if (b0)
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                gotnz <= 1'b1;
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end
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wire cnt81;
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delay1 #(1) u1 (clk4x, 1'b1, cnt[8], cnt81);
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always @(posedge clk4x)
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if (ld)
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        lzcnt <= 8'h00;
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else if (!cnt81) begin
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        if (b0==1'b0 && !gotnz)
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                lzcnt <= lzcnt + 8'd1;
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end
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always @(posedge clk4x)
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if (ld)
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    qi <= {3'b0,a,{WID1{1'b0}}};
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else if (!cnt81)
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    qi[WID1*2-1:0] <= {qi[WID1*2-1-1:0],b0};
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always @(posedge clk4x)
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if (ld)
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        ri <= 0;
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else if (!cnt81)
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    ri <= {r1[DMSB:0],qi[WID1*2-1]};
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always @(posedge clk4x)
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if (done1)
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        q <= qi;
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always @(posedge clk4x)
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if (done1)
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        r <= ri;
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endmodule
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