OpenCores
URL https://opencores.org/ocsvn/thor/thor/trunk

Subversion Repositories thor

[/] [thor/] [trunk/] [FT64v5/] [rtl/] [lib/] [ffz.v] - Blame information for rev 48

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 48 robfinch 
 
2 
// Find first zero
3 
module ffz6(i, o);
4 
input [5:0] i;
5 
output reg [2:0] o;
6 
always @*
7 
casex(i)
8 
6'b0xxxxx:  o <= 3'd5;
9 
6'b10xxxx:  o <= 3'd4;
10 
6'b110xxx:  o <= 3'd3;
11 
6'b1110xx:  o <= 3'd2;
12 
6'b11110x:  o <= 3'd1;
13 
6'b111110:  o <= 3'd0;
14 
default:    o <= 3'd7;
15 
endcase
16 
endmodule
17 
 
18 
module ffz12(i, o);
19 
input [11:0] i;
20 
output reg [3:0] o;
21 
 
22 
wire [2:0] o1,o2;
23 
ffz6 u1 (i[11:6],o1);
24 
ffz6 u2 (i[5:0],o2);
25 
always @*
26 
if (o1==3'd7 && o2==3'd7)
27 
    o <= 4'd15;
28 
else if (o1==3'd7)
29 
    o <= o2;
30 
else
31 
    o <= 3'd6 + o1;
32 
 
33 
endmodule
34 
 
35 
module ffz24(i, o);
36 
input [23:0] i;
37 
output reg [4:0] o;
38 
 
39 
wire [3:0] o1,o2;
40 
ffz12 u1 (i[23:12],o1);
41 
ffz12 u2 (i[11:0],o2);
42 
always @*
43 
if (o1==4'd15 && o2==4'd15)
44 
    o <= 5'd31;
45 
else if (o1==4'd15)
46 
    o <= o2;
47 
else
48 
    o <= 4'd12 + o1;
49 
 
50 
endmodule
51 
 
52 
module ffz48(i, o);
53 
input [47:0] i;
54 
output reg [5:0] o;
55 
 
56 
wire [4:0] o1,o2;
57 
ffz24 u1 (i[47:24],o1);
58 
ffz24 u2 (i[23:0],o2);
59 
always @*
60 
if (o1==5'd31 && o2==5'd31)
61 
    o <= 6'd63;
62 
else if (o1==5'd31)
63 
    o <= o2;
64 
else
65 
    o <= 5'd24 + o1;
66 
 
67 
endmodule
68 
 
69 
module ffz96(i, o);
70 
input [95:0] i;
71 
output reg [6:0] o;
72 
 
73 
wire [5:0] o1,o2;
74 
ffz48 u1 (i[95:48],o1);
75 
ffz48 u2 (i[47:0],o2);
76 
always @*
77 
if (o1==6'd63 && o2==6'd63)
78 
    o <= 7'd127;
79 
else if (o1==6'd63)
80 
    o <= o2;
81 
else
82 
    o <= 6'd48 + o1;
83 
 
84 
endmodule
85 
 
86 
// Find last zero
87 
module flz6(i, o);
88 
input [5:0] i;
89 
output reg [2:0] o;
90 
always @*
91 
casex(i)
92 
6'bxxxxx0:  o <= 3'd0;
93 
6'bxxxx01:  o <= 3'd1;
94 
6'bxxx011:  o <= 3'd2;
95 
6'bxx0111:  o <= 3'd3;
96 
6'bx01111:  o <= 3'd4;
97 
6'b011111:  o <= 3'd5;
98 
default:    o <= 3'd7;
99 
endcase
100 
 
101 
endmodule
102 
 
103 
module flz12(i, o);
104 
input [11:0] i;
105 
output reg [3:0] o;
106 
 
107 
wire [2:0] o1,o2;
108 
flz6 u1 (i[11:6],o1);
109 
flz6 u2 (i[5:0],o2);
110 
 
111 
always @*
112 
if (o1==3'd7 && o2==3'd7)
113 
    o <= 4'd15;
114 
else if (o2==3'd7)
115 
    o <= 4'd6 + o1;
116 
else
117 
    o <= o2;
118 
 
119 
endmodule
120 
 
121 
module flz24(i, o);
122 
input [23:0] i;
123 
output reg [4:0] o;
124 
 
125 
wire [3:0] o1,o2;
126 
flz12 u1 (i[23:12],o1);
127 
flz12 u2 (i[11:0],o2);
128 
 
129 
always @*
130 
if (o1==4'd15 && o2==4'd15)
131 
    o <= 5'd31;
132 
else if (o2==4'd15)
133 
    o <= 4'd12 + o1;
134 
else
135 
    o <= o2;
136 
 
137 
endmodule
138 
 
139 
module flz48(i, o);
140 
input [47:0] i;
141 
output reg [5:0] o;
142 
 
143 
wire [4:0] o1,o2;
144 
flz24 u1 (i[47:24],o1);
145 
flz24 u2 (i[23:0],o2);
146 
 
147 
always @*
148 
if (o1==5'd31 && o2==5'd31)
149 
    o <= 6'd63;
150 
else if (o2==5'd31)
151 
    o <= 5'd24 + o1;
152 
else
153 
    o <= o2;
154 
 
155 
endmodule
156 
 
157 
module flz96(i, o);
158 
input [95:0] i;
159 
output reg [6:0] o;
160 
 
161 
wire [5:0] o1,o2;
162 
flz48 u1 (i[95:48],o1);
163 
flz48 u2 (i[47:0],o2);
164 
 
165 
always @*
166 
if (o1==6'd63 && o2==6'd63)
167 
    o <= 7'd127;
168 
else if (o2==6'd63)
169 
    o <= 6'd48 + o1;
170 
else
171 
    o <= o2;
172 
 
173 
endmodule
174 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.