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// ============================================================================

//        __

//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch<remove>@finitron.ca

//       ||

//

//      FT64.v

//      Features include:

//  - 16/32/48 bit instructions

//  - vector instruction set,

//  - SIMD instructions

//  - data width of 64 bits

//      - 32 general purpose registers

//  - 32 floating point registers

//      - 32 vector registers, length 63

//  - powerful branch prediction

//  - branch target buffer (BTB)

//  - return address predictor (RSB)

//  - bus interface unit

//  - instruction and data caches

//  - asynchronous logic loops for issue and branch miss

//    re-written for synchronous operation, not as elegant

//    but required for operation in an FPGA

//      - fine-grained simultaneous multi-threading (SMT)

//

// This source file is free software: you can redistribute it and/or modify 

// it under the terms of the GNU Lesser General Public License as published 

// by the Free Software Foundation, either version 3 of the License, or     

// (at your option) any later version.                                      

//                                                                          

// This source file is distributed in the hope that it will be useful,      

// but WITHOUT ANY WARRANTY; without even the implied warranty of           

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            

// GNU General Public License for more details.                             

//                                                                          

// You should have received a copy of the GNU General Public License        

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

//

// Approx 41,000 LUTs. 66,000 LC's.

// ============================================================================

//

`include "FT64_config.vh"

`include "FT64_defines.vh"

module FT64(hartid, rst, clk_i, clk4x, tm_clk_i, irq_i, vec_i, bte_o, cti_o, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_o, dat_i,

    ol_o, pcr_o, pcr2_o, exv_i, rdv_i, wrv_i, icl_o, sr_o, cr_o, rbi_i, signal_i);

input [63:0] hartid;

input rst;

input clk_i;

input clk4x;

input tm_clk_i;

input [3:0] irq_i;

input [7:0] vec_i;

output reg [1:0] bte_o;

output reg [2:0] cti_o;

output reg cyc_o;

output reg stb_o;

input ack_i;

input err_i;

output reg we_o;

output reg [7:0] sel_o;

output reg [`ABITS] adr_o;

output reg [63:0] dat_o;

input [63:0] dat_i;

output reg [1:0] ol_o;

output [31:0] pcr_o;

output [63:0] pcr2_o;

input exv_i;

input rdv_i;

input wrv_i;

output reg icl_o;

output reg cr_o;

output reg sr_o;

input rbi_i;

input [31:0] signal_i;

parameter TM_CLKFREQ = 20000000;

parameter QENTRIES = `QENTRIES;

parameter RSTPC = 32'hFFFC0100;

parameter BRKPC = 32'hFFFC0000;

`ifdef SUPPORT_SMT

parameter PREGS = 256;   // number of physical registers - 1

parameter AREGS = 256;   // number of architectural registers

`else

parameter PREGS = 128;

parameter AREGS = 128;

`endif

parameter RBIT = 11;

parameter DEBUG = 1'b0;

parameter NMAP = QENTRIES;

parameter BRANCH_PRED = 1'b0;

parameter SUP_TXE = 1'b0;

`ifdef SUPPORT_VECTOR

parameter SUP_VECTOR = 1'b1;

`else

parameter SUP_VECTOR = 1'b0;

`endif

parameter DBW = 64;

parameter ABW = 32;

parameter AMSB = ABW-1;

parameter NTHREAD = 1;

reg [3:0] i;

integer n;

integer j, k;

genvar g;

parameter TRUE = 1'b1;

parameter FALSE = 1'b0;

// Memory access sizes

parameter byt = 3'd0;

parameter wyde = 3'd1;

parameter tetra = 3'd2;

parameter octa = 3'd3;

// IQ states

parameter IQS_IDLE = 2'd0;

parameter IQS_AGEN = 2'd1;

parameter IQS_LDDONE = 2'd2;

parameter IQS_S3 = 2'd3;

wire clk;

//BUFG uclkb1

//(

//      .I(clk_i),

//      .O(clk)

//);

assign clk = clk_i;

wire dc_ack;

wire acki = ack_i|dc_ack;

wire [RBIT:0] Ra0, Ra1, Ra2;

wire [RBIT:0] Rb0, Rb1, Rb2;

wire [RBIT:0] Rc0, Rc1, Rc2;

wire [RBIT:0] Rt0, Rt1, Rt2;

wire [63:0] rfoa0,rfob0,rfoc0,rfoc0a;

wire [63:0] rfoa1,rfob1,rfoc1,rfoc1a;

wire [63:0] rfoa2,rfob2,rfoc2,rfoc2a;

`ifdef SUPPORT_SMT

wire [7:0] Ra0s = {Ra0[7:0]};

wire [7:0] Ra1s = {Ra1[7:0]};

wire [7:0] Ra2s = {Ra2[7:0]};

wire [7:0] Rb0s = {Rb0[7:0]};

wire [7:0] Rb1s = {Rb1[7:0]};

wire [7:0] Rb2s = {Rb2[7:0]};

wire [7:0] Rc0s = {Rc0[7:0]};

wire [7:0] Rc1s = {Rc1[7:0]};

wire [7:0] Rc2s = {Rc2[7:0]};

wire [7:0] Rt0s = {Rt0[7:0]};

wire [7:0] Rt1s = {Rt1[7:0]};

wire [7:0] Rt2s = {Rt2[7:0]};

`else

wire [6:0] Ra0s = {Ra0[7],Ra0[5:0]};

wire [6:0] Ra1s = {Ra1[7],Ra1[5:0]};

wire [6:0] Ra2s = {Ra2[7],Ra2[5:0]};

wire [6:0] Rb0s = {Rb0[7],Rb0[5:0]};

wire [6:0] Rb1s = {Rb1[7],Rb1[5:0]};

wire [6:0] Rb2s = {Rb2[7],Rb2[5:0]};

wire [6:0] Rc0s = {Rc0[7],Rc0[5:0]};

wire [6:0] Rc1s = {Rc1[7],Rc1[5:0]};

wire [6:0] Rc2s = {Rc2[7],Rc2[5:0]};

wire [6:0] Rt0s = {Rt0[7],Rt0[5:0]};

wire [6:0] Rt1s = {Rt1[7],Rt1[5:0]};

wire [6:0] Rt2s = {Rt2[7],Rt2[5:0]};

/*

wire [5:0] Ra0s = {Ra0[5:0]};

wire [5:0] Ra1s = {Ra1[5:0]};

wire [5:0] Rb0s = {Rb0[5:0]};

wire [5:0] Rb1s = {Rb1[5:0]};

wire [5:0] Rc0s = {Rc0[5:0]};

wire [5:0] Rc1s = {Rc1[5:0]};

wire [5:0] Rt0s = {Rt0[5:0]};

wire [5:0] Rt1s = {Rt1[5:0]};

*/

`endif

reg [63:0] ds [0:NTHREAD];

reg [63:0] ss [0:NTHREAD];

reg [63:0] ptrmask [0:NTHREAD];

reg [63:0] ptrkey = "  OBJECT";

reg [63:0] wbrcd;

reg  [PREGS-1:0] rf_v;

reg  [5:0] rf_source[0:AREGS-1];

initial begin

for (n = 0; n < AREGS; n = n + 1)

        rf_source[n] = 6'd0;

end

wire [`ABITS] pc0;

wire [`ABITS] pc1;

wire [`ABITS] pc2;

reg excmiss;

reg [`ABITS] excmisspc;

reg excthrd;

reg exception_set;

reg rdvq;               // accumulated read violation

reg errq;               // accumulated err_i input status

reg exvq;

// Vector

reg [5:0] vqe0, vqe1, vqe2;   // vector element being queued

reg [5:0] vqet0, vqet1, vqet2;

reg [7:0] vl;           // vector length

reg [63:0] vm [0:7];    // vector mask registers

reg [1:0] m2;

reg [31:0] wb_merges;

// CSR's

reg [63:0] cr0;

wire snr = cr0[17];             // sequence number reset

wire dce = cr0[30];     // data cache enable

wire bpe = cr0[32];     // branch predictor enable

wire wbm = cr0[34];

wire ctgtxe = cr0[33];

reg [63:0] pmr;

wire id1_available = pmr[0];

wire id2_available = pmr[1];

wire id3_available = pmr[2];

wire alu0_available = pmr[8];

wire alu1_available = pmr[9];

wire fpu1_available = pmr[16];

wire fpu2_available = pmr[17];

wire mem1_available = pmr[24];

wire mem2_available = pmr[25];

wire mem3_available = pmr[26];

wire fcu_available = pmr[32];

// Simply setting this flag to zero should strip out almost all the logic

// associated SMT.

`ifdef SUPPORT_SMT

wire thread_en = cr0[16];

`else

wire thread_en = 1'b0;

`endif

wire vechain = cr0[18];

reg [7:0] fcu_timeout;

reg [63:0] tick;

reg [63:0] wc_time;

reg [31:0] pcr;

reg [63:0] pcr2;

assign pcr_o = pcr;

assign pcr2_o = pcr2;

reg [63:0] aec;

reg [15:0] cause[0:15];

`ifdef SUPPORT_SMT

reg [`ABITS] epc [0:NTHREAD];

reg [`ABITS] epc0 [0:NTHREAD];

reg [`ABITS] epc1 [0:NTHREAD];

reg [`ABITS] epc2 [0:NTHREAD];

reg [`ABITS] epc3 [0:NTHREAD];

reg [`ABITS] epc4 [0:NTHREAD];

reg [`ABITS] epc5 [0:NTHREAD];

reg [`ABITS] epc6 [0:NTHREAD];

reg [`ABITS] epc7 [0:NTHREAD];

reg [`ABITS] epc8 [0:NTHREAD];                   // exception pc and stack

reg [63:0] mstatus [0:NTHREAD];           // machine status

wire [3:0] im = mstatus[0][3:0];

wire [1:0] ol [0:NTHREAD];

wire [1:0] dl [0:NTHREAD];

assign ol[0] = mstatus[0][5:3];   // operating level

assign dl[0] = mstatus[0][21:20];

wire [7:0] cpl [0:NTHREAD];

assign cpl[0] = mstatus[0][13:6]; // current privilege level

wire [5:0] rgs [0:NTHREAD];

assign rgs[0] = mstatus[0][19:14];

assign ol[1] = mstatus[1][5:3]; // operating level

assign cpl[1] = mstatus[1][13:6];       // current privilege level

assign rgs[1] = mstatus[1][19:14];

assign dl[1] = mstatus[1][21:20];

reg [15:0] ol_stack [0:NTHREAD];

reg [31:0] im_stack [0:NTHREAD];

reg [63:0] pl_stack [0:NTHREAD];

reg [63:0] rs_stack [0:NTHREAD];

reg [63:0] fr_stack [0:NTHREAD];

wire mprv = mstatus[0][55];

wire [5:0] fprgs = mstatus[0][25:20];

//assign ol_o = mprv ? ol_stack[0][2:0] : ol[0];

wire vca = mstatus[0][32];               // vector chaining active

`else

reg [`ABITS] epc ;

reg [`ABITS] epc0 ;

reg [`ABITS] epc1 ;

reg [`ABITS] epc2 ;

reg [`ABITS] epc3 ;

reg [`ABITS] epc4 ;

reg [`ABITS] epc5 ;

reg [`ABITS] epc6 ;

reg [`ABITS] epc7 ;

reg [`ABITS] epc8 ;                     // exception pc and stack

reg [63:0] mstatus ;             // machine status

wire [3:0] im = mstatus[3:0];

wire [1:0] ol ;

wire [1:0] dl;

assign ol = mstatus[5:3];       // operating level

assign dl = mstatus[21:20];

wire [7:0] cpl ;

assign cpl = mstatus[13:6];     // current privilege level

wire [5:0] rgs ;

assign rgs = mstatus[19:14];

reg [15:0] ol_stack ;

reg [31:0] im_stack ;

reg [63:0] pl_stack ;

reg [63:0] rs_stack ;

reg [63:0] fr_stack ;

wire mprv = mstatus[55];

wire [5:0] fprgs = mstatus[25:20];

//assign ol_o = mprv ? ol_stack[2:0] : ol;

wire vca = mstatus[32];         // vector chaining active

`endif

reg [63:0] tcb;

reg [`ABITS] badaddr[0:15];

reg [`ABITS] tvec[0:7];

reg [63:0] sema;

reg [63:0] vm_sema;

reg [63:0] cas;         // compare and swap

reg [63:0] ve_hold;

reg isCAS, isAMO, isInc, isSpt, isRMW;

reg [`QBITS] casid;

reg [`ABITS] sbl, sbu;

reg [4:0] regLR = 5'd29;

reg [2:0] fp_rm;

reg fp_inexe;

reg fp_dbzxe;

reg fp_underxe;

reg fp_overxe;

reg fp_invopxe;

reg fp_giopxe;

reg fp_nsfp = 1'b0;

reg fp_fractie;

reg fp_raz;

reg fp_neg;

reg fp_pos;

reg fp_zero;

reg fp_inf;

reg fp_inex;            // inexact exception

reg fp_dbzx;            // divide by zero exception

reg fp_underx;          // underflow exception

reg fp_overx;           // overflow exception

reg fp_giopx;           // global invalid operation exception

reg fp_sx;                      // summary exception

reg fp_swtx;        // software triggered exception

reg fp_gx;

reg fp_invopx;

reg fp_infzerox;

reg fp_zerozerox;

reg fp_subinfx;

reg fp_infdivx;

reg fp_NaNCmpx;

reg fp_cvtx;

reg fp_sqrtx;

reg fp_snanx;

wire [31:0] fp_status = {

        fp_rm,

        fp_inexe,

        fp_dbzxe,

        fp_underxe,

        fp_overxe,

        fp_invopxe,

        fp_nsfp,

        fp_fractie,

        fp_raz,

        1'b0,

        fp_neg,

        fp_pos,

        fp_zero,

        fp_inf,

        fp_swtx,

        fp_inex,

        fp_dbzx,

        fp_underx,

        fp_overx,

        fp_giopx,

        fp_gx,

        fp_sx,

        fp_cvtx,

        fp_sqrtx,

        fp_NaNCmpx,

        fp_infzerox,

        fp_zerozerox,

        fp_infdivx,

        fp_subinfx,

        fp_snanx

        };

reg [63:0] fpu_csr;

wire [5:0] fp_rgs = fpu_csr[37:32];

//reg [25:0] m[0:8191];

reg  [3:0] panic;                // indexes the message structure

reg [128:0] message [0:15];       // indexed by panic

wire int_commit;

reg StatusHWI;

reg [47:0] insn0, insn1, insn2;

wire [47:0] insn0a, insn1b, insn2b;

reg [47:0] insn1a, insn2a;

// Only need enough bits in the seqnence number to cover the instructions in

// the queue plus an extra count for skipping on branch misses. In this case

// that would be four bits minimum (count 0 to 8). 

reg [31:0] seq_num;

reg [31:0] seq_num1;

reg [31:0] seq_num2;

wire [63:0] rdat0,rdat1,rdat2;

reg [63:0] xdati;

reg canq1, canq2, canq3;

reg queued1;

reg queued2;

reg queued3;

reg queuedNop;

reg [47:0] codebuf[0:63];

reg [QENTRIES-1:0] setpred;

// instruction queue (ROB)

reg [31:0]  iqentry_sn   [0:QENTRIES-1];  // instruction sequence number

reg [QENTRIES-1:0] iqentry_v;                    // entry valid?  -- this should be the first bit

reg [QENTRIES-1:0] iqentry_iv;           // instruction is valid

reg [4:0]  iqentry_is   [0:QENTRIES-1];   // source of instruction

reg [QENTRIES-1:0] iqentry_out;  // instruction has been issued to an ALU ... 

reg [QENTRIES-1:0] iqentry_done; // instruction result valid

reg [QENTRIES-1:0] iqentry_cmt;

reg [QENTRIES-1:0] iqentry_thrd;         // which thread the instruction is in

reg [QENTRIES-1:0] iqentry_pt;           // predict taken

reg [QENTRIES-1:0] iqentry_bt;           // update branch target buffer

reg [QENTRIES-1:0] iqentry_takb; // take branch record

reg [QENTRIES-1:0] iqentry_jal;

reg [QENTRIES-1:0] iqentry_agen; // address-generate ... signifies that address is ready (only for LW/SW)

reg  [1:0] iqentry_state [0:QENTRIES-1];

reg [QENTRIES-1:0] iqentry_alu = 8'h00;  // alu type instruction

reg [QENTRIES-1:0] iqentry_alu0;  // only valid on alu #0

reg [QENTRIES-1:0] iqentry_fpu;  // floating point instruction

reg [QENTRIES-1:0] iqentry_fc;   // flow control instruction

reg [QENTRIES-1:0] iqentry_canex = 8'h00;        // true if it's an instruction that can exception

reg [QENTRIES-1:0] iqentry_oddball = 8'h00;      // writes to register file

reg [QENTRIES-1:0] iqentry_load; // is a memory load instruction

reg [QENTRIES-1:0] iqentry_loadv;        // is a volatile memory load instruction

reg [QENTRIES-1:0] iqentry_store;        // is a memory store instruction

reg [QENTRIES-1:0] iqentry_preload;      // is a memory preload instruction

reg [QENTRIES-1:0] iqentry_ldcmp;

reg [QENTRIES-1:0] iqentry_mem;  // touches memory: 1 if LW/SW

reg [QENTRIES-1:0] iqentry_memndx;  // indexed memory operation 

reg [2:0] iqentry_memsz [0:QENTRIES-1];   // size of memory op

reg [QENTRIES-1:0] iqentry_rmw;  // memory RMW op

reg [QENTRIES-1:0] iqentry_memdb;

reg [QENTRIES-1:0] iqentry_memsb;

reg [QENTRIES-1:0] iqentry_rtop;

reg [QENTRIES-1:0] iqentry_sei;

reg [QENTRIES-1:0] iqentry_aq;   // memory aquire

reg [QENTRIES-1:0] iqentry_rl;   // memory release

reg [QENTRIES-1:0] iqentry_shft48;

reg [QENTRIES-1:0] iqentry_jmp;  // changes control flow: 1 if BEQ/JALR

reg [QENTRIES-1:0] iqentry_br;  // Bcc (for predictor)

reg [QENTRIES-1:0] iqentry_ret;

reg [QENTRIES-1:0] iqentry_irq;

reg [QENTRIES-1:0] iqentry_brk;

reg [QENTRIES-1:0] iqentry_rti;

reg [QENTRIES-1:0] iqentry_sync;  // sync instruction

reg [QENTRIES-1:0] iqentry_fsync;

reg [QENTRIES-1:0] iqentry_rfw = 8'h00;  // writes to register file

reg  [7:0] iqentry_we   [0:QENTRIES-1];   // enable strobe

reg [63:0] iqentry_res   [0:QENTRIES-1];  // instruction result

reg [47:0] iqentry_instr[0:QENTRIES-1];   // instruction opcode

reg  [2:0] iqentry_insln[0:QENTRIES-1]; // instruction length

reg  [7:0] iqentry_exc   [0:QENTRIES-1];  // only for branches ... indicates a HALT instruction

reg [RBIT:0] iqentry_tgt[0:QENTRIES-1];   // Rt field or ZERO -- this is the instruction's target (if any)

reg  [7:0] iqentry_vl   [0:QENTRIES-1];

reg  [5:0] iqentry_ven  [0:QENTRIES-1];  // vector element number

reg [63:0] iqentry_a0    [0:QENTRIES-1];  // argument 0 (immediate)

reg [63:0] iqentry_a1    [0:QENTRIES-1];  // argument 1

reg        iqentry_a1_v [0:QENTRIES-1];  // arg1 valid

reg  [4:0] iqentry_a1_s  [0:QENTRIES-1];  // arg1 source (iq entry # with top bit representing ALU/DRAM bus)

reg [63:0] iqentry_a2    [0:QENTRIES-1];  // argument 2

reg        iqentry_a2_v [0:QENTRIES-1];  // arg2 valid

reg  [4:0] iqentry_a2_s  [0:QENTRIES-1];  // arg2 source (iq entry # with top bit representing ALU/DRAM bus)

reg [63:0] iqentry_a3    [0:QENTRIES-1];  // argument 3

reg        iqentry_a3_v [0:QENTRIES-1];  // arg3 valid

reg  [4:0] iqentry_a3_s  [0:QENTRIES-1];  // arg3 source (iq entry # with top bit representing ALU/DRAM bus)

reg [`ABITS] iqentry_pc [0:QENTRIES-1];  // program counter for this instruction

reg [RBIT:0] iqentry_Ra [0:QENTRIES-1];

reg [RBIT:0] iqentry_Rb [0:QENTRIES-1];

reg [RBIT:0] iqentry_Rc [0:QENTRIES-1];

// debugging

//reg  [4:0] iqentry_ra   [0:7];  // Ra

initial begin

for (n = 0; n < QENTRIES; n = n + 1)

        iqentry_a1_s[n] = 5'd0;

        iqentry_a2_s[n] = 5'd0;

        iqentry_a3_s[n] = 5'd0;

end

reg [QENTRIES-1:0] iqentry_source = {QENTRIES{1'b0}};

reg   [QENTRIES-1:0] iqentry_imm;

reg  [QENTRIES-1:0] iqentry_memready;

reg  [QENTRIES-1:0] iqentry_memopsvalid;

reg  [QENTRIES-1:0] memissue = {QENTRIES{1'b0}};

reg [1:0] missued;