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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [twoway/] [FT64_regfile1w3r_oc.v] - Blame information for rev 57

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1 57 robfinch 
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Register file with two write ports and six read ports.
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// ============================================================================
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//
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`include "FT64_config.vh"
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module FT64_regfileRam_sim(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb);
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parameter WID=64;
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parameter RBIT = 11;
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input clka;
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input ena;
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input [7:0] wea;
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input [RBIT:0] addra;
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input [WID-1:0] dina;
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input clkb;
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input enb;
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input [RBIT:0] addrb;
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output [WID-1:0] doutb;
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integer n;
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(* RAM_STYLE="BLOCK" *)
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reg [64:0] mem [0:4095];
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reg [RBIT:0] raddrb;
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initial begin
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        for (n = 0; n < 4096; n = n + 1)
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                mem[n] = 0;
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end
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always @(posedge clka) if (ena & wea[0]) mem[addra][7:0] <= dina[7:0];
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always @(posedge clka) if (ena & wea[1]) mem[addra][15:8] <= dina[15:8];
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always @(posedge clka) if (ena & wea[2]) mem[addra][23:16] <= dina[23:16];
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always @(posedge clka) if (ena & wea[3]) mem[addra][31:24] <= dina[31:24];
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always @(posedge clka) if (ena & wea[4]) mem[addra][39:32] <= dina[39:32];
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always @(posedge clka) if (ena & wea[5]) mem[addra][47:40] <= dina[47:40];
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always @(posedge clka) if (ena & wea[6]) mem[addra][55:48] <= dina[55:48];
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always @(posedge clka) if (ena & wea[7]) mem[addra][63:56] <= dina[63:56];
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always @(posedge clkb)
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        raddrb <= addrb;
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assign doutb = mem[raddrb];
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endmodule
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module FT64_regfile1w3r_oc(clk, wr0, we0, wa0, i0,
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        rclk, ra0, ra1, ra2, o0, o1, o2);
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parameter WID=64;
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parameter RBIT = 11;
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input clk;
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input wr0;
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input [7:0] we0;
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input [RBIT:0] wa0;
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input [WID-1:0] i0;
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input rclk;
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input [RBIT:0] ra0;
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input [RBIT:0] ra1;
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input [RBIT:0] ra2;
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output [WID-1:0] o0;
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output [WID-1:0] o1;
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output [WID-1:0] o2;
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reg wr;
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reg [RBIT:0] wa;
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reg [WID-1:0] i;
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reg [7:0] we;
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wire [WID-1:0] o00, o01, o02;
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integer n;
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`ifdef SIM
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FT64_regfileRam_sim urf10 (
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  .clka(clk),
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  .ena(wr),
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  .wea(we),
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  .addra(wa),
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  .dina(i),
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  .clkb(rclk),
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  .enb(1'b1),
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  .addrb(ra0),
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  .doutb(o00)
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);
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FT64_regfileRam_sim urf11 (
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  .clka(clk),
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  .ena(wr),
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  .wea(we),
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  .addra(wa),
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  .dina(i),
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  .clkb(rclk),
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  .enb(1'b1),
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  .addrb(ra1),
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  .doutb(o01)
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);
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FT64_regfileRam_sim urf12 (
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  .clka(clk),
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  .ena(wr),
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  .wea(we),
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  .addra(wa),
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  .dina(i),
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  .clkb(rclk),
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  .enb(1'b1),
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  .addrb(ra2),
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  .doutb(o02)
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);
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`else
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FT64_regfileRam urf10 (
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  .clka(clk),
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  .ena(wr),
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  .wea(we),
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  .addra(wa),
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  .dina(i),
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  .clkb(rclk),
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  .enb(1'b1),
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  .web(8'b0),
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  .addrb(ra0),
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  .dinb(64'h00),
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  .doutb(o00)
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);
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FT64_regfileRam urf11 (
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  .clka(clk),
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  .ena(wr),
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  .wea(we),
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  .addra(wa),
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  .dina(i),
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  .clkb(rclk),
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  .enb(1'b1),
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  .web(8'b0),
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  .addrb(ra1),
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  .dinb(64'h00),
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  .doutb(o01)
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);
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FT64_regfileRam urf12 (
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  .clka(clk),
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  .ena(wr),
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  .wea(we),
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  .addra(wa),
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  .dina(i),
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  .clkb(rclk),
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  .enb(1'b1),
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  .web(8'b0),
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  .addrb(ra2),
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  .dinb(64'h00),
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  .doutb(o02)
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);
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`endif
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always @*
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begin
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        wr <= wr0;
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        we <= we0;
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        wa <= wa0;
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        i <= i0;
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end
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assign o0[7:0] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[0] && (ra0==wa0)) ? i0[7:0] : o00[7:0];
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assign o0[15:8] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[1] && (ra0==wa0)) ? i0[15:8] : o00[15:8];
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assign o0[23:16] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[2] && (ra0==wa0)) ? i0[23:16] : o00[23:16];
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assign o0[31:24] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[3] && (ra0==wa0)) ? i0[31:24] : o00[31:24];
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assign o0[39:32] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[4] && (ra0==wa0)) ? i0[39:32] : o00[39:32];
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assign o0[47:40] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[5] && (ra0==wa0)) ? i0[47:40] : o00[47:40];
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assign o0[55:48] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[6] && (ra0==wa0)) ? i0[55:48] : o00[55:48];
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assign o0[63:56] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[7] && (ra0==wa0)) ? i0[63:56] : o00[63:56];
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assign o1[7:0] = ra1[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[0] && (ra1==wa0)) ? i0[7:0] : o01[7:0];
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assign o1[15:8] = ra1[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[1] && (ra1==wa0)) ? i0[15:8] : o01[15:8];
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assign o1[23:16] = ra1[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[2] && (ra1==wa0)) ? i0[23:16] : o01[23:16];
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assign o1[31:24] = ra1[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[3] && (ra1==wa0)) ? i0[31:24] : o01[31:24];
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assign o1[39:32] = ra1[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[4] && (ra1==wa0)) ? i0[39:32] : o01[39:32];
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assign o1[47:40] = ra1[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[5] && (ra1==wa0)) ? i0[47:40] : o01[47:40];
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assign o1[55:48] = ra1[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[6] && (ra1==wa0)) ? i0[55:48] : o01[55:48];
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assign o1[63:56] = ra1[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[7] && (ra1==wa0)) ? i0[63:56] : o01[63:56];
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assign o2[7:0] = ra2[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[0] && (ra2==wa0)) ? i0[7:0] : o02[7:0];
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assign o2[15:8] = ra2[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[1] && (ra2==wa0)) ? i0[15:8] : o02[15:8];
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assign o2[23:16] = ra2[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[2] && (ra2==wa0)) ? i0[23:16] : o02[23:16];
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assign o2[31:24] = ra2[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[3] && (ra2==wa0)) ? i0[31:24] : o02[31:24];
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assign o2[39:32] = ra2[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[4] && (ra2==wa0)) ? i0[39:32] : o02[39:32];
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assign o2[47:40] = ra2[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[5] && (ra2==wa0)) ? i0[47:40] : o02[47:40];
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assign o2[55:48] = ra2[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[6] && (ra2==wa0)) ? i0[55:48] : o02[55:48];
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assign o2[63:56] = ra2[4:0]==5'd0 ? {8{1'b0}} :
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        (wr0 && we0[7] && (ra2==wa0)) ? i0[63:56] : o02[63:56];
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endmodule
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