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`timescale 1ns / 1ps
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// ============================================================================
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// __
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// \\__/ o\ (C) 2013-2018 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Register file with two write ports and six read ports.
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// ============================================================================
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//
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`include "FT64_config.vh"
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module FT64_regfileRam_sim(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb);
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parameter WID=64;
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parameter RBIT = 11;
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input clka;
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input ena;
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input [7:0] wea;
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input [RBIT:0] addra;
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input [WID-1:0] dina;
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input clkb;
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input enb;
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input [RBIT:0] addrb;
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output [WID-1:0] doutb;
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integer n;
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(* RAM_STYLE="BLOCK" *)
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reg [64:0] mem [0:4095];
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reg [RBIT:0] raddrb;
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initial begin
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for (n = 0; n < 4096; n = n + 1)
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mem[n] = 0;
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end
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always @(posedge clka) if (ena & wea[0]) mem[addra][7:0] <= dina[7:0];
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always @(posedge clka) if (ena & wea[1]) mem[addra][15:8] <= dina[15:8];
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always @(posedge clka) if (ena & wea[2]) mem[addra][23:16] <= dina[23:16];
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always @(posedge clka) if (ena & wea[3]) mem[addra][31:24] <= dina[31:24];
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always @(posedge clka) if (ena & wea[4]) mem[addra][39:32] <= dina[39:32];
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always @(posedge clka) if (ena & wea[5]) mem[addra][47:40] <= dina[47:40];
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always @(posedge clka) if (ena & wea[6]) mem[addra][55:48] <= dina[55:48];
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always @(posedge clka) if (ena & wea[7]) mem[addra][63:56] <= dina[63:56];
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always @(posedge clkb)
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raddrb <= addrb;
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assign doutb = mem[raddrb];
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endmodule
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module FT64_regfile2w6r_oc(clk4x, clk, wr0, wr1, we0, we1, wa0, wa1, i0, i1,
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rclk, ra0, ra1, ra2, ra3, ra4, ra5,
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o0, o1, o2, o3, o4, o5);
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parameter WID=64;
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parameter RBIT = 11;
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input clk4x;
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input clk;
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input wr0;
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input wr1;
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input [7:0] we0;
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input [7:0] we1;
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input [RBIT:0] wa0;
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input [RBIT:0] wa1;
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input [WID-1:0] i0;
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input [WID-1:0] i1;
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input rclk;
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input [RBIT:0] ra0;
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input [RBIT:0] ra1;
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input [RBIT:0] ra2;
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input [RBIT:0] ra3;
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input [RBIT:0] ra4;
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input [RBIT:0] ra5;
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output [WID-1:0] o0;
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output [WID-1:0] o1;
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output [WID-1:0] o2;
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output [WID-1:0] o3;
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output [WID-1:0] o4;
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output [WID-1:0] o5;
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reg wr;
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reg [RBIT:0] wa;
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reg [WID-1:0] i;
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reg [7:0] we;
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wire [WID-1:0] o00, o01, o02, o03, o04, o05;
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reg wr1x;
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reg [RBIT:0] wa1x;
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reg [WID-1:0] i1x;
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reg [7:0] we1x;
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integer n;
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`ifdef SIM
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FT64_regfileRam_sim urf10 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.addrb(ra0),
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.doutb(o00)
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);
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FT64_regfileRam_sim urf11 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.addrb(ra1),
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.doutb(o01)
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);
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FT64_regfileRam_sim urf12 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.addrb(ra2),
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.doutb(o02)
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);
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FT64_regfileRam_sim urf13 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.addrb(ra3),
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.doutb(o03)
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);
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FT64_regfileRam_sim urf14 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.addrb(ra4),
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.doutb(o04)
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);
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FT64_regfileRam_sim urf15 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.addrb(ra5),
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.doutb(o05)
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);
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`else
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FT64_regfileRam urf10 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.web(1'b0),
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.addrb(ra0),
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.dinb(8'h00),
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.doutb(o00)
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);
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FT64_regfileRam urf11 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.web(1'b0),
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.addrb(ra1),
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.dinb(8'h00),
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.doutb(o01)
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);
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FT64_regfileRam urf12 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.web(1'b0),
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.addrb(ra2),
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.dinb(8'h00),
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.doutb(o02)
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);
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FT64_regfileRam urf13 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.web(1'b0),
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.addrb(ra3),
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.dinb(8'h00),
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.doutb(o03)
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);
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FT64_regfileRam urf14 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.web(1'b0),
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.addrb(ra4),
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.dinb(8'h00),
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.doutb(o04)
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);
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FT64_regfileRam urf15 (
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.clka(clk4x),
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.ena(wr),
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.wea(we),
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.addra(wa),
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.dina(i),
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.clkb(rclk),
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.enb(1'b1),
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.web(1'b0),
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.addrb(ra5),
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.dinb(8'h00),
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.doutb(o05)
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);
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`endif
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// The same clock edge that would normally update the register file is the
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// clock edge that causes the data to disappear for the next cycle. The
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// data needs to be held onto so that it can update the register file on
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// the next 4x clock.
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always @(posedge clk)
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begin
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wr1x <= wr1;
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we1x <= we1;
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wa1x <= wa1;
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i1x <= i1;
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end
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reg wclk2;
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always @(posedge clk4x)
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begin
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wclk2 <= clk;
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if (clk & ~wclk2) begin
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wr <= wr0;
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we <= we0;
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wa <= wa0;
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i <= i0;
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end
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else if (~clk & wclk2) begin
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wr <= wr1x;
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we <= we1x;
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wa <= wa1x;
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i <= i1x;
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end
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else begin
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wr <= 1'b0;
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we <= 8'h00;
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wa <= 'd0;
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i <= 'd0;
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end
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end
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assign o0[7:0] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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(wr1 && we1[0] && (ra0==wa1)) ? i1[7:0] :
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(wr0 && we0[0] && (ra0==wa0)) ? i0[7:0] : o00[7:0];
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assign o0[15:8] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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(wr1 && we1[1] && (ra0==wa1)) ? i1[15:8] :
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(wr0 && we0[1] && (ra0==wa0)) ? i0[15:8] : o00[15:8];
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assign o0[23:16] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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(wr1 && we1[2] && (ra0==wa1)) ? i1[23:16] :
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(wr0 && we0[2] && (ra0==wa0)) ? i0[23:16] : o00[23:16];
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assign o0[31:24] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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(wr1 && we1[3] && (ra0==wa1)) ? i1[31:24] :
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(wr0 && we0[3] && (ra0==wa0)) ? i0[31:24] : o00[31:24];
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assign o0[39:32] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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(wr1 && we1[4] && (ra0==wa1)) ? i1[39:32] :
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(wr0 && we0[4] && (ra0==wa0)) ? i0[39:32] : o00[39:32];
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assign o0[47:40] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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(wr1 && we1[5] && (ra0==wa1)) ? i1[47:40] :
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(wr0 && we0[5] && (ra0==wa0)) ? i0[47:40] : o00[47:40];
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assign o0[55:48] = ra0[4:0]==5'd0 ? {8{1'b0}} :
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(wr1 && we1[6] && (ra0==wa1)) ? i1[55:48] :
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(wr0 && we0[6] && (ra0==wa0)) ? i0[55:48] : o00[55:48];
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assign o0[63:56] = ra0[4:0]==5'd0 ? {8{1'b0}} :
|
| 323 |
|
|
(wr1 && we1[7] && (ra0==wa1)) ? i1[63:56] :
|
| 324 |
|
|
(wr0 && we0[7] && (ra0==wa0)) ? i0[63:56] : o00[63:56];
|
| 325 |
|
|
|
| 326 |
|
|
assign o1[7:0] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 327 |
|
|
(wr1 && we1[0] && (ra1==wa1)) ? i1[7:0] :
|
| 328 |
|
|
(wr0 && we0[0] && (ra1==wa0)) ? i0[7:0] : o01[7:0];
|
| 329 |
|
|
assign o1[15:8] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 330 |
|
|
(wr1 && we1[1] && (ra1==wa1)) ? i1[15:8] :
|
| 331 |
|
|
(wr0 && we0[1] && (ra1==wa0)) ? i0[15:8] : o01[15:8];
|
| 332 |
|
|
assign o1[23:16] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 333 |
|
|
(wr1 && we1[2] && (ra1==wa1)) ? i1[23:16] :
|
| 334 |
|
|
(wr0 && we0[2] && (ra1==wa0)) ? i0[23:16] : o01[23:16];
|
| 335 |
|
|
assign o1[31:24] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 336 |
|
|
(wr1 && we1[3] && (ra1==wa1)) ? i1[31:24] :
|
| 337 |
|
|
(wr0 && we0[3] && (ra1==wa0)) ? i0[31:24] : o01[31:24];
|
| 338 |
|
|
assign o1[39:32] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 339 |
|
|
(wr1 && we1[4] && (ra1==wa1)) ? i1[39:32] :
|
| 340 |
|
|
(wr0 && we0[4] && (ra1==wa0)) ? i0[39:32] : o01[39:32];
|
| 341 |
|
|
assign o1[47:40] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 342 |
|
|
(wr1 && we1[5] && (ra1==wa1)) ? i1[47:40] :
|
| 343 |
|
|
(wr0 && we0[5] && (ra1==wa0)) ? i0[47:40] : o01[47:40];
|
| 344 |
|
|
assign o1[55:48] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 345 |
|
|
(wr1 && we1[6] && (ra1==wa1)) ? i1[55:48] :
|
| 346 |
|
|
(wr0 && we0[6] && (ra1==wa0)) ? i0[55:48] : o01[55:48];
|
| 347 |
|
|
assign o1[63:56] = ra1[4:0]==5'd0 ? {8{1'b0}} :
|
| 348 |
|
|
(wr1 && we1[7] && (ra1==wa1)) ? i1[63:56] :
|
| 349 |
|
|
(wr0 && we0[7] && (ra1==wa0)) ? i0[63:56] : o01[63:56];
|
| 350 |
|
|
|
| 351 |
|
|
assign o2[7:0] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 352 |
|
|
(wr1 && we1[0] && (ra2==wa1)) ? i1[7:0] :
|
| 353 |
|
|
(wr0 && we0[0] && (ra2==wa0)) ? i0[7:0] : o02[7:0];
|
| 354 |
|
|
assign o2[15:8] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 355 |
|
|
(wr1 && we1[1] && (ra2==wa1)) ? i1[15:8] :
|
| 356 |
|
|
(wr0 && we0[1] && (ra2==wa0)) ? i0[15:8] : o02[15:8];
|
| 357 |
|
|
assign o2[23:16] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 358 |
|
|
(wr1 && we1[2] && (ra2==wa1)) ? i1[23:16] :
|
| 359 |
|
|
(wr0 && we0[2] && (ra2==wa0)) ? i0[23:16] : o02[23:16];
|
| 360 |
|
|
assign o2[31:24] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 361 |
|
|
(wr1 && we1[3] && (ra2==wa1)) ? i1[31:24] :
|
| 362 |
|
|
(wr0 && we0[3] && (ra2==wa0)) ? i0[31:24] : o02[31:24];
|
| 363 |
|
|
assign o2[39:32] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 364 |
|
|
(wr1 && we1[4] && (ra2==wa1)) ? i1[39:32] :
|
| 365 |
|
|
(wr0 && we0[4] && (ra2==wa0)) ? i0[39:32] : o02[39:32];
|
| 366 |
|
|
assign o2[47:40] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 367 |
|
|
(wr1 && we1[5] && (ra2==wa1)) ? i1[47:40] :
|
| 368 |
|
|
(wr0 && we0[5] && (ra2==wa0)) ? i0[47:40] : o02[47:40];
|
| 369 |
|
|
assign o2[55:48] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 370 |
|
|
(wr1 && we1[6] && (ra2==wa1)) ? i1[55:48] :
|
| 371 |
|
|
(wr0 && we0[6] && (ra2==wa0)) ? i0[55:48] : o02[55:48];
|
| 372 |
|
|
assign o2[63:56] = ra2[4:0]==5'd0 ? {8{1'b0}} :
|
| 373 |
|
|
(wr1 && we1[7] && (ra2==wa1)) ? i1[63:56] :
|
| 374 |
|
|
(wr0 && we0[7] && (ra2==wa0)) ? i0[63:56] : o02[63:56];
|
| 375 |
|
|
|
| 376 |
|
|
assign o3[7:0] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 377 |
|
|
(wr1 && we1[0] && (ra3==wa1)) ? i1[7:0] :
|
| 378 |
|
|
(wr0 && we0[0] && (ra3==wa0)) ? i0[7:0] : o03[7:0];
|
| 379 |
|
|
assign o3[15:8] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 380 |
|
|
(wr1 && we1[1] && (ra3==wa1)) ? i1[15:8] :
|
| 381 |
|
|
(wr0 && we0[1] && (ra3==wa0)) ? i0[15:8] : o03[15:8];
|
| 382 |
|
|
assign o3[23:16] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 383 |
|
|
(wr1 && we1[2] && (ra3==wa1)) ? i1[23:16] :
|
| 384 |
|
|
(wr0 && we0[2] && (ra3==wa0)) ? i0[23:16] : o03[23:16];
|
| 385 |
|
|
assign o3[31:24] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 386 |
|
|
(wr1 && we1[3] && (ra3==wa1)) ? i1[31:24] :
|
| 387 |
|
|
(wr0 && we0[3] && (ra3==wa0)) ? i0[31:24] : o03[31:24];
|
| 388 |
|
|
assign o3[39:32] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 389 |
|
|
(wr1 && we1[4] && (ra3==wa1)) ? i1[39:32] :
|
| 390 |
|
|
(wr0 && we0[4] && (ra3==wa0)) ? i0[39:32] : o03[39:32];
|
| 391 |
|
|
assign o3[47:40] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 392 |
|
|
(wr1 && we1[5] && (ra3==wa1)) ? i1[47:40] :
|
| 393 |
|
|
(wr0 && we0[5] && (ra3==wa0)) ? i0[47:40] : o03[47:40];
|
| 394 |
|
|
assign o3[55:48] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 395 |
|
|
(wr1 && we1[6] && (ra3==wa1)) ? i1[55:48] :
|
| 396 |
|
|
(wr0 && we0[6] && (ra3==wa0)) ? i0[55:48] : o03[55:48];
|
| 397 |
|
|
assign o3[63:56] = ra3[4:0]==5'd0 ? {8{1'b0}} :
|
| 398 |
|
|
(wr1 && we1[7] && (ra3==wa1)) ? i1[63:56] :
|
| 399 |
|
|
(wr0 && we0[7] && (ra3==wa0)) ? i0[63:56] : o03[63:56];
|
| 400 |
|
|
|
| 401 |
|
|
assign o4[7:0] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 402 |
|
|
(wr1 && we1[0] && (ra4==wa1)) ? i1[7:0] :
|
| 403 |
|
|
(wr0 && we0[0] && (ra4==wa0)) ? i0[7:0] : o04[7:0];
|
| 404 |
|
|
assign o4[15:8] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 405 |
|
|
(wr1 && we1[1] && (ra4==wa1)) ? i1[15:8] :
|
| 406 |
|
|
(wr0 && we0[1] && (ra4==wa0)) ? i0[15:8] : o04[15:8];
|
| 407 |
|
|
assign o4[23:16] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 408 |
|
|
(wr1 && we1[2] && (ra4==wa1)) ? i1[23:16] :
|
| 409 |
|
|
(wr0 && we0[2] && (ra4==wa0)) ? i0[23:16] : o04[23:16];
|
| 410 |
|
|
assign o4[31:24] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 411 |
|
|
(wr1 && we1[3] && (ra4==wa1)) ? i1[31:24] :
|
| 412 |
|
|
(wr0 && we0[3] && (ra4==wa0)) ? i0[31:24] : o04[31:24];
|
| 413 |
|
|
assign o4[39:32] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 414 |
|
|
(wr1 && we1[4] && (ra4==wa1)) ? i1[39:32] :
|
| 415 |
|
|
(wr0 && we0[4] && (ra4==wa0)) ? i0[39:32] : o04[39:32];
|
| 416 |
|
|
assign o4[47:40] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 417 |
|
|
(wr1 && we1[5] && (ra4==wa1)) ? i1[47:40] :
|
| 418 |
|
|
(wr0 && we0[5] && (ra4==wa0)) ? i0[47:40] : o04[47:40];
|
| 419 |
|
|
assign o4[55:48] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 420 |
|
|
(wr1 && we1[6] && (ra4==wa1)) ? i1[55:48] :
|
| 421 |
|
|
(wr0 && we0[6] && (ra4==wa0)) ? i0[55:48] : o04[55:48];
|
| 422 |
|
|
assign o4[63:56] = ra4[4:0]==5'd0 ? {8{1'b0}} :
|
| 423 |
|
|
(wr1 && we1[7] && (ra4==wa1)) ? i1[63:56] :
|
| 424 |
|
|
(wr0 && we0[7] && (ra4==wa0)) ? i0[63:56] : o04[63:56];
|
| 425 |
|
|
|
| 426 |
|
|
assign o5[7:0] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 427 |
|
|
(wr1 && we1[0] && (ra5==wa1)) ? i1[7:0] :
|
| 428 |
|
|
(wr0 && we0[0] && (ra5==wa0)) ? i0[7:0] : o05[7:0];
|
| 429 |
|
|
assign o5[15:8] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 430 |
|
|
(wr1 && we1[1] && (ra5==wa1)) ? i1[15:8] :
|
| 431 |
|
|
(wr0 && we0[1] && (ra5==wa0)) ? i0[15:8] : o05[15:8];
|
| 432 |
|
|
assign o5[23:16] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 433 |
|
|
(wr1 && we1[2] && (ra5==wa1)) ? i1[23:16] :
|
| 434 |
|
|
(wr0 && we0[2] && (ra5==wa0)) ? i0[23:16] : o05[23:16];
|
| 435 |
|
|
assign o5[31:24] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 436 |
|
|
(wr1 && we1[3] && (ra5==wa1)) ? i1[31:24] :
|
| 437 |
|
|
(wr0 && we0[3] && (ra5==wa0)) ? i0[31:24] : o05[31:24];
|
| 438 |
|
|
assign o5[39:32] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 439 |
|
|
(wr1 && we1[4] && (ra5==wa1)) ? i1[39:32] :
|
| 440 |
|
|
(wr0 && we0[4] && (ra5==wa0)) ? i0[39:32] : o05[39:32];
|
| 441 |
|
|
assign o5[47:40] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 442 |
|
|
(wr1 && we1[5] && (ra5==wa1)) ? i1[47:40] :
|
| 443 |
|
|
(wr0 && we0[5] && (ra5==wa0)) ? i0[47:40] : o05[47:40];
|
| 444 |
|
|
assign o5[55:48] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 445 |
|
|
(wr1 && we1[6] && (ra5==wa1)) ? i1[55:48] :
|
| 446 |
|
|
(wr0 && we0[6] && (ra5==wa0)) ? i0[55:48] : o05[55:48];
|
| 447 |
|
|
assign o5[63:56] = ra5[4:0]==5'd0 ? {8{1'b0}} :
|
| 448 |
|
|
(wr1 && we1[7] && (ra5==wa1)) ? i1[63:56] :
|
| 449 |
|
|
(wr0 && we0[7] && (ra5==wa0)) ? i0[63:56] : o05[63:56];
|
| 450 |
|
|
/*
|
| 451 |
|
|
assign o5 = ra5[4:0]==5'd0 ? {WID{1'b0}} :
|
| 452 |
|
|
(wr1 && (ra5==wa1)) ? i1 :
|
| 453 |
|
|
(wr0 && (ra5==wa0)) ? i0 : o05;
|
| 454 |
|
|
|
| 455 |
|
|
*/
|
| 456 |
|
|
endmodule
|
| 457 |
|
|
|
