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// ============================================================================
//        __
//   \\__/ o\    (C) 2018-2019  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      FT64_ipt.v
//  - 64 bit CPU inverted page table memory management unit
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
// ============================================================================
//
`ifndef TRUE
`define TRUE    1'b1
`define FALSE   1'b0
`endif
//`define BYPASS        1'b1
 
module FT64_ipt(rst, clk, pkeys_i, ol_i, bte_i, cti_i, cs_i, icl_i, cyc_i, stb_i, ack_o, we_i, sel_i, vadr_i, dat_i, dat_o,
        bte_o, cti_o, cyc_o, ack_i, we_o, sel_o, padr_o, exv_o, rdv_o, wrv_o, prv_o, page_fault);
input rst;
input clk;
input [63:0] pkeys_i;
input [1:0] ol_i;
input [1:0] bte_i;
input [2:0] cti_i;
input cs_i;
input icl_i;
input cyc_i;
input stb_i;
output reg ack_o;
input we_i;
input [7:0] sel_i;
input [63:0] vadr_i;
input [63:0] dat_i;
output reg [63:0] dat_o;
output reg [1:0] bte_o;
output reg [2:0] cti_o;
output reg cyc_o;
input ack_i;
output reg we_o;
output reg [7:0] sel_o;
output reg [31:0] padr_o;
output reg exv_o;
output reg rdv_o;
output reg wrv_o;
output reg prv_o;
output reg page_fault;
 
parameter S_IDLE = 4'd0;
parameter S_CMP1 = 4'd1;
parameter S_CMP2 = 4'd2;
parameter S_CMP3 = 4'd3;
parameter S_CMP4 = 4'd4;
parameter S_CMP5 = 4'd5;
parameter S_CMP6 = 4'd6;
parameter S_WAIT1 = 4'd7;
parameter S_ACK = 4'd8;
parameter S_RESET = 4'd9;
 
integer n;
wire [9:0] pkey [0:5];
assign pkey[0] = pkeys_i[9:0];
assign pkey[1] = pkeys_i[19:10];
assign pkey[2] = pkeys_i[29:20];
assign pkey[3] = pkeys_i[39:30];
assign pkey[4] = pkeys_i[49:40];
assign pkey[5] = pkeys_i[59:50];
reg [3:0] state;
reg [15:0] pt_ad;
reg upd;
reg upd_done;
reg probe, probe_done;
reg pte_last;
reg [7:0] pte_asid;
reg [3:0] pte_drwx;
reg [18:0] pte_vadr;
reg [9:0] pte_key;
reg pt_wr;
reg [41:0] pt_dati;
wire [41:0] pt_dat;
 
FT64_iptram uram1 (
  .clka(clk),
  .ena(1'b1),
  .wea(pt_wr),
  .addra(pt_ad),
  .dina(pt_dati),
  .douta(pt_dat)
);
 
wire pt_last = pt_dat[23];
wire [18:0] pt_vadr = pt_dat[22:4];
wire [7:0] pt_asid = pt_dat[31:24];
wire [3:0] pt_drwx = pt_dat[3:0];
wire [9:0] pt_key = pt_dat[41:32];
 
reg keymatch;
always @*
begin
keymatch = ol_i==2'b00;
for (n = 0; n < 6; n = n + 1)
        if (pt_key==pkey[n] || pt_key==10'h0)
                keymatch = 1'b1;
end
 
function [15:0] Hash1;
input [39:0] vadr;
begin
        Hash1 = {1'b0,vadr[37:32],vadr[21:13]};
end
endfunction
 
function [15:0] Hash2;
input [39:0] vadr;
begin
        Hash2 = {1'b1,vadr[37:32],vadr[21:13]};
end
endfunction
 
always @(posedge clk)
        case(vadr_i[5:3])
        3'd1:
                dat_o <= pt_ad;
        3'd2:
                begin
                        dat_o[41:32] <= pte_key;
                        dat_o[31:24] <= pte_asid;
                        dat_o[23] <= pte_last;
                        dat_o[2:0] <= pte_drwx[2:0];
                        dat_o[7] <= pte_drwx[3];
                end
        3'd3:
                dat_o <= pte_vadr;
        default:        dat_o <= 1'b0;
        endcase
 
always @(posedge clk)
        bte_o <= bte_i;
always @(posedge clk)
        cti_o <= cti_i;
always @(posedge clk)
        sel_o <= sel_i;
`ifdef BYPASS
always @(posedge clk)
        cyc_o <= cyc_i;
always @(posedge clk)
        we_o <= we_i;
always @(posedge clk)
        padr_o <= vadr_i[31:0];
always @(posedge clk)
        exv_o <= 1'b0;
always @(posedge clk)
        rdv_o <= 1'b0;
always @(posedge clk)
        wrv_o <= 1'b0;
always @(posedge clk)
        prv_o <= 1'b0;
always @(posedge clk)
        page_fault <= 1'b0;
`else
always @(posedge clk)
if (rst) begin
        cyc_o <= 1'b0;
        padr_o <= 32'hFFFC0100;
        ack_o <= 1'b0;
        exv_o <= 1'b0;
        rdv_o <= 1'b0;
        wrv_o <= 1'b0;
        prv_o <= 1'b0;
        pt_wr <= 1'b1;
        pt_ad <= 1'b0;
        pt_dati <= 1'b0;
        upd <= 1'b0;
        probe <= 1'b0;
        upd_done <= 1'b0;
        probe_done <= 1'b0;
        goto(S_IDLE);
end
else begin
        pt_wr <= 1'b0;
        page_fault <= 1'b0;
        ack_o <= 1'b0;
case(state)
// Clear page table ram on reset.
S_RESET:
        begin
                pt_ad <= pt_ad + 2'd1;
                if (&pt_ad) begin
                        pt_wr <= 1'b0;
                        state <= S_IDLE;
                end
        end
S_IDLE:
        if (cyc_i) begin
                if (cs_i & stb_i) begin
                        ack_o <= 1'b1;
                        case(vadr_i[5:3])
                        3'd0:
                                begin
                                        if (dat_i[0] & !upd_done) begin
                                                pt_ad <= Hash1({pte_asid,pte_vadr});
                                                upd <= 1'b1;
                                                goto(S_CMP1);
                                        end
                                        else if (dat_i[1] & !probe_done) begin
                                                pt_ad <= Hash1({pte_asid,pte_vadr});
                                                probe <= 1'b1;
                                                goto(S_CMP1);
                                        end
                                end
                        3'd2:
                                begin
                                        pte_key  <= dat_i[41:32];
                                        pte_asid <= dat_i[31:24];
                                        pte_last <= dat_i[22];
                                        pte_drwx <= {dat_i[7],dat_i[2:0]};
                                end
                        3'd3:
                                begin
                                        pte_vadr <= dat_i[18:0];
                                end
                        endcase
                end
                else begin
                        upd_done <= 1'b0;
                        probe_done <= 1'b0;
                        upd <= 1'b0;
                        probe <= 1'b0;
                        if (ol_i==2'b0) begin
                                cyc_o <= 1'b1;
                                we_o <= we_i;
                                padr_o <= vadr_i[31:0];
                                goto(S_ACK);
                        end
                        else begin
                                // Video frame buffer ($00xxxxxx) and ROM / IO ($FFxxxxxx) regions are
                                // not mapped.
                                if (vadr_i[31:24]==8'hFF || vadr_i[31:24]==8'h00) begin
                                        cyc_o <= 1'b1;
                                        we_o <= we_i;
                                        padr_o <= vadr_i[31:0];
                                        goto(S_ACK);
                                end
                                else begin
                                        pt_ad <= Hash1({vadr_i[63:56],vadr_i});
                                        goto(S_CMP1);
                                end
                        end
                end
        end
        else begin
                exv_o <= 1'b0;
                rdv_o <= 1'b0;
                wrv_o <= 1'b0;
                prv_o <= 1'b0;
        end
 
S_CMP1:
        goto(S_CMP2);
S_CMP2:
        goto(S_CMP3);
S_CMP3:
        if (pt_drwx[2:0]==3'b0) begin
                if (upd) begin
                        pte_key  <= 10'h0;
                        pte_last <= 1'b0;
                        pte_drwx <= 4'd0;
                        pt_wr <= 1'b1;
                        pt_dati <= {pte_key,pte_asid,pte_last,pte_vadr[18:0],pte_drwx};
                        upd_done <= 1'b1;
                        goto(S_IDLE);
                end
                else if (probe) begin
                        pte_drwx <= 3'b0;
                        pte_vadr <= 19'b0;
                        pte_asid <= 8'b0;
                        pte_last <= 1'b0;
                        pte_key  <= 10'h0;
                        probe_done <= 1'b1;
                        goto(S_IDLE);
                end
                else begin
                        page_fault <= 1'b1;
                        goto(S_WAIT1);
                end
        end
        else if (pt_asid==vadr_i[63:56] && pt_vadr==vadr_i[31:13]) begin
                if (upd) begin
                        if (keymatch) begin
                                pte_key  <= pt_key;
                                pte_last <= pt_last;
                                pte_drwx <= pt_drwx;
                                pt_wr <= 1'b1;
                                pt_dati <= {pte_key,pt_dat[31:4],pte_drwx};
                        end
                        else
                                prv_o <= 1'b1;
                        upd_done <= 1'b1;
                        goto(S_IDLE);
                end
                else if (probe) begin
                        if (keymatch) begin
                                pte_key  <= pt_key;
                                pte_last <= pt_last;
                                pte_drwx <= pt_drwx;
                        end
                        else
                                prv_o <= 1'b1;
                        probe_done <= 1'b1;
                        goto(S_IDLE);
                end
                else if (~ack_i) begin
                        if (keymatch) begin
                                cyc_o <= 1'b1;
                                we_o <= we_i & pt_drwx[1];
                                if (!pt_drwx[1] & we_i) wrv_o <= 1'b1;
                                if (!pt_drwx[2] & ~we_i) rdv_o <= 1'b1;
                                if (!pt_drwx[0] & icl_i) exv_o <= 1'b1;
                                padr_o <= {pt_ad,vadr_i[12:0]};
                        end
                        else begin
                                cyc_o <= 1'b1;
                                we_o <= 1'b0;
                                padr_o <= 32'hFFFFFFF8;
                                prv_o <= 1'b1;
                        end
                        goto(S_ACK);
                end
        end
        else begin
                if (upd|probe)
                        pt_ad <= Hash2({pte_asid,pte_vadr});
                else
                        pt_ad <= Hash2({vadr_i[63:56],vadr_i});
                goto(S_CMP4);
        end
 
S_CMP4:
        goto(S_CMP5);
S_CMP5:
        goto(S_CMP6);
S_CMP6:
        if (pt_drwx[2:0]==3'b0) begin
                if (upd) begin
                        pte_key  <= 10'h0;
                        pte_last <= 1'b0;
                        pte_drwx <= 4'd0;
                        pt_wr <= 1'b1;
                        pt_dati <= {pte_key,pte_asid,pte_last,pte_vadr[18:0],pte_drwx};
                        upd_done <= 1'b1;
                        goto(S_IDLE);
                end
                else if (probe) begin
                        pte_key  <= 10'h0;
                        pte_drwx <= 43'b0;
                        pte_vadr <= 19'b0;
                        pte_asid <= 8'b0;
                        pte_last <= 1'b0;
                        probe_done <= 1'b1;
                        goto(S_IDLE);
                end
                else begin
                        page_fault <= 1'b1;
                        goto(S_WAIT1);
                end
        end
        else if (pt_asid==vadr_i[63:56] && pt_vadr==vadr_i[31:13]) begin
                if (upd) begin
                        if (keymatch) begin
                                pte_key  <= pt_key;
                                pte_last <= pt_last;
                                pte_drwx <= pt_drwx;
                                pt_wr <= 1'b1;
                                pt_dati <= {pte_key,pt_dat[31:4],pte_drwx};
                        end
                        else
                                prv_o <= 1'b1;
                        upd_done <= 1'b1;
                        goto(S_IDLE);
                end
                else if (probe) begin
                        if (keymatch) begin
                                pte_key  <= pt_key;
                                pte_last <= pt_last;
                                pte_drwx <= pt_drwx;
                                probe_done <= 1'b1;
                        end
                        else
                                prv_o <= 1'b1;
                        goto(S_IDLE);
                end
                else if (~ack_i) begin
                        if (keymatch) begin
                                cyc_o <= 1'b1;
                                we_o <= we_i & pt_drwx[1];
                                if (!pt_drwx[1] & we_i) wrv_o <= 1'b1;
                                if (!pt_drwx[2] & ~we_i) rdv_o <= 1'b1;
                                if (!pt_drwx[0] & icl_i) exv_o <= 1'b1;
                                padr_o <= {pt_ad,vadr_i[12:0]};
                        end
                        else begin
                                cyc_o <= 1'b1;
                                we_o <= 1'b0;
                                padr_o <= 32'hFFFFFFF8;
                                prv_o <= 1'b1;
                        end
                        goto(S_ACK);
                end
        end
        else begin
                pt_ad <= {pt_ad+8'd65};
                goto(S_CMP4);
        end
 
// Wait a clock cycle for a page fault to register.
S_WAIT1:
        goto(S_IDLE);
 
S_ACK:
        if (ack_i) begin
                if (cti_i==3'b000 || cti_i==3'b111) begin
                        cyc_o <= 1'b0;
                        we_o <= 1'b0;
                        goto(S_WAIT1);
                end
        end
 
endcase
end
`endif
 
task goto;
input [3:0] nst;
begin
        state <= nst;
end
endtask
 
endmodule
 

Line No.	Rev	Author	Line
1	60	robfinch	`// ============================================================================`
2			`// __`
3	61	robfinch	`// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo`
4	60	robfinch	`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@finitron.ca`
6			`// \|\|`
7			`//`
8			`// FT64_ipt.v`
9			`// - 64 bit CPU inverted page table memory management unit`
10			`//`
11			`// This source file is free software: you can redistribute it and/or modify`
12			`// it under the terms of the GNU Lesser General Public License as published`
13			`// by the Free Software Foundation, either version 3 of the License, or`
14			`// (at your option) any later version.`
15			`//`
16			`// This source file is distributed in the hope that it will be useful,`
17			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
18			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
19			`// GNU General Public License for more details.`
20			`//`
21			`// You should have received a copy of the GNU General Public License`
22			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
23			`//`
24			`// ============================================================================`
25			`//`
26			`ifndef TRUE
27			`define TRUE 1'b1
28			`define FALSE 1'b0
29			`endif
30	61	robfinch	//`define BYPASS 1'b1
31	60	robfinch
32	61	robfinch	`module FT64_ipt(rst, clk, pkeys_i, ol_i, bte_i, cti_i, cs_i, icl_i, cyc_i, stb_i, ack_o, we_i, sel_i, vadr_i, dat_i, dat_o,`
33			`bte_o, cti_o, cyc_o, ack_i, we_o, sel_o, padr_o, exv_o, rdv_o, wrv_o, prv_o, page_fault);`
34	60	robfinch	`input rst;`
35			`input clk;`
36			`input [63:0] pkeys_i;`
37			`input [1:0] ol_i;`
38	61	robfinch	`input [1:0] bte_i;`
39	60	robfinch	`input [2:0] cti_i;`
40			`input cs_i;`
41			`input icl_i;`
42			`input cyc_i;`
43			`input stb_i;`
44			`output reg ack_o;`
45			`input we_i;`
46			`input [7:0] sel_i;`
47			`input [63:0] vadr_i;`
48			`input [63:0] dat_i;`
49			`output reg [63:0] dat_o;`
50	61	robfinch	`output reg [1:0] bte_o;`
51			`output reg [2:0] cti_o;`
52	60	robfinch	`output reg cyc_o;`
53			`input ack_i;`
54			`output reg we_o;`
55	61	robfinch	`output reg [7:0] sel_o;`
56	60	robfinch	`output reg [31:0] padr_o;`
57			`output reg exv_o;`
58			`output reg rdv_o;`
59			`output reg wrv_o;`
60			`output reg prv_o;`
61			`output reg page_fault;`
62
63			`parameter S_IDLE = 4'd0;`
64			`parameter S_CMP1 = 4'd1;`
65			`parameter S_CMP2 = 4'd2;`
66			`parameter S_CMP3 = 4'd3;`
67			`parameter S_CMP4 = 4'd4;`
68			`parameter S_CMP5 = 4'd5;`
69			`parameter S_CMP6 = 4'd6;`
70			`parameter S_WAIT1 = 4'd7;`
71			`parameter S_ACK = 4'd8;`
72	61	robfinch	`parameter S_RESET = 4'd9;`
73	60	robfinch
74			`integer n;`
75			`wire [9:0] pkey [0:5];`
76			`assign pkey[0] = pkeys_i[9:0];`
77			`assign pkey[1] = pkeys_i[19:10];`
78			`assign pkey[2] = pkeys_i[29:20];`
79			`assign pkey[3] = pkeys_i[39:30];`
80			`assign pkey[4] = pkeys_i[49:40];`
81			`assign pkey[5] = pkeys_i[59:50];`
82			`reg [3:0] state;`
83			`reg [15:0] pt_ad;`
84			`reg upd;`
85			`reg upd_done;`
86			`reg probe, probe_done;`
87			`reg pte_last;`
88			`reg [7:0] pte_asid;`
89			`reg [3:0] pte_drwx;`
90			`reg [18:0] pte_vadr;`
91			`reg [9:0] pte_key;`
92			`reg pt_wr;`
93			`reg [41:0] pt_dati;`
94			`wire [41:0] pt_dat;`
95
96			`FT64_iptram uram1 (`
97			`.clka(clk),`
98			`.ena(1'b1),`
99			`.wea(pt_wr),`
100			`.addra(pt_ad),`
101			`.dina(pt_dati),`
102			`.douta(pt_dat)`
103			`);`
104
105			`wire pt_last = pt_dat[23];`
106			`wire [18:0] pt_vadr = pt_dat[22:4];`
107			`wire [7:0] pt_asid = pt_dat[31:24];`
108			`wire [3:0] pt_drwx = pt_dat[3:0];`
109			`wire [9:0] pt_key = pt_dat[41:32];`
110
111			`reg keymatch;`
112			`always @*`
113			`begin`
114	61	robfinch	`keymatch = ol_i==2'b00;`
115	60	robfinch	`for (n = 0; n < 6; n = n + 1)`
116			`if (pt_key==pkey[n] \|\| pt_key==10'h0)`
117			`keymatch = 1'b1;`
118			`end`
119
120			`function [15:0] Hash1;`
121			`input [39:0] vadr;`
122			`begin`
123			`Hash1 = {1'b0,vadr[37:32],vadr[21:13]};`
124			`end`
125			`endfunction`
126
127			`function [15:0] Hash2;`
128			`input [39:0] vadr;`
129			`begin`
130			`Hash2 = {1'b1,vadr[37:32],vadr[21:13]};`
131			`end`
132			`endfunction`
133
134			`always @(posedge clk)`
135			`case(vadr_i[5:3])`
136			`3'd1:`
137			`dat_o <= pt_ad;`
138			`3'd2:`
139			`begin`
140			`dat_o[41:32] <= pte_key;`
141			`dat_o[31:24] <= pte_asid;`
142			`dat_o[23] <= pte_last;`
143			`dat_o[2:0] <= pte_drwx[2:0];`
144			`dat_o[7] <= pte_drwx[3];`
145			`end`
146			`3'd3:`
147			`dat_o <= pte_vadr;`
148			`default: dat_o <= 1'b0;`
149			`endcase`
150
151			`always @(posedge clk)`
152	61	robfinch	`bte_o <= bte_i;`
153			`always @(posedge clk)`
154			`cti_o <= cti_i;`
155			`always @(posedge clk)`
156			`sel_o <= sel_i;`
157			`ifdef BYPASS
158			`always @(posedge clk)`
159			`cyc_o <= cyc_i;`
160			`always @(posedge clk)`
161			`we_o <= we_i;`
162			`always @(posedge clk)`
163			`padr_o <= vadr_i[31:0];`
164			`always @(posedge clk)`
165			`exv_o <= 1'b0;`
166			`always @(posedge clk)`
167			`rdv_o <= 1'b0;`
168			`always @(posedge clk)`
169			`wrv_o <= 1'b0;`
170			`always @(posedge clk)`
171			`prv_o <= 1'b0;`
172			`always @(posedge clk)`
173			`page_fault <= 1'b0;`
174			`else
175			`always @(posedge clk)`
176	60	robfinch	`if (rst) begin`
177			`cyc_o <= 1'b0;`
178			`padr_o <= 32'hFFFC0100;`
179			`ack_o <= 1'b0;`
180			`exv_o <= 1'b0;`
181			`rdv_o <= 1'b0;`
182			`wrv_o <= 1'b0;`
183			`prv_o <= 1'b0;`
184	61	robfinch	`pt_wr <= 1'b1;`
185			`pt_ad <= 1'b0;`
186			`pt_dati <= 1'b0;`
187	60	robfinch	`upd <= 1'b0;`
188			`probe <= 1'b0;`
189			`upd_done <= 1'b0;`
190			`probe_done <= 1'b0;`
191			`goto(S_IDLE);`
192			`end`
193			`else begin`
194			`pt_wr <= 1'b0;`
195			`page_fault <= 1'b0;`
196			`ack_o <= 1'b0;`
197			`case(state)`
198	61	robfinch	`// Clear page table ram on reset.`
199			`S_RESET:`
200			`begin`
201			`pt_ad <= pt_ad + 2'd1;`
202			`if (&pt_ad) begin`
203			`pt_wr <= 1'b0;`
204			`state <= S_IDLE;`
205			`end`
206			`end`
207	60	robfinch	`S_IDLE:`
208			`if (cyc_i) begin`
209	61	robfinch	`if (cs_i & stb_i) begin`
210	60	robfinch	`ack_o <= 1'b1;`
211			`case(vadr_i[5:3])`
212			`3'd0:`
213			`begin`
214			`if (dat_i[0] & !upd_done) begin`
215			`pt_ad <= Hash1({pte_asid,pte_vadr});`
216			`upd <= 1'b1;`
217			`goto(S_CMP1);`
218			`end`
219			`else if (dat_i[1] & !probe_done) begin`
220			`pt_ad <= Hash1({pte_asid,pte_vadr});`
221			`probe <= 1'b1;`
222			`goto(S_CMP1);`
223			`end`
224			`end`
225			`3'd2:`
226			`begin`
227			`pte_key <= dat_i[41:32];`
228			`pte_asid <= dat_i[31:24];`
229			`pte_last <= dat_i[22];`
230			`pte_drwx <= {dat_i[7],dat_i[2:0]};`
231			`end`
232			`3'd3:`
233			`begin`
234			`pte_vadr <= dat_i[18:0];`
235			`end`
236			`endcase`
237			`end`
238			`else begin`
239			`upd_done <= 1'b0;`
240			`probe_done <= 1'b0;`
241			`upd <= 1'b0;`
242			`probe <= 1'b0;`
243			`if (ol_i==2'b0) begin`
244			`cyc_o <= 1'b1;`
245			`we_o <= we_i;`
246	61	robfinch	`padr_o <= vadr_i[31:0];`
247	60	robfinch	`goto(S_ACK);`
248			`end`
249			`else begin`
250			`// Video frame buffer ($00xxxxxx) and ROM / IO ($FFxxxxxx) regions are`
251			`// not mapped.`
252			`if (vadr_i[31:24]==8'hFF \|\| vadr_i[31:24]==8'h00) begin`
253			`cyc_o <= 1'b1;`
254			`we_o <= we_i;`
255	61	robfinch	`padr_o <= vadr_i[31:0];`
256	60	robfinch	`goto(S_ACK);`
257			`end`
258			`else begin`
259			`pt_ad <= Hash1({vadr_i[63:56],vadr_i});`
260			`goto(S_CMP1);`
261			`end`
262			`end`
263			`end`
264			`end`
265			`else begin`
266			`exv_o <= 1'b0;`
267			`rdv_o <= 1'b0;`
268			`wrv_o <= 1'b0;`
269			`prv_o <= 1'b0;`
270			`end`
271
272			`S_CMP1:`
273			`goto(S_CMP2);`
274			`S_CMP2:`
275			`goto(S_CMP3);`
276			`S_CMP3:`
277			`if (pt_drwx[2:0]==3'b0) begin`
278			`if (upd) begin`
279			`pte_key <= 10'h0;`
280			`pte_last <= 1'b0;`
281			`pte_drwx <= 4'd0;`
282			`pt_wr <= 1'b1;`
283			`pt_dati <= {pte_key,pte_asid,pte_last,pte_vadr[18:0],pte_drwx};`
284			`upd_done <= 1'b1;`
285			`goto(S_IDLE);`
286			`end`
287			`else if (probe) begin`
288			`pte_drwx <= 3'b0;`
289			`pte_vadr <= 19'b0;`
290			`pte_asid <= 8'b0;`
291			`pte_last <= 1'b0;`
292			`pte_key <= 10'h0;`
293			`probe_done <= 1'b1;`
294			`goto(S_IDLE);`
295			`end`
296			`else begin`
297			`page_fault <= 1'b1;`
298			`goto(S_WAIT1);`
299			`end`
300			`end`
301			`else if (pt_asid==vadr_i[63:56] && pt_vadr==vadr_i[31:13]) begin`
302			`if (upd) begin`
303			`if (keymatch) begin`
304			`pte_key <= pt_key;`
305			`pte_last <= pt_last;`
306			`pte_drwx <= pt_drwx;`
307			`pt_wr <= 1'b1;`
308			`pt_dati <= {pte_key,pt_dat[31:4],pte_drwx};`
309			`end`
310			`else`
311			`prv_o <= 1'b1;`
312			`upd_done <= 1'b1;`
313			`goto(S_IDLE);`
314			`end`
315			`else if (probe) begin`
316			`if (keymatch) begin`
317			`pte_key <= pt_key;`
318			`pte_last <= pt_last;`
319			`pte_drwx <= pt_drwx;`
320			`end`
321			`else`
322			`prv_o <= 1'b1;`
323			`probe_done <= 1'b1;`
324			`goto(S_IDLE);`
325			`end`
326			`else if (~ack_i) begin`
327			`if (keymatch) begin`
328			`cyc_o <= 1'b1;`
329			`we_o <= we_i & pt_drwx[1];`
330			`if (!pt_drwx[1] & we_i) wrv_o <= 1'b1;`
331			`if (!pt_drwx[2] & ~we_i) rdv_o <= 1'b1;`
332			`if (!pt_drwx[0] & icl_i) exv_o <= 1'b1;`
333			`padr_o <= {pt_ad,vadr_i[12:0]};`
334			`end`
335			`else begin`
336			`cyc_o <= 1'b1;`
337			`we_o <= 1'b0;`
338	61	robfinch	`padr_o <= 32'hFFFFFFF8;`
339	60	robfinch	`prv_o <= 1'b1;`
340			`end`
341			`goto(S_ACK);`
342			`end`
343			`end`
344			`else begin`
345			`if (upd\|probe)`
346			`pt_ad <= Hash2({pte_asid,pte_vadr});`
347			`else`
348			`pt_ad <= Hash2({vadr_i[63:56],vadr_i});`
349			`goto(S_CMP4);`
350			`end`
351
352			`S_CMP4:`
353			`goto(S_CMP5);`
354			`S_CMP5:`
355			`goto(S_CMP6);`
356			`S_CMP6:`
357			`if (pt_drwx[2:0]==3'b0) begin`
358			`if (upd) begin`
359			`pte_key <= 10'h0;`
360			`pte_last <= 1'b0;`
361			`pte_drwx <= 4'd0;`
362			`pt_wr <= 1'b1;`
363			`pt_dati <= {pte_key,pte_asid,pte_last,pte_vadr[18:0],pte_drwx};`
364			`upd_done <= 1'b1;`
365			`goto(S_IDLE);`
366			`end`
367			`else if (probe) begin`
368			`pte_key <= 10'h0;`
369			`pte_drwx <= 43'b0;`
370			`pte_vadr <= 19'b0;`
371			`pte_asid <= 8'b0;`
372			`pte_last <= 1'b0;`
373			`probe_done <= 1'b1;`
374			`goto(S_IDLE);`
375			`end`
376			`else begin`
377			`page_fault <= 1'b1;`
378			`goto(S_WAIT1);`
379			`end`
380			`end`
381			`else if (pt_asid==vadr_i[63:56] && pt_vadr==vadr_i[31:13]) begin`
382			`if (upd) begin`
383			`if (keymatch) begin`
384			`pte_key <= pt_key;`
385			`pte_last <= pt_last;`
386			`pte_drwx <= pt_drwx;`
387			`pt_wr <= 1'b1;`
388			`pt_dati <= {pte_key,pt_dat[31:4],pte_drwx};`
389			`end`
390			`else`
391			`prv_o <= 1'b1;`
392			`upd_done <= 1'b1;`
393			`goto(S_IDLE);`
394			`end`
395			`else if (probe) begin`
396			`if (keymatch) begin`
397			`pte_key <= pt_key;`
398			`pte_last <= pt_last;`
399			`pte_drwx <= pt_drwx;`
400			`probe_done <= 1'b1;`
401			`end`
402			`else`
403			`prv_o <= 1'b1;`
404			`goto(S_IDLE);`
405			`end`
406			`else if (~ack_i) begin`
407			`if (keymatch) begin`
408			`cyc_o <= 1'b1;`
409			`we_o <= we_i & pt_drwx[1];`
410			`if (!pt_drwx[1] & we_i) wrv_o <= 1'b1;`
411			`if (!pt_drwx[2] & ~we_i) rdv_o <= 1'b1;`
412			`if (!pt_drwx[0] & icl_i) exv_o <= 1'b1;`
413			`padr_o <= {pt_ad,vadr_i[12:0]};`
414			`end`
415			`else begin`
416			`cyc_o <= 1'b1;`
417			`we_o <= 1'b0;`
418	61	robfinch	`padr_o <= 32'hFFFFFFF8;`
419	60	robfinch	`prv_o <= 1'b1;`
420			`end`
421			`goto(S_ACK);`
422			`end`
423			`end`
424			`else begin`
425			`pt_ad <= {pt_ad+8'd65};`
426			`goto(S_CMP4);`
427			`end`
428
429			`// Wait a clock cycle for a page fault to register.`
430			`S_WAIT1:`
431			`goto(S_IDLE);`
432
433			`S_ACK:`
434			`if (ack_i) begin`
435			`if (cti_i==3'b000 \|\| cti_i==3'b111) begin`
436			`cyc_o <= 1'b0;`
437			`we_o <= 1'b0;`
438			`goto(S_WAIT1);`
439			`end`
440			`end`
441
442			`endcase`
443			`end`
444	61	robfinch	`endif
445	60	robfinch
446			`task goto;`
447			`input [3:0] nst;`
448			`begin`
449			`state <= nst;`
450			`end`
451			`endtask`
452
453			`endmodule`
454

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