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// ============================================================================

//        __

//   \\__/ o\    (C) 2017-2019  Robert Finch, Waterloo

//    \  __ /    All rights reserved.

//     \/_//     robfinch<remove>@finitron.ca

//       ||

//

//      FT64.v

//      Features include:

//  - 16/32/48 bit instructions

//  - vector instruction set,

//  - SIMD instructions

//  - data width of 64 bits

//      - 32 general purpose registers

//  - 32 floating point registers

//      - 32 vector registers, length 63

//  - powerful branch prediction

//  - branch target buffer (BTB)

//  - return address predictor (RSB)

//  - bus interface unit

//  - instruction and data caches

//      - fine-grained simultaneous multi-threading (SMT)

//  - bus randomizer on exceptional conditions

//

// This source file is free software: you can redistribute it and/or modify 

// it under the terms of the GNU Lesser General Public License as published 

// by the Free Software Foundation, either version 3 of the License, or     

// (at your option) any later version.                                      

//                                                                          

// This source file is distributed in the hope that it will be useful,      

// but WITHOUT ANY WARRANTY; without even the implied warranty of           

// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            

// GNU General Public License for more details.                             

//                                                                          

// You should have received a copy of the GNU General Public License        

// along with this program.  If not, see <http://www.gnu.org/licenses/>.    

//

// Approx 41,000 LUTs. 66,000 LC's.

// ============================================================================

//

`include "FT64_config.vh"

`include "FT64_defines.vh"

module FT64(hartid, rst, clk_i, clk4x, tm_clk_i, irq_i, vec_i, bte_o, cti_o, bok_i, cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_o, dat_i,

    ol_o, pcr_o, pcr2_o, pkeys_o, icl_o, sr_o, cr_o, rbi_i, signal_i, exc_o);

input [63:0] hartid;

input rst;

input clk_i;

input clk4x;

input tm_clk_i;

input [3:0] irq_i;

input [7:0] vec_i;

output reg [1:0] bte_o;

output reg [2:0] cti_o;

input bok_i;

output cyc_o;

output reg stb_o;

input ack_i;

input err_i;

output we_o;

output reg [7:0] sel_o;

output [`ABITS] adr_o;

output reg [63:0] dat_o;

input [63:0] dat_i;

output reg [1:0] ol_o;

output [31:0] pcr_o;

output [63:0] pcr2_o;

output [63:0] pkeys_o;

output reg icl_o;

output reg cr_o;

output reg sr_o;

input rbi_i;

input [31:0] signal_i;

(* mark_debug="true" *)

output [7:0] exc_o;

parameter TM_CLKFREQ = 20000000;

parameter QENTRIES = `QENTRIES;

parameter RSTPC = 64'hFFFFFFFFFFFC0100;

parameter BRKPC = 64'hFFFFFFFFFFFC0000;

`ifdef SUPPORT_SMT

parameter PREGS = 256;   // number of physical registers - 1

parameter AREGS = 256;   // number of architectural registers

`else

parameter PREGS = 128;

parameter AREGS = 128;

`endif

parameter RBIT = 11;

parameter DEBUG = 1'b0;

parameter NMAP = QENTRIES;

parameter BRANCH_PRED = 1'b0;

parameter SUP_TXE = 1'b0;

`ifdef SUPPORT_VECTOR

parameter SUP_VECTOR = 1'b1;

`else

parameter SUP_VECTOR = 1'b0;

`endif

parameter DBW = 64;

parameter ABW = 64;

parameter AMSB = ABW-1;

parameter NTHREAD = 1;

reg [7:0] i;

integer n;

integer j, k;

genvar g, h;

parameter TRUE = 1'b1;

parameter FALSE = 1'b0;

// Memory access sizes

parameter byt = 3'd0;

parameter wyde = 3'd1;

parameter tetra = 3'd2;

parameter octa = 3'd3;

parameter hexi = 3'd4;

// IQ states

parameter IQS_INVALID = 3'd0;

parameter IQS_QUEUED = 3'd1;

parameter IQS_OUT = 3'd2;

parameter IQS_AGEN = 3'd3;

parameter IQS_MEM = 3'd4;

parameter IQS_DONE = 3'd5;

parameter IQS_CMT = 3'd6;

wire clk;

//BUFG uclkb1

//(

//      .I(clk_i),

//      .O(clk)

//);

assign clk = clk_i;

wire exv_i;

wire rdv_i;

wire wrv_i;

reg [ABW-1:0] vadr;

reg cyc;

reg we;

wire dc_ack;

wire acki = ack_i|dc_ack;

wire [RBIT:0] Ra0, Ra1, Ra2;

wire [RBIT:0] Rb0, Rb1, Rb2;

wire [RBIT:0] Rc0, Rc1, Rc2;

wire [RBIT:0] Rt0, Rt1, Rt2;

wire [63:0] rfoa0,rfob0,rfoc0,rfoc0a,rfot0;

wire [63:0] rfoa1,rfob1,rfoc1,rfoc1a,rfot1;

wire [63:0] rfoa2,rfob2,rfoc2,rfoc2a,rfot2;

`ifdef SUPPORT_SMT

wire [7:0] Ra0s = {Ra0[7:0]};

wire [7:0] Ra1s = {Ra1[7:0]};

wire [7:0] Ra2s = {Ra2[7:0]};

wire [7:0] Rb0s = {Rb0[7:0]};

wire [7:0] Rb1s = {Rb1[7:0]};

wire [7:0] Rb2s = {Rb2[7:0]};

wire [7:0] Rc0s = {Rc0[7:0]};

wire [7:0] Rc1s = {Rc1[7:0]};

wire [7:0] Rc2s = {Rc2[7:0]};

wire [7:0] Rt0s = {Rt0[7:0]};

wire [7:0] Rt1s = {Rt1[7:0]};

wire [7:0] Rt2s = {Rt2[7:0]};

`else

wire [6:0] Ra0s = {Ra0[7],Ra0[5:0]};

wire [6:0] Ra1s = {Ra1[7],Ra1[5:0]};

wire [6:0] Ra2s = {Ra2[7],Ra2[5:0]};

wire [6:0] Rb0s = {Rb0[7],Rb0[5:0]};

wire [6:0] Rb1s = {Rb1[7],Rb1[5:0]};

wire [6:0] Rb2s = {Rb2[7],Rb2[5:0]};

wire [6:0] Rc0s = {Rc0[7],Rc0[5:0]};

wire [6:0] Rc1s = {Rc1[7],Rc1[5:0]};

wire [6:0] Rc2s = {Rc2[7],Rc2[5:0]};

wire [6:0] Rt0s = {Rt0[7],Rt0[5:0]};

wire [6:0] Rt1s = {Rt1[7],Rt1[5:0]};

wire [6:0] Rt2s = {Rt2[7],Rt2[5:0]};

/*

wire [5:0] Ra0s = {Ra0[5:0]};

wire [5:0] Ra1s = {Ra1[5:0]};

wire [5:0] Rb0s = {Rb0[5:0]};

wire [5:0] Rb1s = {Rb1[5:0]};

wire [5:0] Rc0s = {Rc0[5:0]};

wire [5:0] Rc1s = {Rc1[5:0]};

wire [5:0] Rt0s = {Rt0[5:0]};

wire [5:0] Rt1s = {Rt1[5:0]};

*/

`endif

reg [63:0] wbrcd;

wire [5:0] brgs;

`ifdef SUPPORT_BBMS

reg [15:0] thrd_handle [0:63];

reg [63:0] prg_base [0:63];

reg [63:0] prg_limit [0:63];

reg [63:0] en_barrier [0:63];                                     // environment bound

reg [63:0] cl_barrier [0:63];

reg [63:0] cu_barrier [0:63];

reg [63:0] ro_barrier [0:63];

reg [63:0] dl_barrier [0:63];

reg [63:0] du_barrier [0:63];

reg [63:0] sl_barrier [0:63];

reg [63:0] su_barrier [0:63];

reg [7:0] env_priv [0:63];

reg [7:0] cod_priv [0:63];

reg [7:0] rdo_priv [0:63];

reg [7:0] dat_priv [0:63];

reg [7:0] stk_priv [0:63];

reg [15:0] th;

reg [63:0] pb;

reg [63:0] cbl;

reg [63:0] cbu;

reg [63:0] ro;

reg [63:0] dbl;

reg [63:0] dbu;

reg [63:0] sbl;

reg [63:0] sbu;

reg [63:0] en;

reg [7:0] env_pl;

reg [7:0] cod_pl;

reg [7:0] rdo_pl;

reg [7:0] dat_pl;

reg [7:0] stk_pl;

initial begin

        for (n = 0; n < 64; n = n + 1)

        begin

                thrd_handle[n] <= 1'd0;

                prg_base[n] <= 1'd0;

                cl_barrier[n] <= 1'd0;

                cu_barrier[n] <= 64'hFFFFFFFFFFFFFFFF;

                ro_barrier[n] <= 1'd0;

                dl_barrier[n] <= 1'd0;

                du_barrier[n] <= 64'hFFFFFFFFFFFFFFFF;

                sl_barrier[n] <= 1'd0;

                su_barrier[n] <= 64'hFFFFFFFFFFFFFFFF;

                env_priv[n] <= 8'h00;

                cod_priv[n] <= 8'h00;

                rdo_priv[n] <= 8'h00;

                dat_priv[n] <= 8'h00;

                stk_priv[n] <= 8'h00;

        end

end

always @(posedge clk_i)

begin

        th <= thrd_handle[brgs];

        pb <= prg_base[brgs];

        cbl <= cl_barrier[brgs];

        cbu <= cu_barrier[brgs];

        ro <= ro_barrier[brgs];

        dbl <= dl_barrier[brgs];

        dbu <= du_barrier[brgs];

        sbl <= sl_barrier[brgs];

        sbu <= su_barrier[brgs];

        en <= en_barrier[brgs];

        env_pl <= env_priv[brgs];

        cod_pl <= cod_priv[brgs];

        rdo_pl <= rdo_priv[brgs];

        dat_pl <= dat_priv[brgs];

        stk_pl <= stk_priv[brgs];

end

//wire [23:0] currentPrgSelector = prg_selector[brgs];

`else

wire [63:0] pb = 1'd0;

wire [63:0] cbl = 1'd0;

wire [63:0] cbu = 64'hFFFFFFFFFFFFFFFF;

wire [63:0] ro = 1'd0;

wire [63:0] dbl = 1'd0;

wire [63:0] dbu = 64'hFFFFFFFFFFFFFFFF;

wire [63:0] sbl = 1'd0;

wire [63:0] sbu = 64'hFFFFFFFFFFFFFFFF;

wire [63:0] en = 1'd0;

wire [7:0] env_pl = 8'h00;

wire [7:0] cod_pl = 8'h00;

wire [7:0] rdo_pl = 8'h00;

wire [7:0] dat_pl = 8'h00;

wire [7:0] stk_pl = 8'h00;

`endif

reg  [PREGS-1:0] rf_v;

reg  [`QBITSP1] rf_source[0:AREGS-1];

reg  [15:0] prf_v;

reg  [`QBITSP1] prf_source[0:15];

initial begin

for (n = 0; n < AREGS; n = n + 1)

        rf_source[n] = 1'b0;

for (n = 0; n < 16; n = n + 1)

        prf_source[n] <= 1'b0;

end

wire [`ABITS] pc0a;

wire [`ABITS] pc1a;

wire [`ABITS] pc2a;

`ifdef SUPPORT_BBMS

wire [`ABITS] pc0 = (pc0a[47:40]==8'hFF||ol==2'b00) ? pc0a : {pb[50:0],13'd0} + pc0a[47:0];

wire [`ABITS] pc1 = (pc1a[47:40]==8'hFF||ol==2'b00) ? pc1a : {pb[50:0],13'd0} + pc1a[47:0];

wire [`ABITS] pc2 = (pc2a[47:40]==8'hFF||ol==2'b00) ? pc2a : {pb[50:0],13'd0} + pc2a[47:0];

`else

wire [`ABITS] pc0 = pc0a;

wire [`ABITS] pc1 = pc1a;

wire [`ABITS] pc2 = pc2a;

`endif

reg excmiss;

reg [`ABITS] excmisspc;

reg excthrd;

reg exception_set;

reg rdvq;               // accumulated read violation

reg errq;               // accumulated err_i input status

reg exvq;

// Vector

reg [5:0] vqe0, vqe1, vqe2;   // vector element being queued

reg [5:0] vqet0, vqet1, vqet2;

reg [7:0] vl;           // vector length

reg [63:0] vm [0:7];    // vector mask registers

reg [1:0] m2;

reg [31:0] wb_merges;

// CSR's

reg [63:0] cr0;

wire snr = cr0[17];             // sequence number reset

wire dce = cr0[30];     // data cache enable

wire bpe = cr0[32];     // branch predictor enable

wire wbm = cr0[34];

wire sple = cr0[35];            // speculative load enable

wire ctgtxe = cr0[33];

wire pred_on = 1'b0;

reg [63:0] pmr;

wire id1_available = pmr[0];

wire id2_available = pmr[1];

wire id3_available = pmr[2];

wire alu0_available = pmr[8];

wire alu1_available = pmr[9];

wire fpu1_available = pmr[16];

wire fpu2_available = pmr[17];

wire mem1_available = pmr[24];

wire mem2_available = pmr[25];

wire mem3_available = pmr[26];

wire fcu_available = pmr[32];

// Simply setting this flag to zero should strip out almost all the logic

// associated SMT.

`ifdef SUPPORT_SMT

wire thread_en = cr0[16];

`else

wire thread_en = 1'b0;

`endif

wire vechain = cr0[18];

// Performance CSR's

reg [39:0] iq_ctr;

reg [39:0] irq_ctr;                                      // count of number of interrupts

reg [39:0] bm_ctr;                                       // branch miss counter

reg [39:0] br_ctr;                                       // branch counter

reg [39:0] icl_ctr;                                      // instruction cache load counter

reg [7:0] fcu_timeout;

reg [63:0] tick;

reg [63:0] wc_time;

reg [31:0] pcr;

reg [63:0] pcr2;

assign pcr_o = pcr;

assign pcr2_o = pcr2;

reg [63:0] aec;

(* mark_debug = "true" *)

reg [15:0] cause[0:15];

`ifdef SUPPORT_SMT

reg [`ABITS] epc [0:NTHREAD];

reg [`ABITS] epc0 [0:NTHREAD];

reg [`ABITS] epc1 [0:NTHREAD];

reg [`ABITS] epc2 [0:NTHREAD];

reg [`ABITS] epc3 [0:NTHREAD];

reg [`ABITS] epc4 [0:NTHREAD];

reg [`ABITS] epc5 [0:NTHREAD];

reg [`ABITS] epc6 [0:NTHREAD];

reg [`ABITS] epc7 [0:NTHREAD];

reg [`ABITS] epc8 [0:NTHREAD];                   // exception pc and stack

reg [63:0] mstatus [0:NTHREAD];           // machine status

wire [3:0] im = mstatus[0][3:0];

wire [1:0] ol [0:NTHREAD];

wire [1:0] dl [0:NTHREAD];

assign ol[0] = mstatus[0][5:4];   // operating level

assign dl[0] = mstatus[0][21:20];

wire [7:0] cpl [0:NTHREAD];

assign cpl[0] = mstatus[0][13:6]; // current privilege level

wire [5:0] rgs [0:NTHREAD];

assign ol[1] = mstatus[1][5:4]; // operating level

assign cpl[1] = mstatus[1][13:6];       // current privilege level

assign dl[1] = mstatus[1][21:20];

wire [7:0] ASID = mstatus[0][47:40];

reg [15:0] ol_stack [0:NTHREAD];

reg [15:0] dl_stack [0:NTHREAD];

reg [31:0] im_stack [0:NTHREAD];

reg [63:0] pl_stack [0:NTHREAD];

reg [63:0] rs_stack [0:NTHREAD];

reg [63:0] brs_stack [0:NTHREAD];

reg [63:0] fr_stack [0:NTHREAD];

assign rgs[0] = rs_stack[0][5:0];

assign rgs[1] = rs_stack[1][5:0];

wire mprv = mstatus[0][55];

wire [5:0] fprgs = mstatus[0][25:20];

//assign ol_o = mprv ? ol_stack[0][2:0] : ol[0];

wire vca = mstatus[0][32];               // vector chaining active

`else

reg [`ABITS] epc ;

reg [`ABITS] epc0 ;

reg [`ABITS] epc1 ;

reg [`ABITS] epc2 ;

reg [`ABITS] epc3 ;

reg [`ABITS] epc4 ;

reg [`ABITS] epc5 ;

reg [`ABITS] epc6 ;

reg [`ABITS] epc7 ;

reg [`ABITS] epc8 ;                     // exception pc and stack

reg [63:0] mstatus ;             // machine status

wire [3:0] im = mstatus[3:0];

wire [1:0] ol ;

wire [1:0] dl;

assign ol = mstatus[5:4];       // operating level

assign dl = mstatus[21:20];

wire [7:0] cpl ;

assign cpl = mstatus[13:6];     // current privilege level

wire [5:0] rgs ;

reg [15:0] ol_stack ;

reg [15:0] dl_stack ;

reg [31:0] im_stack ;

reg [63:0] pl_stack ;

reg [63:0] rs_stack ;

reg [63:0] brs_stack ;

reg [63:0] fr_stack ;

assign rgs = rs_stack[5:0];

assign brgs = brs_stack[5:0];

wire mprv = mstatus[55];

wire [7:0] ASID = mstatus[47:40];

wire [5:0] fprgs = mstatus[25:20];

//assign ol_o = mprv ? ol_stack[2:0] : ol;

wire vca = mstatus[32];         // vector chaining active

`endif

reg [63:0] keys;

assign pkeys_o = keys;

reg [63:0] tcb;

reg [47:0] bad_instr[0:15];

reg [`ABITS] badaddr[0:15];

reg [`ABITS] tvec[0:7];

reg [63:0] sema;

reg [63:0] vm_sema;

reg [63:0] cas;         // compare and swap

reg [63:0] ve_hold;

reg isCAS, isAMO, isInc, isSpt, isRMW;

reg [`QBITS] casid;

reg [4:0] regLR = 5'd29;

reg [2:0] fp_rm;

reg fp_inexe;

reg fp_dbzxe;

reg fp_underxe;

reg fp_overxe;

reg fp_invopxe;

reg fp_giopxe;

reg fp_nsfp = 1'b0;

reg fp_fractie;

reg fp_raz;

reg fp_neg;

reg fp_pos;

reg fp_zero;

reg fp_inf;

reg fp_inex;            // inexact exception

reg fp_dbzx;            // divide by zero exception

reg fp_underx;          // underflow exception

reg fp_overx;           // overflow exception

reg fp_giopx;           // global invalid operation exception

reg fp_sx;                      // summary exception

reg fp_swtx;        // software triggered exception

reg fp_gx;

reg fp_invopx;

reg fp_infzerox;

reg fp_zerozerox;

reg fp_subinfx;

reg fp_infdivx;

reg fp_NaNCmpx;

reg fp_cvtx;

reg fp_sqrtx;

reg fp_snanx;

wire [31:0] fp_status = {

        fp_rm,

        fp_inexe,

        fp_dbzxe,

        fp_underxe,

        fp_overxe,

        fp_invopxe,

        fp_nsfp,

        fp_fractie,

        fp_raz,

        1'b0,

        fp_neg,

        fp_pos,

        fp_zero,

        fp_inf,

        fp_swtx,

        fp_inex,

        fp_dbzx,

        fp_underx,

        fp_overx,

        fp_giopx,

        fp_gx,

        fp_sx,

        fp_cvtx,

        fp_sqrtx,

        fp_NaNCmpx,

        fp_infzerox,

        fp_zerozerox,

        fp_infdivx,

        fp_subinfx,

        fp_snanx

        };

reg [63:0] fpu_csr;