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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [twoway/] [FT64_BTB.v] - Blame information for rev 60

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1 60 robfinch 
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      FT64_BTB.v
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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module FT64_BTB(rst, wclk,
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                wr0, wadr0, wdat0, valid0,
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                wr1, wadr1, wdat1, valid1,
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                wr2, wadr2, wdat2, valid2,
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                rclk, pcA, btgtA, pcB, btgtB,
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                pcC, btgtC, pcD, btgtD, pcE, btgtE, pcF, btgtF,
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                hitA, hitB, hitC, hitD, hitE, hitF,
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    npcA, npcB, npcC, npcD, npcE, npcF);
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parameter AMSB = 63;
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parameter RSTPC = 64'hFFFFFFFFFFFC0100;
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input rst;
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input wclk;
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input wr0;
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input [AMSB:0] wadr0;
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input [AMSB:0] wdat0;
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input valid0;
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input wr1;
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input [AMSB:0] wadr1;
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input [AMSB:0] wdat1;
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input valid1;
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input wr2;
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input [AMSB:0] wadr2;
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input [AMSB:0] wdat2;
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input valid2;
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input rclk;
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input [AMSB:0] pcA;
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output [AMSB:0] btgtA;
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input [AMSB:0] pcB;
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output [AMSB:0] btgtB;
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input [AMSB:0] pcC;
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output [AMSB:0] btgtC;
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input [AMSB:0] pcD;
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output [AMSB:0] btgtD;
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input [AMSB:0] pcE;
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output [AMSB:0] btgtE;
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input [AMSB:0] pcF;
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output [AMSB:0] btgtF;
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output hitA;
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output hitB;
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output hitC;
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output hitD;
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output hitE;
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output hitF;
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input [AMSB:0] npcA;
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input [AMSB:0] npcB;
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input [AMSB:0] npcC;
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input [AMSB:0] npcD;
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input [AMSB:0] npcE;
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input [AMSB:0] npcF;
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integer n;
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reg [AMSB:0] pcs [0:31];
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reg [AMSB:0] wdats [0:31];
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reg [AMSB:0] wdat;
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reg [4:0] pcstail,pcshead;
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reg [AMSB:0] pc;
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reg takb;
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reg wrhist;
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reg [(AMSB+1)*2+1:0] mem [0:1023];
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reg [9:0] radrA, radrB, radrC, radrD, radrE, radrF;
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initial begin
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    for (n = 0; n < 1024; n = n + 1)
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        mem[n] <= RSTPC;
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end
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always @(posedge wclk)
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if (rst)
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        pcstail <= 5'd0;
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else begin
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        case({wr0,wr1,wr2})
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        3'b000: ;
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        3'b001:
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                begin
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                pcs[pcstail] <= {wadr2[31:1],valid2};
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                wdats[pcstail] <= wdat2;
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                pcstail <= pcstail + 5'd1;
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                end
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        3'b010:
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                begin
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                pcs[pcstail] <= {wadr1[31:1],valid1};
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                wdats[pcstail] <= wdat1;
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                pcstail <= pcstail + 5'd1;
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                end
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        3'b011:
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                begin
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                pcs[pcstail] <= {wadr1[31:1],valid1};
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                pcs[pcstail+1] <= {wadr2[31:1],valid2};
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                wdats[pcstail] <= wdat1;
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                wdats[pcstail+1] <= wdat2;
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                pcstail <= pcstail + 5'd2;
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                end
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        3'b100:
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                begin
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                pcs[pcstail] <= {wadr0[31:1],valid0};
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                wdats[pcstail] <= wdat0;
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                pcstail <= pcstail + 5'd1;
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                end
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        3'b101:
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                begin
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                pcs[pcstail] <= {wadr0[31:1],valid0};
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                pcs[pcstail+1] <= {wadr2[31:1],valid2};
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                wdats[pcstail] <= wdat0;
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                wdats[pcstail+1] <= wdat2;
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                pcstail <= pcstail + 5'd2;
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                end
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        3'b110:
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                begin
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                pcs[pcstail] <= {wadr0[31:1],valid0};
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                pcs[pcstail+1] <= {wadr1[31:1],valid1};
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                wdats[pcstail] <= wdat0;
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                wdats[pcstail+1] <= wdat1;
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                pcstail <= pcstail + 5'd2;
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                end
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        3'b111:
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                begin
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                pcs[pcstail] <= {wadr0[31:1],valid0};
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                pcs[pcstail+1] <= {wadr1[31:1],valid1};
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                pcs[pcstail+2] <= {wadr2[31:1],valid2};
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                wdats[pcstail] <= wdat0;
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                wdats[pcstail+1] <= wdat1;
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                wdats[pcstail+2] <= wdat2;
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                pcstail <= pcstail + 5'd3;
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                end
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        endcase
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end
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always @(posedge wclk)
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if (rst)
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        pcshead <= 5'd0;
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else begin
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        wrhist <= 1'b0;
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        if (pcshead != pcstail) begin
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                pc <= pcs[pcshead];
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                takb <= pcs[pcshead][0];
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                wdat <= wdats[pcshead];
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                wrhist <= 1'b1;
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                pcshead <= pcshead + 5'd1;
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        end
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end
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always @(posedge wclk)
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begin
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    if (wrhist) #1 mem[pc[9:0]][AMSB:0] <= wdat;
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    if (wrhist) #1 mem[pc[9:0]][(AMSB+1)*2:AMSB+1] <= pc;
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    if (wrhist) #1 mem[pc[9:0]][(AMSB+1)*2+1] <= takb;
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end
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always @(posedge rclk)
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    #1 radrA <= pcA[11:2];
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always @(posedge rclk)
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    #1 radrB <= pcB[11:2];
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always @(posedge rclk)
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    #1 radrC <= pcC[11:2];
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always @(posedge rclk)
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    #1 radrD <= pcD[11:2];
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always @(posedge rclk)
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    #1 radrE <= pcE[11:2];
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always @(posedge rclk)
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    #1 radrF <= pcF[11:2];
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assign hitA = mem[radrA][(AMSB+1)*2:AMSB+1]==pcA && mem[radrA][(AMSB+1)*2+1];
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assign hitB = mem[radrB][(AMSB+1)*2:AMSB+1]==pcB && mem[radrB][(AMSB+1)*2+1];
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assign hitC = mem[radrC][(AMSB+1)*2:AMSB+1]==pcC && mem[radrC][(AMSB+1)*2+1];
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assign hitD = mem[radrD][(AMSB+1)*2:AMSB+1]==pcD && mem[radrD][(AMSB+1)*2+1];
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assign hitE = mem[radrE][(AMSB+1)*2:AMSB+1]==pcE && mem[radrE][(AMSB+1)*2+1];
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assign hitF = mem[radrF][(AMSB+1)*2:AMSB+1]==pcF && mem[radrF][(AMSB+1)*2+1];
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assign btgtA = hitA ? mem[radrA][AMSB:0] : npcA;
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assign btgtB = hitB ? mem[radrB][AMSB:0] : npcB;
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assign btgtC = hitC ? mem[radrC][AMSB:0] : npcC;
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assign btgtD = hitD ? mem[radrD][AMSB:0] : npcD;
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assign btgtE = hitE ? mem[radrE][AMSB:0] : npcE;
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assign btgtF = hitF ? mem[radrF][AMSB:0] : npcF;
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endmodule

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