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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [twoway/] [FT64_BranchPredictor.v] - Blame information for rev 60

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1 60 robfinch 
//=============================================================================
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//        __
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//   \\__/ o\    (C) 2013-2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      FT64_BranchPredictor.v
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//=============================================================================
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//
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module FT64_BranchPredictor(rst, clk, en,
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    xisBranch0, xisBranch1, xisBranch2,
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    pcA, pcB, pcC, pcD, pcE, pcF, xpc0, xpc1, xpc2, takb0, takb1, takb2,
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    predict_takenA, predict_takenB, predict_takenC, predict_takenD,
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    predict_takenE, predict_takenF);
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parameter AMSB=63;
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parameter DBW=32;
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input rst;
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input clk;
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input en;
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input xisBranch0;
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input xisBranch1;
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input xisBranch2;
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input [AMSB:0] pcA;
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input [AMSB:0] pcB;
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input [AMSB:0] pcC;
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input [AMSB:0] pcD;
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input [AMSB:0] pcE;
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input [AMSB:0] pcF;
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input [AMSB:0] xpc0;
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input [AMSB:0] xpc1;
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input [AMSB:0] xpc2;
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input takb0;
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input takb1;
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input takb2;
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output predict_takenA;
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output predict_takenB;
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output predict_takenC;
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output predict_takenD;
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output predict_takenE;
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output predict_takenF;
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integer n;
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reg [AMSB:0] pcs [0:31];
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reg [AMSB:0] pc;
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reg takb;
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reg [4:0] pcshead,pcstail;
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reg wrhist;
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reg [2:0] gbl_branch_hist;
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reg [1:0] branch_history_table [511:0];
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// For simulation only, initialize the history table to zeros.
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// In the real world we don't care.
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initial begin
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    gbl_branch_hist = 3'b000;
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        for (n = 0; n < 512; n = n + 1)
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                branch_history_table[n] = 3;
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end
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wire [8:0] bht_wa = {pc[7:1],gbl_branch_hist[2:1]};              // write address
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wire [8:0] bht_raA = {pcA[7:1],gbl_branch_hist[2:1]};    // read address (IF stage)
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wire [8:0] bht_raB = {pcB[7:1],gbl_branch_hist[2:1]};    // read address (IF stage)
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wire [8:0] bht_raC = {pcC[7:1],gbl_branch_hist[2:1]};    // read address (IF stage)
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wire [8:0] bht_raD = {pcD[7:1],gbl_branch_hist[2:1]};    // read address (IF stage)
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wire [8:0] bht_raE = {pcE[7:1],gbl_branch_hist[2:1]};    // read address (IF stage)
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wire [8:0] bht_raF = {pcF[7:1],gbl_branch_hist[2:1]};    // read address (IF stage)
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wire [1:0] bht_xbits = branch_history_table[bht_wa];
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wire [1:0] bht_ibitsA = branch_history_table[bht_raA];
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wire [1:0] bht_ibitsB = branch_history_table[bht_raB];
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wire [1:0] bht_ibitsC = branch_history_table[bht_raC];
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wire [1:0] bht_ibitsD = branch_history_table[bht_raD];
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wire [1:0] bht_ibitsE = branch_history_table[bht_raE];
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wire [1:0] bht_ibitsF = branch_history_table[bht_raF];
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assign predict_takenA = (bht_ibitsA==2'd0 || bht_ibitsA==2'd1) && en;
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assign predict_takenB = (bht_ibitsB==2'd0 || bht_ibitsB==2'd1) && en;
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assign predict_takenC = (bht_ibitsC==2'd0 || bht_ibitsC==2'd1) && en;
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assign predict_takenD = (bht_ibitsD==2'd0 || bht_ibitsD==2'd1) && en;
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assign predict_takenE = (bht_ibitsE==2'd0 || bht_ibitsE==2'd1) && en;
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assign predict_takenF = (bht_ibitsF==2'd0 || bht_ibitsF==2'd1) && en;
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always @(posedge clk)
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if (rst)
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        pcstail <= 5'd0;
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else begin
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        case({xisBranch0,xisBranch1,xisBranch2})
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        3'b000: ;
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        3'b001:
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                begin
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                pcs[pcstail] <= {xpc2[31:1],takb2};
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                pcstail <= pcstail + 5'd1;
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                end
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        3'b010:
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                begin
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                pcs[pcstail] <= {xpc1[31:1],takb1};
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                pcstail <= pcstail + 5'd1;
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                end
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        3'b011:
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                begin
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                pcs[pcstail] <= {xpc1[31:1],takb1};
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                pcs[pcstail+1] <= {xpc2[31:1],takb2};
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                pcstail <= pcstail + 5'd2;
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                end
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        3'b100:
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                begin
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                pcs[pcstail] <= {xpc0[31:1],takb0};
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                pcstail <= pcstail + 5'd1;
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                end
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        3'b101:
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                begin
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                pcs[pcstail] <= {xpc0[31:1],takb0};
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                pcs[pcstail+1] <= {xpc2[31:1],takb2};
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                pcstail <= pcstail + 5'd2;
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                end
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        3'b110:
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                begin
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                pcs[pcstail] <= {xpc0[31:1],takb0};
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                pcs[pcstail+1] <= {xpc1[31:1],takb1};
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                pcstail <= pcstail + 5'd2;
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                end
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        3'b111:
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                begin
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                pcs[pcstail] <= {xpc0[31:1],takb0};
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                pcs[pcstail+1] <= {xpc1[31:1],takb1};
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                pcs[pcstail+2] <= {xpc2[31:1],takb2};
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                pcstail <= pcstail + 5'd3;
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                end
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        endcase
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end
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always @(posedge clk)
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if (rst)
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        pcshead <= 5'd0;
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else begin
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        wrhist <= 1'b0;
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        if (pcshead != pcstail) begin
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                pc <= pcs[pcshead];
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                takb <= pcs[pcshead][0];
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                wrhist <= 1'b1;
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                pcshead <= pcshead + 5'd1;
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        end
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end
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// Two bit saturating counter
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// If taking a branch in commit0 then a following branch
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// in commit1 is never encountered. So only update for
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// commit1 if commit0 is not taken.
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reg [1:0] xbits_new;
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always @*
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if (wrhist) begin
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        if (takb) begin
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                if (bht_xbits != 2'd1)
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                        xbits_new <= bht_xbits + 2'd1;
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                else
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                        xbits_new <= bht_xbits;
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        end
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        else begin
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                if (bht_xbits != 2'd2)
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                        xbits_new <= bht_xbits - 2'd1;
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                else
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                        xbits_new <= bht_xbits;
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        end
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end
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else
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        xbits_new <= bht_xbits;
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always @(posedge clk)
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if (rst)
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        gbl_branch_hist <= 3'b000;
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else begin
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  if (en) begin
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    if (wrhist) begin
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      gbl_branch_hist <= {gbl_branch_hist[1:0],takb};
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      branch_history_table[bht_wa] <= xbits_new;
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    end
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        end
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end
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endmodule
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