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// ============================================================================
//        __
//   \\__/ o\    (C) 2018-2019  Robert Finch, Waterloo
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//
//      FT64_fetchbuf_x1.v
//
// This source file is free software: you can redistribute it and/or modify 
// it under the terms of the GNU Lesser General Public License as published 
// by the Free Software Foundation, either version 3 of the License, or     
// (at your option) any later version.                                      
//                                                                          
// This source file is distributed in the hope that it will be useful,      
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
// GNU General Public License for more details.                             
//                                                                          
// You should have received a copy of the GNU General Public License        
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
//
// ============================================================================
//
`include "FT64_config.vh"
`include "FT64_defines.vh"
 
// FETCH
//
// fetch exactly one instructions from memory into the fetch buffer
// unless either one of the buffers is still full, in which case we
// do nothing (kinda like alpha approach)
//
module FT64_fetchbuf_x1(rst, clk4x, clk, fcu_clk,
        cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,
        cmpgrp,
        freezePC, thread_en, pred_on,
        regLR,
  insn0, phit,
  threadx,
  branchmiss, misspc, branchmiss_thrd, predict_taken0,
  predict_takenA, predict_takenB,
  queued1, queuedNop,
  pc0, fetchbuf, fetchbufA_v, fetchbufB_v,
  fetchbufA_instr, fetchbufA_pc, fetchbufA_pbyte,
  fetchbufB_instr, fetchbufB_pc, fetchbufB_pbyte,
  fetchbuf0_instr, fetchbuf0_insln,
  fetchbuf0_thrd,
  fetchbuf0_pc,
  fetchbuf0_v,
  fetchbuf0_pbyte,
  codebuf0,
  btgtA, btgtB,
  nop_fetchbuf,
  take_branch0,
  stompedRets,
  panic
);
parameter AMSB = `AMSB;
parameter RSTPC = 64'hFFFFFFFFFFFC0100;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
input rst;
input clk4x;
input clk;
input fcu_clk;
input cs_i;
input cyc_i;
input stb_i;
output ack_o;
input we_i;
input [15:0] adr_i;
input [55:0] dat_i;
input [2:0] cmpgrp;
input freezePC;
input thread_en;
input pred_on;
input [4:0] regLR;
input [55:0] insn0;
input phit;
output threadx;
input branchmiss;
input [AMSB:0] misspc;
input branchmiss_thrd;
output predict_taken0;
input predict_takenA;
input predict_takenB;
input queued1;
input queuedNop;
output reg [AMSB:0] pc0;
output reg fetchbuf;
output reg fetchbufA_v;
output reg fetchbufB_v;
output fetchbuf0_thrd;
output reg [47:0] fetchbufA_instr;
output reg [7:0] fetchbufA_pbyte;
output reg [47:0] fetchbufB_instr;
output reg [7:0] fetchbufB_pbyte;
output reg [AMSB:0] fetchbufA_pc;
output reg [AMSB:0] fetchbufB_pc;
output [47:0] fetchbuf0_instr;
output [AMSB:0] fetchbuf0_pc;
output [2:0] fetchbuf0_insln;
output fetchbuf0_v;
output [7:0] fetchbuf0_pbyte;
input [55:0] codebuf0;
input [AMSB:0] btgtA;
input [AMSB:0] btgtB;
input [3:0] nop_fetchbuf;
output take_branch0;
input [3:0] stompedRets;
output reg [3:0] panic;
integer n;
 
reg [55:0] cinsn0;
 
//`include "FT64_decode.vh"
 
function IsBranch;
input [47:0] isn;
casex(isn[`INSTRUCTION_OP])
`Bcc:   IsBranch = TRUE;
`BLcc:  IsBranch = TRUE;
`BBc:   IsBranch = TRUE;
`BEQI:  IsBranch = TRUE;
`BNEI:  IsBranch = TRUE;
`BCHK:  IsBranch = TRUE;
default: IsBranch = FALSE;
endcase
endfunction
 
function IsJAL;
input [47:0] isn;
IsJAL = isn[`INSTRUCTION_OP]==`JAL;
endfunction
 
function IsJmp;
input [47:0] isn;
IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
endfunction
 
function IsCall;
input [47:0] isn;
IsCall = isn[`INSTRUCTION_OP]==`CALL && isn[7]==1'b0;
endfunction
 
function IsRet;
input [47:0] isn;
IsRet = isn[`INSTRUCTION_OP]==`RET;
endfunction
 
function IsBrk;
input [47:0] isn;
IsBrk = isn[`INSTRUCTION_OP]==`BRK;
endfunction
 
function IsRTI;
input [47:0] isn;
IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
endfunction
 
function IsExec;
input [47:0] isn;
if (isn[7:6]==2'b00)
        case(isn[`INSTRUCTION_OP])
        `R2:
                case(isn[`INSTRUCTION_S2])
                `R1:
                        case(isn[22:18])
                        `EXEC:  IsExec = TRUE;
                        default:        IsExec = FALSE;
                        endcase
                default:        IsExec = FALSE;
                endcase
        default:        IsExec = FALSE;
        endcase
else
        IsExec = FALSE;
endfunction
 
function [2:0] fnInsLength;
input [47:0] ins;
`ifdef SUPPORT_DCI
if (ins[`INSTRUCTION_OP]==`CMPRSSD)
        fnInsLength = 3'd2 | pred_on;
else
`endif
        case(ins[7:6])
        2'd0:   fnInsLength = 3'd4 | pred_on;
        2'd1:   fnInsLength = 3'd6 | pred_on;
        default:        fnInsLength = 3'd2 | pred_on;
        endcase
endfunction
 
wire [2:0] fetchbufA_inslen;
wire [2:0] fetchbufB_inslen;
FT64_InsLength uilA (fetchbufA_instr, fetchbufA_inslen, pred_on);
FT64_InsLength uilB (fetchbufB_instr, fetchbufB_inslen, pred_on);
 
wire [47:0] xinsn0;
 
FT64_iexpander ux1
(
        .cinstr(pred_on ? insn0[23:8] : insn0[15:0]),
        .expand(xinsn0)
);
 
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
// Table of decompressed instructions.
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
assign ack_o = cs_i & cyc_i & stb_i;
`ifdef SUPPORT_DCI
reg [47:0] DecompressTable [0:2047];
always @(posedge clk)
        if (cs_i & cyc_i & stb_i & we_i)
                DecompressTable[adr_i[12:3]] <= dat_i[47:0];
wire [47:0] expand0 = DecompressTable[{cmpgrp,pred_on ? insn0[23:16]:insn0[15:8]}];
`endif
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
 
reg thread;
reg stompedRet;
reg ret0Counted;
wire [AMSB:0] retpc0;
 
assign predict_taken0 = (fetchbuf==1'b0) ? ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA}  == {`VAL, `TRUE, `TRUE})
                                                                                                                                                                 : ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB}  == {`VAL, `TRUE, `TRUE});
 
reg [AMSB:0] branch_pcA;
reg [AMSB:0] branch_pcB;
 
always @*
begin
case(fetchbufA_instr[`INSTRUCTION_OP])
`RET:           branch_pcA = retpc0;
`JMP,`CALL:
        begin
`ifdef JMP40
        branch_pcA[39:0] = fetchbufA_instr[6] ? {fetchbufA_instr[47:8]} : {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
`else
        branch_pcA[39:0] = {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
`endif
        branch_pcA[63:40] = fetchbufA_pc[63:40];
        end
`R2:            branch_pcA = btgtA;     // RTI
`BRK,`JAL:      branch_pcA = btgtA;
default:
        begin
        branch_pcA[31:0] = fetchbufA_pc[31:0] +
                ((fetchbufA_instr[7:6]==2'b01) ? {{4{fetchbufA_instr[47]}},fetchbufA_instr[47:23],fetchbufA_instr[17:16],1'b0} : {{20{fetchbufA_instr[31]}},fetchbufA_instr[31:23],fetchbufA_instr[17:16],1'b0});
        branch_pcA[63:32] = fetchbufA_pc[63:32];
        end
endcase
end
 
always @*
begin
case(fetchbufB_instr[`INSTRUCTION_OP])
`RET:           branch_pcB = retpc0;
`JMP,`CALL:
        begin
`ifdef JMP40
                branch_pcB[39:0] = fetchbufB_instr[6] ? {fetchbufB_instr[47:8]} : {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
`else
                branch_pcB[39:0] = {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
`endif
                branch_pcB[63:40] = fetchbufB_pc[63:40];
        end
`R2:            branch_pcB = btgtB;     // RTI
`BRK,`JAL:      branch_pcB = btgtB;
default:
        begin
        branch_pcB[31:0] = fetchbufB_pc[31:0] +
                ((fetchbufB_instr[7:6]==2'b01) ? {{4{fetchbufB_instr[47]}},fetchbufB_instr[47:23],fetchbufB_instr[17:16],1'b0} : {{20{fetchbufB_instr[31]}},fetchbufB_instr[31:23],fetchbufB_instr[17:16],1'b0});
        branch_pcB[63:32] = fetchbufB_pc[63:32];
        end
endcase
end
 
wire take_branchA = ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA}  == {`VAL, `TRUE, `TRUE}) || ((
`ifdef FCU_ENH
                           IsRet(fetchbufA_instr)
                        || IsRTI(fetchbufA_instr)|| IsBrk(fetchbufA_instr) || IsJAL(fetchbufA_instr) ||
`endif
                           IsJmp(fetchbufA_instr)||IsCall(fetchbufA_instr)) &&
                        fetchbufA_v);
wire take_branchB = ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB}  == {`VAL, `TRUE, `TRUE}) || ((
`ifdef FCU_ENH
                           IsRet(fetchbufB_instr)
                        || IsRTI(fetchbufB_instr)|| IsBrk(fetchbufB_instr) || IsJAL(fetchbufB_instr) ||
`endif
                           IsJmp(fetchbufB_instr)||IsCall(fetchbufB_instr)) &&
                        fetchbufB_v);
 
wire take_branch = (fetchbuf==1'b0) ? take_branchA : take_branchB;
assign take_branch0 = take_branch;
 
/*
always @*
begin
        pc0 <= thread_en ? (fetchbuf ? pc0b : pc0a) : pc0a;
        pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;
end
*/
assign threadx = fetchbuf;
 
`ifdef FCU_ENH
FT64_RSB #(AMSB) ursb1
(
        .rst(rst),
        .clk(fcu_clk),
        .regLR(regLR),
        .queued1(queued1),
        .queued2(1'b0),
        .fetchbuf0_v(fetchbuf0_v),
        .fetchbuf0_pc(fetchbuf0_pc),
        .fetchbuf0_instr(fetchbuf0_instr),
        .fetchbuf1_v(1'b0),
        .fetchbuf1_pc(RSTPC),
        .fetchbuf1_instr(`NOP_INSN),
        .stompedRets(stompedRets),
        .stompedRet(stompedRet),
        .pc(retpc0)
);
 
`else
assign retpc0 = RSTPC;
assign retpc1 = RSTPC;
`endif
 
wire peclk, neclk;
edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());
 
reg did_branch;
 
always @(posedge clk)
if (rst) begin
        pc0 <= RSTPC;
        fetchbufA_v <= 1'b0;
        fetchbufB_v <= 1'b0;
        fetchbuf <= 1'b0;
        panic <= `PANIC_NONE;
        did_branch <= 1'b0;
end
else begin
 
        did_branch <= take_branch & ~branchmiss;
 
        begin
 
        // On a branch miss with threading enabled all fectch buffers are
        // invalidated even though the data in the fetch buffer would be valid
        // for the thread that isn't in a branchmiss state. This is done to
        // keep things simple. For the thread that doesn't miss the current
        // data for the fetch buffer needs to be retrieved again, so the pc
        // for that thread is assigned the current fetchbuf pc.
        // For the thread that misses the pc is simply assigned the misspc.
        if (branchmiss) begin
                pc0 <= misspc;
                fetchbufA_v <= `INV;
                fetchbufB_v <= `INV;
                fetchbuf <= 1'b0;
                $display("********************");
                $display("********************");
                $display("********************");
                $display("Branch miss");
                $display("misspc=%h", misspc);
                $display("********************");
                $display("********************");
                $display("********************");
        end
//      else if (cinsn0[`INSTRUCTION_OP]==`CALL || cinsn0[`INSTRUCTION_OP]==`JMP) begin
//              pc0[31:0] = cinsn0[6] ? {cinsn0[47:8]} : {pc0[31:24],cinsn0[31:8]};
//              fetchbufA_v <= `INV;
//              fetchbufB_v <= `INV;
//              fetchbuf <= 1'b0;
//      end
        else if (take_branch) begin
    if (fetchbuf == 1'b0) begin
        // In this case fetchbufA must be valid, or take_branch wouldn't be.
        case(fetchbufB_v)
        1'b0:
                begin
                                        pc0 <= branch_pcA;
                                  fetchbufA_v <= !(queued1|queuedNop);  // if it can be queued, it will
                                  fetchbuf <= (queued1|queuedNop);
                end
        1'b1:
                        if (did_branch) begin
                                  fetchbufA_v <= !(queued1|queuedNop);  // if it can be queued, it will
                                  fetchbuf <= (queued1|queuedNop);
                                  FetchB();
                        end
                        else
                        begin
                                        pc0 <= branch_pcA;
                                  fetchbufA_v <= !(queued1|queuedNop);  // if it can be queued, it will
                                        fetchbufB_v <= `INV;
                                  fetchbuf <= (queued1|queuedNop);
                        end
        endcase
                end
    else begin
        case(fetchbufA_v)
        1'b0:
                begin
                                        pc0 <= branch_pcB;
                                  fetchbufB_v <= !(queued1|queuedNop);
                                  fetchbuf <= !(queued1|queuedNop);
                                end
                        1'b1:
                                if (did_branch) begin
                                  fetchbufB_v <= !(queued1|queuedNop);
                                  fetchbuf <= ~(queued1|queuedNop);
                                  FetchA();
                                end
                                else
                                begin
                                        pc0 <= branch_pcB;
                                  fetchbufB_v <= !(queued1|queuedNop);
                                        fetchbufA_v <= `INV;
                                  fetchbuf <= !(queued1|queuedNop);
                                end
                        endcase
                end
        end // if branch
 
        else begin      // there is no branchback in the system
    // update fetchbufX_v and fetchbuf ... relatively simple, as
    // there are no backwards branches in the mix
          if (fetchbuf == 1'b0) case ({fetchbufA_v, (queued1|queuedNop)})
                2'b00: ;        // do nothing
                2'b10: ;
                2'b11: begin fetchbufA_v <= `INV; fetchbuf <= ~fetchbuf; end
                default:  panic <= `PANIC_INVALIDIQSTATE;
                endcase
          else case ({fetchbufB_v, (queued1|queuedNop)})
                2'b00: ;        // do nothing
                2'b10: ;
                2'b11: begin fetchbufB_v <= `INV; fetchbuf <= ~fetchbuf; end
                default:  panic <= `PANIC_INVALIDIQSTATE;
                endcase
    //
    // get data iff the fetch buffers are empty
    //
    if (fetchbufA_v == `INV) begin
        FetchA();
        // fetchbuf steering logic correction
        if (fetchbufB_v==`INV && phit)
          fetchbuf <= 1'b0;
    end
    else if (fetchbufB_v == `INV) begin
            FetchB();
          end
        end
  //
  // get data iff the fetch buffers are empty
  //
  if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
        FetchA();
    fetchbuf <= 1'b0;
  end
//  // Steer fetchbuf to the valid buffer.
//  else if (fetchbufB_v == `INV)
//      fetchbuf <= 1'b0;
//  else if (fetchbufA_v == `INV)
//              fetchbuf <= 1'b1;
//  else if (fetchbufA_v == `INV) begin
//      FetchA();
//      end
//      else if (fetchbufB_v == `INV) begin
//              FetchB();
//      end
end
 
        // The fetchbuffer is invalidated at the end of a vector instruction
        // queue.
        if (nop_fetchbuf[0])  fetchbufA_v <= `INV;
        if (nop_fetchbuf[1])  fetchbufB_v <= `INV;
end
 
assign fetchbuf0_instr = (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufB_instr;
assign fetchbuf0_insln = (fetchbuf == 1'b0) ? fetchbufA_inslen: fetchbufB_inslen;
assign fetchbuf0_v     = (fetchbuf == 1'b0) ? fetchbufA_v     : fetchbufB_v    ;
assign fetchbuf0_pc    = (fetchbuf == 1'b0) ? fetchbufA_pc    : fetchbufB_pc   ;
assign fetchbuf0_thrd  = 1'b0;
assign fetchbuf0_pbyte = (fetchbuf == 1'b0) ? fetchbufA_pbyte : fetchbufB_pbyte;
 
reg [2:0] insln0;
always @*
begin
`ifdef SUPPORT_DCI
        if (insn0[5:0]==`CMPRSSD)
                insln0 <= 3'd2 | pred_on;
        else
`endif
        if (IsExec(insn0))
                insln0 <= fnInsLength(codebuf0);        //???? should be 4?
        else
                insln0 <= fnInsLength(insn0);
end
 
 
always @*
begin
`ifdef SUPPORT_DCI
        if (insn0[13:8]==`CMPRSSD && pred_on)
                cinsn0 <= expand0;
        else if (insn0[5:0]==`CMPRSSD && !pred_on)
                cinsn0 <= expand0;
        else
`endif
        if (IsExec(insn0) && !pred_on)
                cinsn0 <= codebuf0;
        else if (IsExec(insn0[55:8]) && pred_on)
                cinsn0 <= codebuf0;
        else if (insn0[15] & pred_on)
                cinsn0 <= {xinsn0,insn0[7:0]};
        else if (insn0[7] & ~pred_on)
                cinsn0 <= xinsn0;
        else
                cinsn0 <= insn0;
end
 
task FetchA;
begin
        fetchbufA_instr <= pred_on ? cinsn0[55:8] : cinsn0[47:0];
        fetchbufA_pbyte = cinsn0[7:0];
        fetchbufA_v <= `VAL;
        fetchbufA_pc <= pc0;
        if (phit && ~freezePC)
                pc0 <= pc0 + insln0;
        else
                pc0 <= pc0;
end
endtask
 
task FetchB;
begin
        fetchbufB_instr <= pred_on ? cinsn0[55:8] : cinsn0[47:0];
        fetchbufB_pbyte = cinsn0[7:0];
        fetchbufB_v <= `VAL;
        fetchbufB_pc <= pc0;
        if (phit && ~freezePC)
                pc0 <= pc0 + insln0;
        else
                pc0 <= pc0;
end
endtask
 
endmodule

Line No.	Rev	Author	Line
1	60	robfinch	`// ============================================================================`
2			`// __`
3	61	robfinch	`// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo`
4	60	robfinch	`// \ __ / All rights reserved.`
5			`// \/_// robfinch<remove>@finitron.ca`
6			`// \|\|`
7			`//`
8			`// FT64_fetchbuf_x1.v`
9			`//`
10			`// This source file is free software: you can redistribute it and/or modify`
11			`// it under the terms of the GNU Lesser General Public License as published`
12			`// by the Free Software Foundation, either version 3 of the License, or`
13			`// (at your option) any later version.`
14			`//`
15			`// This source file is distributed in the hope that it will be useful,`
16			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
17			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
18			`// GNU General Public License for more details.`
19			`//`
20			`// You should have received a copy of the GNU General Public License`
21			`// along with this program. If not, see <http://www.gnu.org/licenses/>.`
22			`//`
23			`// ============================================================================`
24			`//`
25			`include "FT64_config.vh"
26			`include "FT64_defines.vh"
27
28			`// FETCH`
29			`//`
30			`// fetch exactly one instructions from memory into the fetch buffer`
31			`// unless either one of the buffers is still full, in which case we`
32			`// do nothing (kinda like alpha approach)`
33			`//`
34			`module FT64_fetchbuf_x1(rst, clk4x, clk, fcu_clk,`
35			`cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i,`
36			`cmpgrp,`
37			`freezePC, thread_en, pred_on,`
38			`regLR,`
39			`insn0, phit,`
40			`threadx,`
41			`branchmiss, misspc, branchmiss_thrd, predict_taken0,`
42			`predict_takenA, predict_takenB,`
43			`queued1, queuedNop,`
44			`pc0, fetchbuf, fetchbufA_v, fetchbufB_v,`
45			`fetchbufA_instr, fetchbufA_pc, fetchbufA_pbyte,`
46			`fetchbufB_instr, fetchbufB_pc, fetchbufB_pbyte,`
47			`fetchbuf0_instr, fetchbuf0_insln,`
48			`fetchbuf0_thrd,`
49			`fetchbuf0_pc,`
50			`fetchbuf0_v,`
51			`fetchbuf0_pbyte,`
52			`codebuf0,`
53			`btgtA, btgtB,`
54			`nop_fetchbuf,`
55			`take_branch0,`
56			`stompedRets,`
57			`panic`
58			`);`
59			parameter AMSB = `AMSB;
60			`parameter RSTPC = 64'hFFFFFFFFFFFC0100;`
61			`parameter TRUE = 1'b1;`
62			`parameter FALSE = 1'b0;`
63			`input rst;`
64			`input clk4x;`
65			`input clk;`
66			`input fcu_clk;`
67			`input cs_i;`
68			`input cyc_i;`
69			`input stb_i;`
70			`output ack_o;`
71			`input we_i;`
72			`input [15:0] adr_i;`
73			`input [55:0] dat_i;`
74			`input [2:0] cmpgrp;`
75			`input freezePC;`
76			`input thread_en;`
77			`input pred_on;`
78			`input [4:0] regLR;`
79			`input [55:0] insn0;`
80			`input phit;`
81			`output threadx;`
82			`input branchmiss;`
83			`input [AMSB:0] misspc;`
84			`input branchmiss_thrd;`
85			`output predict_taken0;`
86			`input predict_takenA;`
87			`input predict_takenB;`
88			`input queued1;`
89			`input queuedNop;`
90			`output reg [AMSB:0] pc0;`
91			`output reg fetchbuf;`
92			`output reg fetchbufA_v;`
93			`output reg fetchbufB_v;`
94			`output fetchbuf0_thrd;`
95			`output reg [47:0] fetchbufA_instr;`
96			`output reg [7:0] fetchbufA_pbyte;`
97			`output reg [47:0] fetchbufB_instr;`
98			`output reg [7:0] fetchbufB_pbyte;`
99			`output reg [AMSB:0] fetchbufA_pc;`
100			`output reg [AMSB:0] fetchbufB_pc;`
101			`output [47:0] fetchbuf0_instr;`
102			`output [AMSB:0] fetchbuf0_pc;`
103			`output [2:0] fetchbuf0_insln;`
104			`output fetchbuf0_v;`
105			`output [7:0] fetchbuf0_pbyte;`
106			`input [55:0] codebuf0;`
107			`input [AMSB:0] btgtA;`
108			`input [AMSB:0] btgtB;`
109			`input [3:0] nop_fetchbuf;`
110			`output take_branch0;`
111			`input [3:0] stompedRets;`
112			`output reg [3:0] panic;`
113			`integer n;`
114
115			`reg [55:0] cinsn0;`
116
117			//`include "FT64_decode.vh"
118
119			`function IsBranch;`
120			`input [47:0] isn;`
121			casex(isn[`INSTRUCTION_OP])
122			`Bcc: IsBranch = TRUE;
123	61	robfinch	`BLcc: IsBranch = TRUE;
124	60	robfinch	`BBc: IsBranch = TRUE;
125			`BEQI: IsBranch = TRUE;
126	61	robfinch	`BNEI: IsBranch = TRUE;
127	60	robfinch	`BCHK: IsBranch = TRUE;
128			`default: IsBranch = FALSE;`
129			`endcase`
130			`endfunction`
131
132			`function IsJAL;`
133			`input [47:0] isn;`
134			IsJAL = isn[`INSTRUCTION_OP]==`JAL;
135			`endfunction`
136
137			`function IsJmp;`
138			`input [47:0] isn;`
139	61	robfinch	IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
140	60	robfinch	`endfunction`
141
142			`function IsCall;`
143			`input [47:0] isn;`
144	61	robfinch	IsCall = isn[`INSTRUCTION_OP]==`CALL && isn[7]==1'b0;
145	60	robfinch	`endfunction`
146
147			`function IsRet;`
148			`input [47:0] isn;`
149			IsRet = isn[`INSTRUCTION_OP]==`RET;
150			`endfunction`
151
152			`function IsBrk;`
153			`input [47:0] isn;`
154			IsBrk = isn[`INSTRUCTION_OP]==`BRK;
155			`endfunction`
156
157			`function IsRTI;`
158			`input [47:0] isn;`
159			IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
160			`endfunction`
161
162	61	robfinch	`function IsExec;`
163			`input [47:0] isn;`
164			`if (isn[7:6]==2'b00)`
165			case(isn[`INSTRUCTION_OP])
166			`R2:
167			case(isn[`INSTRUCTION_S2])
168			`R1:
169			`case(isn[22:18])`
170			`EXEC: IsExec = TRUE;
171			`default: IsExec = FALSE;`
172			`endcase`
173			`default: IsExec = FALSE;`
174			`endcase`
175			`default: IsExec = FALSE;`
176			`endcase`
177			`else`
178			`IsExec = FALSE;`
179			`endfunction`
180
181	60	robfinch	`function [2:0] fnInsLength;`
182			`input [47:0] ins;`
183			`ifdef SUPPORT_DCI
184			if (ins[`INSTRUCTION_OP]==`CMPRSSD)
185			`fnInsLength = 3'd2 \| pred_on;`
186			`else`
187			`endif
188			`case(ins[7:6])`
189			`2'd0: fnInsLength = 3'd4 \| pred_on;`
190			`2'd1: fnInsLength = 3'd6 \| pred_on;`
191			`default: fnInsLength = 3'd2 \| pred_on;`
192			`endcase`
193			`endfunction`
194
195			`wire [2:0] fetchbufA_inslen;`
196			`wire [2:0] fetchbufB_inslen;`
197			`FT64_InsLength uilA (fetchbufA_instr, fetchbufA_inslen, pred_on);`
198			`FT64_InsLength uilB (fetchbufB_instr, fetchbufB_inslen, pred_on);`
199
200			`wire [47:0] xinsn0;`
201
202			`FT64_iexpander ux1`
203			`(`
204			`.cinstr(pred_on ? insn0[23:8] : insn0[15:0]),`
205			`.expand(xinsn0)`
206			`);`
207
208
209			`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
210			`// Table of decompressed instructions.`
211			`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
212			`assign ack_o = cs_i & cyc_i & stb_i;`
213			`ifdef SUPPORT_DCI
214			`reg [47:0] DecompressTable [0:2047];`
215			`always @(posedge clk)`
216			`if (cs_i & cyc_i & stb_i & we_i)`
217			`DecompressTable[adr_i[12:3]] <= dat_i[47:0];`
218			`wire [47:0] expand0 = DecompressTable[{cmpgrp,pred_on ? insn0[23:16]:insn0[15:8]}];`
219			`endif
220
221			`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
222			`// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -`
223
224			`reg thread;`
225			`reg stompedRet;`
226			`reg ret0Counted;`
227			`wire [AMSB:0] retpc0;`
228
229			assign predict_taken0 = (fetchbuf==1'b0) ? ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE})
230			: ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE});
231
232			`reg [AMSB:0] branch_pcA;`
233			`reg [AMSB:0] branch_pcB;`
234
235			`always @*`
236			`begin`
237			case(fetchbufA_instr[`INSTRUCTION_OP])
238			`RET: branch_pcA = retpc0;
239			`JMP,`CALL:
240			`begin`
241	61	robfinch	`ifdef JMP40
242	60	robfinch	`branch_pcA[39:0] = fetchbufA_instr[6] ? {fetchbufA_instr[47:8]} : {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};`
243	61	robfinch	`else
244			`branch_pcA[39:0] = {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};`
245			`endif
246	60	robfinch	`branch_pcA[63:40] = fetchbufA_pc[63:40];`
247			`end`
248			`R2: branch_pcA = btgtA; // RTI
249			`BRK,`JAL: branch_pcA = btgtA;
250			`default:`
251			`begin`
252	61	robfinch	`branch_pcA[31:0] = fetchbufA_pc[31:0] +`
253			`((fetchbufA_instr[7:6]==2'b01) ? {{4{fetchbufA_instr[47]}},fetchbufA_instr[47:23],fetchbufA_instr[17:16],1'b0} : {{20{fetchbufA_instr[31]}},fetchbufA_instr[31:23],fetchbufA_instr[17:16],1'b0});`
254	60	robfinch	`branch_pcA[63:32] = fetchbufA_pc[63:32];`
255			`end`
256			`endcase`
257			`end`
258
259			`always @*`
260			`begin`
261			case(fetchbufB_instr[`INSTRUCTION_OP])
262			`RET: branch_pcB = retpc0;
263			`JMP,`CALL:
264			`begin`
265	61	robfinch	`ifdef JMP40
266	60	robfinch	`branch_pcB[39:0] = fetchbufB_instr[6] ? {fetchbufB_instr[47:8]} : {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};`
267	61	robfinch	`else
268			`branch_pcB[39:0] = {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};`
269			`endif
270	60	robfinch	`branch_pcB[63:40] = fetchbufB_pc[63:40];`
271			`end`
272			`R2: branch_pcB = btgtB; // RTI
273			`BRK,`JAL: branch_pcB = btgtB;
274			`default:`
275			`begin`
276	61	robfinch	`branch_pcB[31:0] = fetchbufB_pc[31:0] +`
277			`((fetchbufB_instr[7:6]==2'b01) ? {{4{fetchbufB_instr[47]}},fetchbufB_instr[47:23],fetchbufB_instr[17:16],1'b0} : {{20{fetchbufB_instr[31]}},fetchbufB_instr[31:23],fetchbufB_instr[17:16],1'b0});`
278	60	robfinch	`branch_pcB[63:32] = fetchbufB_pc[63:32];`
279			`end`
280			`endcase`
281			`end`
282
283			wire take_branchA = ({fetchbufA_v, IsBranch(fetchbufA_instr), predict_takenA} == {`VAL, `TRUE, `TRUE}) \|\| ((
284			`ifdef FCU_ENH
285			`IsRet(fetchbufA_instr)`
286			`\|\| IsRTI(fetchbufA_instr)\|\| IsBrk(fetchbufA_instr) \|\| IsJAL(fetchbufA_instr) \|\|`
287			`endif
288			`IsJmp(fetchbufA_instr)\|\|IsCall(fetchbufA_instr)) &&`
289			`fetchbufA_v);`
290			wire take_branchB = ({fetchbufB_v, IsBranch(fetchbufB_instr), predict_takenB} == {`VAL, `TRUE, `TRUE}) \|\| ((
291			`ifdef FCU_ENH
292			`IsRet(fetchbufB_instr)`
293			`\|\| IsRTI(fetchbufB_instr)\|\| IsBrk(fetchbufB_instr) \|\| IsJAL(fetchbufB_instr) \|\|`
294			`endif
295			`IsJmp(fetchbufB_instr)\|\|IsCall(fetchbufB_instr)) &&`
296			`fetchbufB_v);`
297
298			`wire take_branch = (fetchbuf==1'b0) ? take_branchA : take_branchB;`
299			`assign take_branch0 = take_branch;`
300
301			`/*`
302			`always @*`
303			`begin`
304			`pc0 <= thread_en ? (fetchbuf ? pc0b : pc0a) : pc0a;`
305			`pc1 <= thread_en ? (fetchbuf ? pc1b : pc1a) : pc1a;`
306			`end`
307			`*/`
308			`assign threadx = fetchbuf;`
309
310			`ifdef FCU_ENH
311			`FT64_RSB #(AMSB) ursb1`
312			`(`
313			`.rst(rst),`
314			`.clk(fcu_clk),`
315			`.regLR(regLR),`
316			`.queued1(queued1),`
317			`.queued2(1'b0),`
318			`.fetchbuf0_v(fetchbuf0_v),`
319			`.fetchbuf0_pc(fetchbuf0_pc),`
320			`.fetchbuf0_instr(fetchbuf0_instr),`
321			`.fetchbuf1_v(1'b0),`
322			`.fetchbuf1_pc(RSTPC),`
323			.fetchbuf1_instr(`NOP_INSN),
324			`.stompedRets(stompedRets),`
325			`.stompedRet(stompedRet),`
326			`.pc(retpc0)`
327			`);`
328
329			`else
330			`assign retpc0 = RSTPC;`
331			`assign retpc1 = RSTPC;`
332			`endif
333
334			`wire peclk, neclk;`
335			`edge_det ued1 (.rst(rst), .clk(clk4x), .ce(1'b1), .i(clk), .pe(peclk), .ne(neclk), .ee());`
336
337			`reg did_branch;`
338
339			`always @(posedge clk)`
340			`if (rst) begin`
341			`pc0 <= RSTPC;`
342			`fetchbufA_v <= 1'b0;`
343			`fetchbufB_v <= 1'b0;`
344			`fetchbuf <= 1'b0;`
345			panic <= `PANIC_NONE;
346			`did_branch <= 1'b0;`
347			`end`
348			`else begin`
349
350			`did_branch <= take_branch & ~branchmiss;`
351
352			`begin`
353
354			`// On a branch miss with threading enabled all fectch buffers are`
355			`// invalidated even though the data in the fetch buffer would be valid`
356			`// for the thread that isn't in a branchmiss state. This is done to`
357			`// keep things simple. For the thread that doesn't miss the current`
358			`// data for the fetch buffer needs to be retrieved again, so the pc`
359			`// for that thread is assigned the current fetchbuf pc.`
360			`// For the thread that misses the pc is simply assigned the misspc.`
361			`if (branchmiss) begin`
362			`pc0 <= misspc;`
363			fetchbufA_v <= `INV;
364			fetchbufB_v <= `INV;
365			`fetchbuf <= 1'b0;`
366			`$display("********************");`
367			`$display("********************");`
368			`$display("********************");`
369			`$display("Branch miss");`
370			`$display("misspc=%h", misspc);`
371			`$display("********************");`
372			`$display("********************");`
373			`$display("********************");`
374			`end`
375			// else if (cinsn0[`INSTRUCTION_OP]==`CALL \|\| cinsn0[`INSTRUCTION_OP]==`JMP) begin
376			`// pc0[31:0] = cinsn0[6] ? {cinsn0[47:8]} : {pc0[31:24],cinsn0[31:8]};`
377			// fetchbufA_v <= `INV;
378			// fetchbufB_v <= `INV;
379			`// fetchbuf <= 1'b0;`
380			`// end`
381			`else if (take_branch) begin`
382			`if (fetchbuf == 1'b0) begin`
383			`// In this case fetchbufA must be valid, or take_branch wouldn't be.`
384			`case(fetchbufB_v)`
385			`1'b0:`
386			`begin`
387			`pc0 <= branch_pcA;`
388			`fetchbufA_v <= !(queued1\|queuedNop); // if it can be queued, it will`
389			`fetchbuf <= (queued1\|queuedNop);`
390			`end`
391			`1'b1:`
392			`if (did_branch) begin`
393			`fetchbufA_v <= !(queued1\|queuedNop); // if it can be queued, it will`
394			`fetchbuf <= (queued1\|queuedNop);`
395			`FetchB();`
396			`end`
397			`else`
398			`begin`
399			`pc0 <= branch_pcA;`
400			`fetchbufA_v <= !(queued1\|queuedNop); // if it can be queued, it will`
401			fetchbufB_v <= `INV;
402			`fetchbuf <= (queued1\|queuedNop);`
403			`end`
404			`endcase`
405			`end`
406			`else begin`
407			`case(fetchbufA_v)`
408			`1'b0:`
409			`begin`
410			`pc0 <= branch_pcB;`
411			`fetchbufB_v <= !(queued1\|queuedNop);`
412			`fetchbuf <= !(queued1\|queuedNop);`
413			`end`
414			`1'b1:`
415			`if (did_branch) begin`
416			`fetchbufB_v <= !(queued1\|queuedNop);`
417			`fetchbuf <= ~(queued1\|queuedNop);`
418			`FetchA();`
419			`end`
420			`else`
421			`begin`
422			`pc0 <= branch_pcB;`
423			`fetchbufB_v <= !(queued1\|queuedNop);`
424			fetchbufA_v <= `INV;
425			`fetchbuf <= !(queued1\|queuedNop);`
426			`end`
427			`endcase`
428			`end`
429			`end // if branch`
430
431			`else begin // there is no branchback in the system`
432			`// update fetchbufX_v and fetchbuf ... relatively simple, as`
433			`// there are no backwards branches in the mix`
434			`if (fetchbuf == 1'b0) case ({fetchbufA_v, (queued1\|queuedNop)})`
435			`2'b00: ; // do nothing`
436			`2'b10: ;`
437			2'b11: begin fetchbufA_v <= `INV; fetchbuf <= ~fetchbuf; end
438			default: panic <= `PANIC_INVALIDIQSTATE;
439			`endcase`
440			`else case ({fetchbufB_v, (queued1\|queuedNop)})`
441			`2'b00: ; // do nothing`
442			`2'b10: ;`
443			2'b11: begin fetchbufB_v <= `INV; fetchbuf <= ~fetchbuf; end
444			default: panic <= `PANIC_INVALIDIQSTATE;
445			`endcase`
446			`//`
447			`// get data iff the fetch buffers are empty`
448			`//`
449			if (fetchbufA_v == `INV) begin
450			`FetchA();`
451			`// fetchbuf steering logic correction`
452			if (fetchbufB_v==`INV && phit)
453			`fetchbuf <= 1'b0;`
454			`end`
455			else if (fetchbufB_v == `INV) begin
456			`FetchB();`
457			`end`
458			`end`
459			`//`
460			`// get data iff the fetch buffers are empty`
461			`//`
462			if (fetchbufA_v == `INV && fetchbufB_v == `INV) begin
463			`FetchA();`
464			`fetchbuf <= 1'b0;`
465			`end`
466			`// // Steer fetchbuf to the valid buffer.`
467			// else if (fetchbufB_v == `INV)
468			`// fetchbuf <= 1'b0;`
469			// else if (fetchbufA_v == `INV)
470			`// fetchbuf <= 1'b1;`
471			// else if (fetchbufA_v == `INV) begin
472			`// FetchA();`
473			`// end`
474			// else if (fetchbufB_v == `INV) begin
475			`// FetchB();`
476			`// end`
477			`end`
478
479			`// The fetchbuffer is invalidated at the end of a vector instruction`
480			`// queue.`
481			if (nop_fetchbuf[0]) fetchbufA_v <= `INV;
482			if (nop_fetchbuf[1]) fetchbufB_v <= `INV;
483			`end`
484
485			`assign fetchbuf0_instr = (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufB_instr;`
486			`assign fetchbuf0_insln = (fetchbuf == 1'b0) ? fetchbufA_inslen: fetchbufB_inslen;`
487			`assign fetchbuf0_v = (fetchbuf == 1'b0) ? fetchbufA_v : fetchbufB_v ;`
488			`assign fetchbuf0_pc = (fetchbuf == 1'b0) ? fetchbufA_pc : fetchbufB_pc ;`
489			`assign fetchbuf0_thrd = 1'b0;`
490			`assign fetchbuf0_pbyte = (fetchbuf == 1'b0) ? fetchbufA_pbyte : fetchbufB_pbyte;`
491
492			`reg [2:0] insln0;`
493			`always @*`
494			`begin`
495			`ifdef SUPPORT_DCI
496			if (insn0[5:0]==`CMPRSSD)
497			`insln0 <= 3'd2 \| pred_on;`
498			`else`
499			`endif
500	61	robfinch	`if (IsExec(insn0))`

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