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[/] [thor/] [trunk/] [bench/] [rtfSerialTxSim.v] - Blame information for rev 21

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1 21 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2015  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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// This core simulates a serial transmitter by outputing a text stream.
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// ============================================================================
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//
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module rtfSerialTxSim(rst,baud16,txd);
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input rst;
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input baud16;
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output txd;
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reg [9:0] buff;
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reg [9:0] buf2;
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reg [5:0] cnt;
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reg [3:0]  bitcnt;
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reg [7:0] msg [0:7];
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reg [7:0] msgndx;
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assign txd = buff[9];
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always @(posedge baud16)
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if (rst) begin
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    cnt <= 6'd0;
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    buff <= 10'h3FF;
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    buf2 <= 10'h3ff;
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    msg[0] = "H";
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    msg[1] = "i";
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    msg[2] = "T";
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    msg[3] = "h";
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    msg[4] = "e";
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    msg[5] = "r";
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    msg[6] = "e";
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    msg[7] = " ";
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    msgndx <= 4'd0;
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end
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else begin
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    cnt <= cnt + 6'd1;
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    if (cnt==6'd15) begin
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        cnt <= 6'd0;
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        bitcnt <= bitcnt + 4'd1;
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        if (bitcnt==4'd9) begin
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            bitcnt <= 4'd0;
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            buff <= buf2;
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            msgndx <= msgndx + 8'd1;
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            buf2 <= {1'b0,msg[msgndx],^msg[msgndx]};
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        end
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        else
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            buff <= {buff[8:0],1'b1};
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    end
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end
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endmodule

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