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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_shifter.v] - Blame information for rev 3

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1 3 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2013  Robert Finch, Stratford
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//
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//
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// Thor SuperScalar
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// Shift logic
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//
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// ============================================================================
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//
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`include "Thor_defines.v"
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module Thor_shifter(func, a, b, o);
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parameter DBW=64;
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input [5:0] func;
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input [DBW-1:0] a;
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input [DBW-1:0] b;
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output reg [DBW-1:0] o;
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wire [DBW*2-1:0] shlo = {{DBW{1'd0}},a} << b[5:0];
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wire [DBW*2-1:0] shruo = {a,{DBW{1'b0}}} >> b[5:0];
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wire signed [DBW-1:0] as = a;
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wire signed [DBW-1:0] shro = as >> b[5:0];
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always @(func or shlo or shro or shruo)
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case(func)
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`SHL,`SHLU,`SHLI,`SHLUI:
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        o <= shlo[DBW-1:0];
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`SHR,`SHRI:
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        o <= shro;
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`SHRU,`SHRUI:
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        o <= shruo[DBW*2-1:DBW];
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`ROL,`ROLI:
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        o <= shlo[DBW*2-1:DBW]|shlo[DBW-1:0];
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`ROR,`RORI:
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        o <= shruo[DBW*2-1:DBW]|shruo[DBW-1:0];
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default:        o <= 64'hDEADDEADDEADDEAD;
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endcase
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endmodule

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