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entactogen |
-- Copyright (c) 2011 Antonio de la Piedra
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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entity key_schedule is
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port(clk : in std_logic;
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rst : in std_logic;
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load : in std_logic;
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start : in std_logic;
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key_in : in std_logic_vector(127 downto 0);
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key_ready : out std_logic;
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key_out : out std_logic_vector(127 downto 0));
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end key_schedule;
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architecture Behavioral of key_schedule is
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signal w_3_i_s : std_logic_vector(31 downto 0);
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signal g_sub_0_s : std_logic_vector(7 downto 0);
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signal g_sub_1_s : std_logic_vector(7 downto 0);
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signal g_sub_2_s : std_logic_vector(7 downto 0);
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signal g_sub_3_s : std_logic_vector(7 downto 0);
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signal count_5 : natural range 0 to 5;
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signal count_10 : natural range 0 to 10;
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type type_RCON is array (0 to 9) of std_logic_vector(7 downto 0);
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constant rcon : type_RCON := (x"01", x"02", x"04", x"08", x"10", x"20", x"40", x"80", x"1B", x"36");
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begin
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mod_5_cnt : process(clk, rst, start)
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begin
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if rising_edge(clk) then
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if (rst = '1') then
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count_5 <= 0;
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elsif(start = '1') then
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if (count_5 = 4) then
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count_5 <= 0;
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else
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count_5 <= count_5 + 1;
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end if;
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end if;
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end if;
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end process mod_5_cnt;
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mod_10_cnt : process(clk, rst, start, count_5)
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begin
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if rising_edge(clk) then
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if (rst = '1') then
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count_10 <= 0;
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elsif(start = '1' and count_5 = 4) then
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if (count_10 = 9) then
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count_10 <= 0;
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else
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count_10 <= count_10 + 1;
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end if;
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end if;
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end if;
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end process mod_10_cnt;
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gen_sub_keys : process(clk, rst, start, count_5, count_10, load)
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variable w_0_i_tmp_old : std_logic_vector(31 downto 0) := (others => '0');
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variable w_1_i_tmp_old : std_logic_vector(31 downto 0) := (others => '0');
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variable w_2_i_tmp_old : std_logic_vector(31 downto 0) := (others => '0');
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variable w_3_i_tmp_old : std_logic_vector(31 downto 0) := (others => '0');
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variable tmp_0 : std_logic_vector(31 downto 0) := (others => '0');
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variable tmp_1 : std_logic_vector(31 downto 0) := (others => '0');
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variable tmp_2 : std_logic_vector(31 downto 0) := (others => '0');
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variable tmp_3 : std_logic_vector(31 downto 0) := (others => '0');
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begin
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if rising_edge(clk) then
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if (rst = '1') then
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w_0_i_tmp_old := (others => '0');
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w_1_i_tmp_old := (others => '0');
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w_2_i_tmp_old := (others => '0');
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w_3_i_tmp_old := (others => '0');
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elsif (load = '1') then
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w_0_i_tmp_old := key_in(31 downto 0);
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w_1_i_tmp_old := key_in(63 downto 32);
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w_2_i_tmp_old := key_in(95 downto 64);
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w_3_i_tmp_old := key_in(127 downto 96);
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elsif (start = '1') then
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if (count_5 = 1) then
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tmp_0 := w_0_i_tmp_old xor (g_sub_3_s & g_sub_2_s & g_sub_1_s & (g_sub_0_s xor rcon(count_10)));
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w_0_i_tmp_old := tmp_0;
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elsif (count_5 = 2) then
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tmp_1 := w_1_i_tmp_old xor w_0_i_tmp_old;
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w_1_i_tmp_old := tmp_1;
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elsif (count_5 = 3) then
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tmp_2 := w_2_i_tmp_old xor w_1_i_tmp_old;
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w_2_i_tmp_old := tmp_2;
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elsif (count_5 = 4) then
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tmp_3 := w_3_i_tmp_old xor w_2_i_tmp_old;
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w_3_i_tmp_old := tmp_3;
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end if;
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end if;
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end if;
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w_3_i_s <= w_3_i_tmp_old;
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key_out <= tmp_3 & tmp_2 & tmp_1 & tmp_0;
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end process;
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key_ready <= '1' when (count_5 = 1 and start = '1') else '0';
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S_BOX_DUAL_1: entity work.dual_mem(rtl) port map (clk, '0', w_3_i_s(7 downto 0), w_3_i_s(15 downto 8), (others=>'0'), g_sub_3_s, g_sub_0_s);
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S_BOX_DUAL_2: entity work.dual_mem(rtl) port map (clk, '0', w_3_i_s(23 downto 16), w_3_i_s(31 downto 24), (others=>'0'), g_sub_1_s, g_sub_2_s);
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end Behavioral;
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