Subversion Repositories timerocd

--------------------------------------------------------------------------------

--      File name : TimerOCD.vhd

--------------------------------------------------------------------------------

--      Copyright (C) 2015 Donna Whisnant/Dewtronics.

--      Contact: http://www.dewtronics.com/

--

--      This file may be used under the terms of the GNU Lesser General Public License

--      version 3.0 as published by the Free Software Foundation and appearing

--      in the files lgpl-3.0.txt/gpl-3.0.txt included in the packaging of this file.

--      Please review the following information to ensure the GNU Lesser General

--      Public License version 3.0 requirements will be met:

--      https://www.gnu.org/licenses/lgpl-3.0.html

--      Attribution requested, but not required.

--

--      Target Device: Xilinx Spartan-6 XC6SLX9-2-TQG144

--              Using Numato Mimas Spartan 6 FPGA Development Board

--              http://numato.com/mimas-spartan-6-fpga-development-board.html

--

--

--      Timer Output Compare Driver

--

--      This FPGA/CPLD code serves as a SPI Device and functions as a multichannel

--      Timer Output Compare driver for use in the DRSSTC (Dual Resonance Solid-State

--      Tesla Coil) MIDI Interrupter.

--

--      My original DRSSTC MIDI Interrupter used a series of Arduino ProMini boards,

--      each with a built-in limit of six timer output compare channels, to drive

--      the many note signal timing generation.  But instead of cascading six to

--      eight of those processors per interrupter output, this is an attempt to do

--      it all in a single chip.

--

--      The SPI Interface functions as a slave device with the following stream:

--              Master must send MSbit First:

--

--              Input (9 bytes per data message transfer or 1 byte per command message transfer):

--                      * 8-bit Command/Address Byte:

--                              C7..C0 :

--

--                              C7..C0 : Timer Address for Read and Write operations

--                                      C7 C6 C5 C4 C3 C2 C1 C0

--                                      -- -- -- -- -- -- -- --

--                                      |  |  |  |  |  |  |  |

--                                      |  |  +--+--+--+--+--+----- Timer Address 0-63 0x00-0x3F (000000-111111) (For Data Mode)

--                                      |  |                                            Commands (for Command Mode):

--                                      |  |                                                    000000 = Reset (performs power-on reset equivalent) on Write (Read has no effect)

--                                      |  |                                                    000001 = RESERVED

--                                      |  |                                                    000010 = Switch to Note/Power/PitchBend Run mode (initial default) on Write (Read has no effect)

--                                      |  |                                                    000011 = Switch to Timer On/Off Compare Value Run mode on Write (Read has no effect)

--                                      |  |                                                    000100 = Bank Select 0 (Notes 0-63) for future transfers on Write (Read has no effect)

--                                      |  |                                                    000101 = Bank Select 1 (Notes 64-127) for future transfers on Write (Read has no effect)

--                                      |  |                                                    000110 = Bank Select 2 (Notes 128-191) for future transfers on Write (Read has no effect)

--                                      |  |                                                    000111 = Bank Select 3 (Notes 192-255) for future transfers on Write (Read has no effect)

--                                      |  |                                                    001xxx = TBD/RESERVED

--                                      |  |                              Note: on 00xxxx Commands (above) and with Timer Address in the Data Mode the Concurrent

--                                      |  |                                     Read Nybble with the command send will be as follows:

--                                      |  |                                  0 m b b

--                                      |  |                                  - - - -

--                                      |  |                                  | | | |

--                                      |  |                                  | | +-+-- Currently Selected Bank

--                                      |  |                                  | |           00 = Bank 0

--                                      |  |                                  | |           01 = Bank 1

--                                      |  |                                  | |           10 = Bank 2

--                                      |  |                                  | |           11 = Bank 3

--                                      |  |                                  | |

--                                      |  |                                  | +------ RunMode : 0 = Note/Power/PitchBend, 1 = Timer On/Off Compare Values

--                                      |  |                                  |

--                                      |  |                                  +-------- Reserved for 001xxx command, TBD, will be sent as 0

--                                      |  |

--                                      |  |                                                    01xxxx = Read Push Button Switch 0-3 Status (Read Nybble is concurrent with sending command byte, Write has no effect)

--                                      |  |                                                    10xxxx = Read/Set LEDs 0-3 (Read Nybble is concurrent with sending command byte)

--                                      |  |                                                    11xxxx = Read/Set LEDs 4-7 (Read Nybble is concurrent with sending command byte)

--                                      |  |

--                                      |  +----------------------- Command/Data Select (0=Data, 1=Command)

--                                      |

--                                      +-------------------------- R/W Mode Select

--                                                                                                      0 = Write new value to TimerOCD and concurrently Read present value from TimerOCD

--                                                                                                      1 = Read present value from TimerOCD (Data received during read operation is ignored)

--

--              Note/Power/PitchBend Run Mode

--              -----------------------------

--                      * 16-Bit : 7-Bit Note/Key and 7-Bit Power/Velocity for Left Channel:  (Data Mode Only)

--                              0,N6..N0,0,P6..P0 :

--

--                                      0  N6 N5 N4 N3 N2 N1 N0

--                                      -- -- -- -- -- -- -- --

--                                      |  |  |  |  |  |  |  |

--                                      |  +--+--+--+--+--+--+-- Note/Key 0-127 0x00-0x7F (0000000-1111111) - Left Channel

--                                      |

--                                      +----------------------- Unused

--

--                                      0  P6 P5 P4 P3 P2 P1 P0

--                                      -- -- -- -- -- -- -- --

--                                      |  |  |  |  |  |  |  |

--                                      |  +--+--+--+--+--+--+-- Power/Velocity 0-127 0x00-0x7F (0000000-1111111) - Left Channel

--                                      |

--                                      +----------------------- Unused

--

--                      * 16-Bit : 14-Bit Pitch Bend for Left Channel:  (Data Mode Only)

--                              0,0,B13..B0 :

--

--                                      0  0  B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

--                                      -- -- --- --- --- --- -- -- -- -- -- -- -- -- -- --

--                                      |  |  |   |   |   |   |  |  |  |  |  |  |  |  |  |

--                                      |  |  +---+---+---+---+--+--+--+--+--+--+--+--+--+-- Pitch Bend 0000/2000(NoBend)/3FFF - Left Channel

--                                      |  |

--                                      +--+------------------------------------------------ Unused

--

--

--                      * 16-Bit : 7-Bit Note/Key and 7-Bit Power/Velocity for Right Channel:  (Data Mode Only)

--                              0,N6..N0,0,P6..P0 :

--

--                                      0  N6 N5 N4 N3 N2 N1 N0

--                                      -- -- -- -- -- -- -- --

--                                      |  |  |  |  |  |  |  |

--                                      |  +--+--+--+--+--+--+-- Note/Key 0-127 0x00-0x7F (0000000-1111111) - Right Channel

--                                      |

--                                      +----------------------- Unused

--

--                                      0  P6 P5 P4 P3 P2 P1 P0

--                                      -- -- -- -- -- -- -- --

--                                      |  |  |  |  |  |  |  |

--                                      |  +--+--+--+--+--+--+-- Power/Velocity 0-127 0x00-0x7F (0000000-1111111) - Right Channel

--                                      |

--                                      +----------------------- Unused

--

--                      * 16-Bit : 14-Bit Pitch Bend for Right Channel:  (Data Mode Only)

--                              0,0,B13..B0 :

--

--                                      0  0  B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

--                                      -- -- --- --- --- --- -- -- -- -- -- -- -- -- -- --

--                                      |  |  |   |   |   |   |  |  |  |  |  |  |  |  |  |

--                                      |  |  +---+---+---+---+--+--+--+--+--+--+--+--+--+-- Pitch Bend 0000/2000(NoBend)/3FFF - Right Channel

--                                      |  |

--                                      +--+------------------------------------------------ Unused

--

--

--                      >> A Note Value of 0 or Power Level of 0 is considered "OFF" and will disable the timer compare channel

--

--

--              Timer On/Off Value Run Mode

--              ---------------------------

--                      * 16-Bit : Timer ON Value for Left Channel:             (Data Mode Only)

--                              T15..T0 :

--

--                                      T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

--                                      --- --- --- --- --- --- -- -- -- -- -- -- -- -- -- --

--                                      |   |   |   |   |   |   |  |  |  |  |  |  |  |  |  |

--                                      +---+---+---+---+---+---+--+--+--+--+--+--+--+--+--+--  Timer ON Value 0x0000 - 0xFFFF - Left Channel

--

--

--                      * 16-Bit : Timer OFF Value for Left Channel:    (Data Mode Only)

--                              T15..T0 :

--

--                                      T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

--                                      --- --- --- --- --- --- -- -- -- -- -- -- -- -- -- --

--                                      |   |   |   |   |   |   |  |  |  |  |  |  |  |  |  |

--                                      +---+---+---+---+---+---+--+--+--+--+--+--+--+--+--+--  Timer OFF Value 0x0000 - 0xFFFF - Left Channel

--

--

--                      * 16-Bit : Timer ON Value for Right Channel:    (Data Mode Only)

--                              T15..T0 :

--

--                                      T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

--                                      --- --- --- --- --- --- -- -- -- -- -- -- -- -- -- --

--                                      |   |   |   |   |   |   |  |  |  |  |  |  |  |  |  |

--                                      +---+---+---+---+---+---+--+--+--+--+--+--+--+--+--+--  Timer ON Value 0x0000 - 0xFFFF - Right Channel

--

--

--                      * 16-Bit : Timer OFF Value for Right Channel:   (Data Mode Only)

--                              T15..T0 :

--

--                                      T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0

--                                      --- --- --- --- --- --- -- -- -- -- -- -- -- -- -- --

--                                      |   |   |   |   |   |   |  |  |  |  |  |  |  |  |  |

--                                      +---+---+---+---+---+---+--+--+--+--+--+--+--+--+--+--  Timer OFF Value 0x0000 - 0xFFFF - Right Channel

--

--                      >> Writing either Timer On or Timer Off to 0 is considered "OFF" and will disable the timer compare channel

--

--

--------------------------------------------------------------------------------

--

--      tmrMemBlkLeftXX/tmrMemBlkRightXX Memory Mapping:

--

--              Each Configured as 256 x 16-bit True Dual-Port RAM Memory

--                      Port A = All Read/Write processing (xferdataproc only)

--                      Port B = All Read-Only processing (tmrupdproc only)

--              (Address is 8-bits)

--

--              A7 A6 A5 A4 A3 A2 A1 A0

--              -- -- -- -- -- -- -- --

--              |  |  |  |  |  |  |  |

--              |  |  +--+--+--+--+--+------------      Subtimer Index (0-63) 0x00-0x3F

--              |  |

--              +--+--+---------------------------      Entry Selection:

--                                                                                              00 = Note and Power Data (as sent/received to/from SPI) (Read/Written on SPI side) (Note in MSB, Power in LSB)

--                                                                                              01 = Pitch Bend Value (as sent/received to/from SPI) (Read/Written on SPI side) (right-justified)

--                                                                                              10 = Timer ON Compare Value (Calculated during SPI receive and written then, Read on signal generation timer processing)

--                                                                                              11 = Timer OFF Compare Value (Calculated during SPI receive and written then, Read on signal generation timer processing)

--

--              Block Mapping:

--              --------------

--                      tmrMemBlkLeft00/tmrMemBlkRight00 - Holds notes 0-63

--                      tmrMemBlkLeft01/tmrMemBlkRight01 - Holds notes 64-127

--                      tmrMemBlkLeft02/tmrMemBlkRight02 - Holds notes 128-191

--                      tmrMemBlkLeft03/tmrMemBlkRight03 - Holds notes 192-255

--

--

--      tmrCTMemBlkLeftXX/tmrCTMemBlkRightXX Memory Mapping:

--

--              Each Configured as 64 x 16-bit Simple Dual-Port RAM Memory

--                      Port A = All Read/Write processing (used exclusively by tmrupdproc)

--              (Address is 6-bits)

--

--              A5 A4 A3 A2 A1 A0

--              -- -- -- -- -- --

--              |  |  |  |  |  |

--              +--+--+--+--+--+------- Subtimer Index (0-63) 0x00-0x3F

--

--

--                      tmrCTMemBlkLeft00/tmrCTMemBlkRight00 - Holds notes 0-63

--                      tmrCTMemBlkLeft01/tmrCTMemBlkRight01 - Holds notes 64-127

--                      tmrCTMemBlkLeft02/tmrCTMemBlkRight02 - Holds notes 128-191

--                      tmrCTMemBlkLeft03/tmrCTMemBlkRight03 - Holds notes 192-255

--

--------------------------------------------------------------------------------

--

--      cmpFreqMemBlk Memory Mapping:

--

--              Timer Output Compare FREQ Values

--                      (OFF Values) = (FREQ Value) - (ON Value)

--

--              Configured as 128 x 16-bit Dual Port ROM Memory

--              (Address is 7-bits)

--

--              A6 A5 A4 A3 A2 A1 A0

--              -- -- -- -- -- -- --

--              |  |  |  |  |  |  |

--              +--+--+--+--+--+--+------       Note Value 0-127 (0 is reserved for output disabled compare value of 0)

--

--

--------------------------------------------------------------------------------

--

--      cmpOnMemBlk Memory Mapping:

--

--              Timer Output Compare ON Values

--

--              Configured as 16384 x 16-bit Dual Port ROM Memory

--              (Address is 14-bits)

--

--              A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

--              --- --- --- --- -- -- -- -- -- -- -- -- -- --

--              |   |   |   |   |  |  |  |  |  |  |  |  |  |

--              |   |   |   |   |  |  |  +--+--+--+--+--+--+------      Note Value 0-127 (0 is reserved for output disabled compare value of 0)

--              |   |   |   |   |  |  |

--              +---+---+---+---+--+--+---------------------------      Power Value 0-127 (0 is reserved for output disabled compare value of 0)

--

--------------------------------------------------------------------------------

--

-- For PitchBend calculations, the top-two bits (bit B13 and B12) of the PitchBend determine which note

--              compare stores are used in the PitchBend calculation as follows:

--

--                      B13 B12

--                      --- ---

--                      0   0           -- Use Note-2 and Note-1

--                      0   1           -- Use Note-1 and Note

--                      1   0           -- Use Note and Note+1

--                      1   1           -- Use Note+1 and Note+2

--

--              Notes in the extremes of the Note values (i.e. outside of the meaningful

--                      88 note piano range where our compares wrap anyway) are excluded from

--                      the pitch bend calculations

--

--

--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

library UNISIM;

use UNISIM.VCOMPONENTS.all;

--------------------------------------------------------------------------------

-- ENTITY DECLARATION

--------------------------------------------------------------------------------

entity TimerOCD is

        port (

                reset_n: in STD_LOGIC;                                  -- Master reset (Active Low)

                SPI_SS_n_in: in STD_LOGIC;                              -- SPI Slave Select In (Active Low)

                SPI_CLK_in: in STD_LOGIC;                               -- SPI Clock In

                SPI_MOSI_in: in STD_LOGIC;                              -- SPI Master Out, Slave In

                SPI_MISO: out STD_LOGIC := 'Z';                 -- SPI Master In, Slave Out

                FiberOut: out STD_LOGIC_VECTOR(1 downto 0) := (OTHERS => '0');            -- Fiber Optic Output Drive Left/Right Channels

                ---

                ---                                                                             Numato Mimas Spartan6 Module I/O Mapping:

                GCLK_in: in STD_LOGIC;                                  -- Master System Clock (GCLK)

                SW0: in STD_LOGIC;                                              -- Push-Button Switch 0

                SW1: in STD_LOGIC;                                              -- Push-Button Switch 1

                SW2: in STD_LOGIC;                                              -- Push-Button Switch 2

                SW3: in STD_LOGIC;                                              -- Push-Button Switch 3

                LED: out STD_LOGIC_VECTOR(7 downto 0)    -- LEDs 0 - 7

        );

end TimerOCD;

--------------------------------------------------------------------------------

-- ARCHITECTURE DECLARATION

--------------------------------------------------------------------------------

architecture TimerOCD_arch of TimerOCD is

        constant tmrclkPrescaler : INTEGER := 64;       -- Output Timer Clock Prescaler (Based on incoming GCLK frequency) tmrclk = 1.5625MHz

        constant LEDpostPrescaler : INTEGER := 6250000;         -- 1/8th of a second pulse per LED with 100MHz GCLK

        constant numTimers : INTEGER := 256;            -- Number of Timers Supported

        constant numTimerBits : INTEGER := 8;           -- Number of Timer Address Bits

        constant numSubTimers : INTEGER := 64;          -- Number of Timers per Block

        constant numSubTimerBits : INTEGER := 6;        -- Number of SubTimer Address Bits

        constant numTimerBlocks : INTEGER := 4;         -- Number of Timer Blocks

        constant numTimerBlockBits : INTEGER := 2;      -- Number of Timer Block Address Bits

        constant numCommandXferBits : INTEGER := 6;     -- Number of Bit of Address Xfer is Command Bits

        constant numXferBits : INTEGER := 64;           -- Number of bits transmitted/received during SPI data exchange

        constant numOutputs : INTEGER := 2;                     -- Number of Outputs Supported

        constant LEFT_OUT_NDX : INTEGER := 0;            -- Left Output Index for array processing

        constant RIGHT_OUT_NDX : INTEGER := 1;          -- Right Output Index for array processing

        constant EVEN_NDX : STD_LOGIC := '0';            -- tmrupdproc Even-Half Index for array processing

        constant ODD_NDX : STD_LOGIC := '1';            -- tmrupdproc Odd-Half Index for array processing

        constant adrNotePower : STD_LOGIC_VECTOR := "00";       -- Note/Power address slots

        constant adrPitchBend : STD_LOGIC_VECTOR := "01";       -- PitchBend address slots

        constant adrTimeON : STD_LOGIC_VECTOR := "10";          -- Timer ON Compare address slots

        constant adrTimeOFF : STD_LOGIC_VECTOR := "11";         -- Timer OFF Compare address slots

        constant LOWERNOTE_INDEX : INTEGER := 21;       -- First "Piano" note index (i.e. lowest one considered in pitchbend)

        constant UPPERNOTE_INDEX : INTEGER := 108;      -- Last "Piano" note index (i.e. highest one considered in pitchbend)

        -- Conversion Functions:

        function TmrBlock(constant nAddrBlock : STD_LOGIC_VECTOR(numTimerBlockBits-1 downto 0)) return INTEGER is

        begin

                return CONV_INTEGER(nAddrBlock);

        end function TmrBlock;

        function Tmr(constant nSubTimer : STD_LOGIC_VECTOR(numSubTimerBits-1 downto 0)) return INTEGER is

        begin

                return CONV_INTEGER(nSubTimer);

        end function Tmr;

        function Tmr(constant nOddEven : STD_LOGIC; constant nSubTimerUpd : STD_LOGIC_VECTOR(numSubTimerBits-2 downto 0)) return INTEGER is

        begin

                return CONV_INTEGER(nOddEven & nSubTimerUpd);

        end function Tmr;

        component BUFG is

                port (

                        I : in STD_ULOGIC;

                        O : out STD_ULOGIC

                );

        end component;

        component timer_memblk

                port (

                        clka : in STD_LOGIC;

                        ena : in STD_LOGIC;

                        wea : in STD_LOGIC_VECTOR(0 downto 0);

                        addra : in STD_LOGIC_VECTOR(7 downto 0);

                        dina : in STD_LOGIC_VECTOR(15 downto 0);

                        douta : out STD_LOGIC_VECTOR(15 downto 0);

                        ----

                        clkb : in STD_LOGIC;

                        enb : in STD_LOGIC;

                        web : in STD_LOGIC_VECTOR(0 downto 0);

                        addrb : in STD_LOGIC_VECTOR(7 downto 0);

                        dinb : in STD_LOGIC_VECTOR(15 downto 0);

                        doutb : out STD_LOGIC_VECTOR(15 downto 0)

                );

        end component;

        component timerCT_memblk

                port (

                        clka : in STD_LOGIC;

                        ena : in STD_LOGIC;

                        wea : in STD_LOGIC_VECTOR(0 downto 0);

                        addra : in STD_LOGIC_VECTOR(5 downto 0);

                        dina : in STD_LOGIC_VECTOR(15 downto 0);

                        clkb : in STD_LOGIC;

                        enb : in STD_LOGIC;

                        addrb : in STD_LOGIC_VECTOR(5 downto 0);

                        doutb : out STD_LOGIC_VECTOR(15 downto 0)

                );

        end component;

        component cmpFreqData_memblk

                port (

                        clka : in STD_LOGIC;

                        addra : in STD_LOGIC_VECTOR(6 downto 0);

                        douta : out STD_LOGIC_VECTOR(15 downto 0);

                        clkb : IN STD_LOGIC;

                        addrb : IN STD_LOGIC_VECTOR(6 downto 0);

                        doutb : OUT STD_LOGIC_VECTOR(15 downto 0)

                );

        end component;

        component cmpOnData_memblk

                port (

                        clka : in STD_LOGIC;

                        addra : in STD_LOGIC_VECTOR(13 downto 0);

                        douta : out STD_LOGIC_VECTOR(15 downto 0);

                        clkb : IN STD_LOGIC;

                        addrb : IN STD_LOGIC_VECTOR(13 downto 0);

                        doutb : OUT STD_LOGIC_VECTOR(15 downto 0)

                );

        end component;

        component InterpolateMultAdd

                port (

                        a : in STD_LOGIC_VECTOR(15 downto 0);

                        b : in STD_LOGIC_VECTOR(11 downto 0);

                        c : in STD_LOGIC_VECTOR(27 downto 0);

                        subtract : in STD_LOGIC;

                        p : out STD_LOGIC_VECTOR(27 downto 12);

                        pcout : out STD_LOGIC_VECTOR(47 downto 0)

                );

        end component;

        -- Master Timer:

        signal theTimer : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');

        -- The Outputs:

        --              This is the value of all output signals and their corresponding "pseudo" outputs forming the combined output.

        --              Each output will be generated by the 'OR' of all values for the numTimers associated with that output:

        type TOutputBlockArray is array (0 to numTimerBlocks-1) of STD_LOGIC_VECTOR(numSubTimers-1 downto 0);

        type TOutputArray is array (0 to numOutputs-1) of TOutputBlockArray;

        signal outputLevels : TOutputArray;                     -- Toggles during On/Off transitions

        signal outputEnables : TOutputArray;            -- Set to '1' when timer loaded with valid compares and is enabled

        signal outputEnablesNext : TOutputArray;        -- Next state for outputEnables, set in xferdataproc and transferred to outputEnables in tmrupdproc when a timer compare occurs

        signal outputForceLoad : TOutputArray;          -- Toggled in the xferdataproc when receiving a timer value causing the tmrupdproc to force-load that timer during the next timer processing cycle

        signal outputForceLoad_done : TOutputArray;     -- Toggled when the tmrupdproc processes an OutputForceLoad flag

        signal LEDenable : STD_LOGIC_VECTOR(7 downto 0);                 -- LED Outputs, set in RxData Processing

        signal LEDSet : STD_LOGIC;                                                                      -- Set to '1' whenever any LED value is written via SPI, used to switch from LEDpost to LEDenable mode

        signal LEDpost : STD_LOGIC_VECTOR(7 downto 0);                           -- LED POST drive

        signal LEDpostScalerCount : STD_LOGIC_VECTOR(31 downto 0);       -- POST timer clock/counter

        signal LEDpostPulse : STD_LOGIC;                                                        -- LED POST Pulse generated on scaler counter rollover, used to strobe LEDpost to the next state

        signal runMode : STD_LOGIC := '0';                       -- Run Mode : 0 = Note/Power/PitchBend,  1 = Timer On/Off (via SPI command)

        constant rmodeNote : STD_LOGIC := '0';

        constant rmodeTime : STD_LOGIC := '1';

        -- SPI Connection:

        signal SPI_SS_n : STD_LOGIC;                                                                                            -- Preprocessed SPI_SS

        signal SPI_CLK : STD_LOGIC;                                                                                                     -- Preprocessed SPI_CLK

        signal SPI_MOSI : STD_LOGIC;                                                                                            -- Preprocessed SPI_MOSI

        signal SPI_addr : STD_LOGIC_VECTOR(7 downto 0) := (OTHERS => '0');                        -- Current Address for SPI Read/Write

        signal SPI_addr_latch : STD_LOGIC := '0';                                                                        -- Address Latch enable from SPI

        signal SPI_rx_data : STD_LOGIC_VECTOR(numXferBits-1 downto 0);                           -- Receive Data for On/Off Timer Values by Note/Velocity

        signal SPI_tx_data : STD_LOGIC_VECTOR(numXferBits-1 downto 0);                           -- Transmit Data for On/Off Timer Values by Note/Velocity

        signal SPI_rrdy : STD_LOGIC := '0';                                                                                      -- Receive Data Ready (when new command is available)

        signal SPI_cmd_addr : STD_LOGIC_VECTOR(2 downto 0) := (OTHERS => '0');            -- Command Address portion of Current Address for SPI Read/Write

        signal SPI_txcmd_data : STD_LOGIC_VECTOR(3 downto 0);                                            -- Transmit Command Data generated on SPI_cmd_data_latch synchronization logic in response to command byte

        signal SPI_busy : STD_LOGIC;                                                                                            -- Cooked and Buffered (i.e. clock synchronized) SPI busy

        -- Timer MemBlk Connections:

        type TTimerAddrBus is array (0 to numTimerBlocks-1) of STD_LOGIC_VECTOR(7 downto 0);

        type TTimerDataBus is array (0 to numTimerBlocks-1) of STD_LOGIC_VECTOR(15 downto 0);

        -----------------------------------

        signal tmrMemBlkLeft_CLKXfer : STD_LOGIC;                                                                       -- PORT A : xferdataproc Processing (All Synchronous R/W)

        signal tmrMemBlkLeft_ENXfer : STD_LOGIC;

        signal tmrMemBlkLeft_WEXfer : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);

        signal tmrMemBlkLeft_ADDRXfer : STD_LOGIC_VECTOR(7 downto 0);

        signal tmrMemBlkLeft_DINXfer : TTimerDataBus;

        signal tmrMemBlkLeft_DOUTXfer : TTimerDataBus;

        signal tmrMemBlkLeft_CLKTmr : STD_LOGIC;                                                                        -- PORT B : tmrupdproc Processing (All Synchronous Read-Only)

        signal tmrMemBlkLeft_ENTmr : STD_LOGIC;

        signal tmrMemBlkLeft_ADDRTmr : TTimerAddrBus;

        signal tmrMemBlkLeft_DOUTTmr : TTimerDataBus;

        signal tmrMemBlkLeft_WE_GATE : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);              -- Port Write Enable Gate for xferdataproc processing

        -----------------------------------

        signal tmrMemBlkRight_CLKXfer : STD_LOGIC;                                                                      -- PORT A : xferdataproc Processing (All Synchronous R/W)

        signal tmrMemBlkRight_ENXfer : STD_LOGIC;

        signal tmrMemBlkRight_WEXfer : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);

        signal tmrMemBlkRight_ADDRXfer : STD_LOGIC_VECTOR(7 downto 0);

        signal tmrMemBlkRight_DINXfer : TTimerDataBus;

        signal tmrMemBlkRight_DOUTXfer : TTimerDataBus;

        signal tmrMemBlkRight_CLKTmr : STD_LOGIC;                                                                       -- PORT B : tmrupdproc Processing (All Synchronous Read-Only)

        signal tmrMemBlkRight_ENTmr : STD_LOGIC;

        signal tmrMemBlkRight_ADDRTmr : TTimerAddrBus;

        signal tmrMemBlkRight_DOUTTmr : TTimerDataBus;

        signal tmrMemBlkRight_WE_GATE : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);     -- Port Write Enable Gate for xferdataproc processing

        -- TimerCT MemBlk Connections:

        signal tmrCTMemBlkLeft_CLKA : STD_LOGIC;

        signal tmrCTMemBlkLeft_ENA : STD_LOGIC;

        signal tmrCTMemBlkLeft_WEA : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);

        signal tmrCTMemBlkLeft_ADDRA : STD_LOGIC_VECTOR(5 downto 0);

        signal tmrCTMemBlkLeft_DINA : TTimerDataBus;

        signal tmrCTMemBlkLeft_CLKB : STD_LOGIC;

        signal tmrCTMemBlkLeft_ENB : STD_LOGIC;

        signal tmrCTMemBlkLeft_ADDRB : STD_LOGIC_VECTOR(5 downto 0);

        signal tmrCTMemBlkLeft_DOUTB : TTimerDataBus;

        signal tmrMemBlkLeft_DOUTBpTimer : TTimerDataBus;                                                               -- tmrMemBlkLeft_DOUTTmr Data plus timer from concurrent logic to load into tmrCTMemBlkLeft to reduce memory setup time in tmrupdproc

        signal tmrMemBlkLeft_DINAmuxODD : TTimerDataBus;                                                                -- Multiplexer for tmrMemBlk Left ODD Data In Port A

        signal tmrMemBlkLeft_DINAmuxEVEN : TTimerDataBus;                                                               -- Multiplexer for tmrMemBlk Left EVEN Data In Port A

        signal tmrCTMemBlkLeft_eqTimer : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);    -- Comparison result of tmrCTMemBlkLeft == theTimer, used to reduce memory setup time in tmrupdproc

        signal tmrCTMemBlkLeft_WE_GATE : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);    -- Port Write Enable Gate for tmrupdproc processing

        -----------------------------------

        signal tmrCTMemBlkRight_CLKA : STD_LOGIC;

        signal tmrCTMemBlkRight_ENA : STD_LOGIC;

        signal tmrCTMemBlkRight_WEA : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);

        signal tmrCTMemBlkRight_ADDRA : STD_LOGIC_VECTOR(5 downto 0);

        signal tmrCTMemBlkRight_DINA : TTimerDataBus;

        signal tmrCTMemBlkRight_CLKB : STD_LOGIC;

        signal tmrCTMemBlkRight_ENB : STD_LOGIC;

        signal tmrCTMemBlkRight_ADDRB : STD_LOGIC_VECTOR(5 downto 0);

        signal tmrCTMemBlkRight_DOUTB : TTimerDataBus;

        signal tmrMemBlkRight_DOUTBpTimer : TTimerDataBus;                                                              -- tmrMemBlkRight_DOUTTmr Data plus timer from concurrent logic to load into tmrCTMemBlkRight to reduce memory setup time in tmrupdproc

        signal tmrMemBlkRight_DINAmuxODD : TTimerDataBus;                                                               -- Multiplexer for tmrMemBlk Right ODD Data In Port A

        signal tmrMemBlkRight_DINAmuxEVEN : TTimerDataBus;                                                              -- Multiplexer for tmrMemBlk Right EVEN Data In Port A

        signal tmrCTMemBlkRight_eqTimer : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);   -- Comparison result of tmrCTMemBlkRight == theTimer, used to reduce memory setup time in tmrupdproc

        signal tmrCTMemBlkRight_WE_GATE : STD_LOGIC_VECTOR(numTimerBlocks-1 downto 0);   -- Port Write Enable Gate for tmrupdproc processing

        -- Compare Freq MemBlk Connection:

        signal cmpFreqLeftMemBlk_CLK : STD_LOGIC;                                                                       -- Port A used by Left Channel

        signal cmpFreqLeftMemBlk_ADDR : STD_LOGIC_VECTOR(6 downto 0);

        signal cmpFreqLeftMemBlk_DOUT : STD_LOGIC_VECTOR(15 downto 0);

        ----

        signal cmpFreqRightMemBlk_CLK : STD_LOGIC;                                                                      -- Port B used by Right Channel

        signal cmpFreqRightMemBlk_ADDR : STD_LOGIC_VECTOR(6 downto 0);

        signal cmpFreqRightMemBlk_DOUT : STD_LOGIC_VECTOR(15 downto 0);

        -- Compare On MemBlk Connection:

        signal cmpOnLeftMemBlk_CLK : STD_LOGIC;                                                                         -- Port A used by Left Channel

        signal cmpOnLeftMemBlk_ADDR : STD_LOGIC_VECTOR(13 downto 0);

        signal cmpOnLeftMemBlk_DOUT : STD_LOGIC_VECTOR(15 downto 0);

        -----

        signal cmpOnRightMemBlk_CLK : STD_LOGIC;                                                                        -- Port B used by Right Channel

        signal cmpOnRightMemBlk_ADDR : STD_LOGIC_VECTOR(13 downto 0);

        signal cmpOnRightMemBlk_DOUT : STD_LOGIC_VECTOR(15 downto 0);

        -- Calculations:

        signal pitchBendLeftNoteAIndex : STD_LOGIC_VECTOR(6 downto 0) := (OTHERS => '0');                 -- Lower note index for pitch bend (see comments at top)

        signal pitchBendLeftNoteBIndex : STD_LOGIC_VECTOR(6 downto 0) := (OTHERS => '0');                 -- Upper note index for pitch bend (see comments at top)

        signal pitchBendLeftMagnitude : STD_LOGIC_VECTOR(11 downto 0) := (OTHERS => '0');                 -- Absolute value of magnitude of pitch bend => DSP InterpolateMultAdd(B)

        signal pitchBendLeftCalcFREQAlpha : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');             -- NoteA Compare FREQ Value (lower) => DSP InterpolateMultAdd(C and delta)

        signal pitchBendLeftCalcFREQAlphaLeft : STD_LOGIC_VECTOR(27 downto 0) := (OTHERS => '0'); -- Left Justified NoteA Compare FREQ Value (lower) => DSP InterpolateMultAdd(C), Needed for addition to be "Multiplied" by 2^12

        signal pitchBendLeftCalcFreqBeta : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');              -- NoteB Compare FREQ Value (upper) => DSP InterpolateMultAdd(delta)

        signal pitchBendLeftCalcFREQDelta : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');             -- Compare FREQ (NoteB-NoteA) => DSP InterpolateMultAdd(A)

        signal pitchBendLeftCalcFREQResult : STD_LOGIC_VECTOR(15 downto 0);                                                      -- Compare FREQ Output from DSP InterpolateMultAdd

        signal pitchBendLeftCalcONAlpha : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');                       -- NoteA Compare ON Value (lower) => DSP InterpolateMultAdd(C and delta)

        signal pitchBendLeftCalcONAlphaLeft : STD_LOGIC_VECTOR(27 downto 0) := (OTHERS => '0');           -- Left Justified NoteA Compare ON Value (lower) => DSP InterpolateMultAdd(C), Needed for addition to be "Multiplied" by 2^12

        signal pitchBendLeftCalcONBeta : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');                        -- NoteB Compare ON Value (upper) => DSP InterpolateMultAdd(delta)

        signal pitchBendLeftCalcONDelta : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');                       -- Compare ON (NoteB-NoteA) => DSP InterpolateMultAdd(A)

        signal pitchBendLeftCalcONResult : STD_LOGIC_VECTOR(15 downto 0);                                                        -- Compare ON Output from DSP InterpolateMultAdd

        -----

        signal pitchBendRightNoteAIndex : STD_LOGIC_VECTOR(6 downto 0) := (OTHERS => '0');                        -- Lower note index for pitch bend (see comments at top)

        signal pitchBendRightNoteBIndex : STD_LOGIC_VECTOR(6 downto 0) := (OTHERS => '0');                        -- Upper note index for pitch bend (see comments at top)

        signal pitchBendRightMagnitude : STD_LOGIC_VECTOR(11 downto 0) := (OTHERS => '0');                        -- Absolute value of magnitude of pitch bend => DSP InterpolateMultAdd(B)

        signal pitchBendRightCalcFREQAlpha : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');            -- NoteA Compare FREQ Value (lower) => DSP InterpolateMultAdd(C and delta)

        signal pitchBendRightCalcFREQAlphaLeft : STD_LOGIC_VECTOR(27 downto 0) := (OTHERS => '0');        -- Left Justified NoteA Compare FREQ Value (lower) => DSP InterpolateMultAdd(C), Needed for addition to be "Multiplied" by 2^12

        signal pitchBendRightCalcFREQBeta : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');             -- NoteB Compare FREQ Value (upper) => DSP InterpolateMultAdd(delta)

        signal pitchBendRightCalcFREQDelta : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');            -- Compare FREQ (NoteB-NoteA) => DSP InterpolateMultAdd(A)

        signal pitchBendRightCalcFREQResult : STD_LOGIC_VECTOR(15 downto 0);                                             -- Compare FREQ Output from DSP InterpolateMultAdd

        signal pitchBendRightCalcONAlpha : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');              -- NoteA Compare ON Value (lower) => DSP InterpolateMultAdd(C and delta)

        signal pitchBendRightCalcONAlphaLeft : STD_LOGIC_VECTOR(27 downto 0) := (OTHERS => '0');  -- Left Justified NoteA Compare ON Value (lower) => DSP InterpolateMultAdd(C), Needed for addition to be "Multiplied" by 2^12

        signal pitchBendRightCalcONBeta : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');                       -- NoteB Compare ON Value (upper) => DSP InterpolateMultAdd(delta)

        signal pitchBendRightCalcONDelta : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');              -- Compare ON (NoteB-NoteA) => DSP InterpolateMultAdd(A)

        signal pitchBendRightCalcONResult : STD_LOGIC_VECTOR(15 downto 0);                                                       -- Compare ON Output from DSP InterpolateMultAdd

        -- Clocks

        signal GCLK : STD_LOGIC;                                -- Buffered GCLK input

        signal tmrclk : STD_LOGIC;                              -- Buffered Timer Clock (derived from GCLK based on timer prescaler)

        signal sysclk : STD_LOGIC;                              -- Buffered System processing clock (equivalent to GCLK with a separate name reserved for possible scaling)

        signal xferdataclk : STD_LOGIC;                 -- Buffered System Clock divided from sysclk for xferdataproc to slow it down enough to meet timing constraints for calculations

        signal tmrclk_in: STD_LOGIC;                    -- Timer Clock In (Derived from GCLK by dividing by prescaler)

        signal tmrclk_prescaler_count: STD_LOGIC_VECTOR(15 downto 0);            -- tmrclk generation prescaler counter

        signal xferdataclk_in: STD_LOGIC := '0'; -- XferData Clock in (Derived from GCLK/sysclk by dividing it to meet timing constraints, currently a divide by 2)

        -- Misc

        signal syn_rrdy : STD_LOGIC;                    -- Synchronous SPI_rrdy signal

        signal syn_rrdy_armed : STD_LOGIC;              -- Arming for Synchronous SPI_rrdy signal generation.  Used to extend the trigger period to at least one sysclk cycle

        signal syn_rrdy_clr_n : STD_LOGIC;              -- Synchronous rrdy clear signal (asserted when data has been read)

        signal syn_rxdata_trigger_n : STD_LOGIC := '1';         -- Synchronous rxdata processing trigger (asserted to start the rxdata receive process)

        signal syn_rxdata_processing_n : STD_LOGIC := '1';      -- Synchronous rxdata processing signal (asserted when we are processing incoming data)

        signal syn_cmd_processing_n : STD_LOGIC := '1';         -- Synchronous cmd processing signal (asserted hwen rxdataproc is processing the incoming SPI command)

        constant nRxSB : integer := 3;                                          -- Number of RxData State Bits (used for conversions)

        signal syn_rxdata_state : STD_LOGIC_VECTOR(nRxSB-1 downto 0) := (OTHERS => '0');  -- Synchronous rxdata processing state-machine state (See xferdataproc for details)

        signal syn_rxdata : STD_LOGIC_VECTOR(numXferBits-1 downto 0);            -- Synchronized received buffer to hold the SPI_rx_data before transferring to our internal logic

        signal txdata_trigger_n : STD_LOGIC := '1';                     -- txdata trigger, set upon the rising edge of SPI_addr_latch, meaning latch address is in progress, reset when txdata_processing_n becomes active or SPI_SS_n deasserts indicating xfer was aborted

        signal txdata_processing_n : STD_LOGIC := '1';          -- txdata processing, set when xferdataproc starts transmitting data (to the buffer) to be sent out over SPI

        constant nTxSB : integer := 2;                                          -- Number of TxData State Bits (used for conversions)

        signal txdata_state : STD_LOGIC_VECTOR(nTxSB-1 downto 0) := (OTHERS => '0');      -- Synchronous txdata processing state-machine state (See xferdataproc for details)

        signal local_rst_n : STD_LOGIC := '1';  -- Local reset to process the reset command from SPI

        signal reset_trigger_n : STD_LOGIC := '1';                      -- Reset trigger -- initiated by either reset_n or local_reset_n during sysclk processing of rxproc

        signal reset_in_progress_n : STD_LOGIC := '1';          -- Reset currently is progress -- initiated by reset_trigger_n, cleared when reset is complete

        signal tmrproc_trigger_n : STD_LOGIC := '1';            -- Timer Process Trigger - Set by tmrclk event in timerproc, acted on by tmrupdproc

        signal tmrproc_processing_n : STD_LOGIC := '1';         -- Timer Process Processing - Set in tmrupdproc in response to tmrclk to indicate tmrupdproc state-machine is running

        signal tmrproc_tmrndxEVEN : STD_LOGIC_VECTOR(numSubTimerBits-2 downto 0) := (OTHERS => '0');              -- Even Timer Index during the Timer Update Processing loop

        signal tmrproc_tmrndxODD : STD_LOGIC_VECTOR(numSubTimerBits-2 downto 0) := (OTHERS => '0');                       -- Odd Timer Index during the Timer Update Processing loop

        signal tmrproc_tmrndxEVENLock : STD_LOGIC_VECTOR(numSubTimerBits-2 downto 0) := (OTHERS => '0');  -- Even Timer Index Locked during the Timer Output Update Processing loop

        signal tmrproc_tmrndxODDLock : STD_LOGIC_VECTOR(numSubTimerBits-2 downto 0) := (OTHERS => '0');           -- Odd Timer Index Locked during the Timer Output Update Processing loop

        constant nTSB : integer := 1;                                           -- Number of Timer State Bits (used for conversions)

        signal tmrproc_state : STD_LOGIC_VECTOR(nTSB-1 downto 0) := (OTHERS => '0');                              -- Timer Update Processing state machine (See tmrupdproc for details)

        signal spi_xfer_mode : STD_LOGIC := '0';                 -- Command/Data mode from SPI address (0=Data, 1=Command)

        signal syn_xfer_mode : STD_LOGIC := '0';                 -- Latched version of spi_xfer_mode.  Latched at start of rxdata/xferdata proc in case new address starts transferring while we are still processing