URL https://opencores.org/ocsvn/timerocd/timerocd/trunk

Subversion Repositories timerocd

[/] [timerocd/] [trunk/] [xilinx/] [TimerOCD/] [ipcore_dir/] [coregen.cgc] - Blame information for rev 2

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   xilinx.com
   project
   coregen
   1.0
   
      
         InterpolateMultAdd
         
         
            InterpolateMultAdd
            0
            0
            1
            1
            false
            16
            12
            28
            27
            12
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx9
                  spartan6
                  tqg144
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
               
                  2013-07-22+10:41
               
            
         
      
      
         cmpFreqData_memblk
         
         
            cmpFreqData_memblk
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            Dual_Port_ROM
            false
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            false
            16
            128
            16
            WRITE_FIRST
            Always_Enabled
            16
            16
            WRITE_FIRST
            Always_Enabled
            false
            false
            false
            false
            false
            false
            false
            false
            0
            true
            ./cmpFreqData_memblk.coe
            true
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            0
            100
            0
            100
            100
            ALL
            false
            false
            Stand_Alone
            no_Mem_file_loaded
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx9
                  spartan6
                  tqg144
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
               
                  2012-11-19+16:22
               
            
         
      
      
         cmpOffData_memblk
         
         
            cmpOffData_memblk
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            Dual_Port_ROM
            false
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            false
            16
            16384
            16
            WRITE_FIRST
            Always_Enabled
            16
            16
            WRITE_FIRST
            Always_Enabled
            false
            false
            false
            false
            false
            false
            false
            false
            0
            true
            ./cmpOffData_memblk.coe
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            0
            100
            0
            100
            100
            ALL
            false
            false
            Stand_Alone
            no_Mem_file_loaded
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx9
                  spartan6
                  tqg144
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
               
                  2012-11-19+16:22
               
            
         
      
      
         cmpOnData_memblk
         
         
            cmpOnData_memblk
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            Dual_Port_ROM
            false
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            false
            16
            16384
            16
            WRITE_FIRST
            Always_Enabled
            16
            16
            WRITE_FIRST
            Always_Enabled
            false
            false
            false
            false
            false
            false
            false
            false
            0
            true
            ./cmpOnData_memblk.coe
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            0
            100
            0
            100
            100
            ALL
            false
            false
            Stand_Alone
            no_Mem_file_loaded
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx9
                  spartan6
                  tqg144
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
               
                  2012-11-19+16:22
               
            
         
      
      
         timerCT_memblk
         
         
            timerCT_memblk
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            Simple_Dual_Port_RAM
            false
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            true
            16
            64
            16
            READ_FIRST
            Use_ENA_Pin
            16
            16
            READ_FIRST
            Use_ENB_Pin
            false
            false
            false
            false
            false
            false
            false
            false
            0
            false
            no_coe_file_loaded
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            50
            100
            0
            100
            100
            ALL
            false
            false
            Stand_Alone
            no_Mem_file_loaded
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx9
                  spartan6
                  tqg144
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
               
                  2012-11-19+16:22
               
            
         
      
      
         timer_memblk
         
         
            timer_memblk
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            True_Dual_Port_RAM
            false
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            false
            9
            Minimum_Area
            8kx2
            true
            16
            256
            16
            WRITE_FIRST
            Use_ENA_Pin
            16
            16
            WRITE_FIRST
            Use_ENB_Pin
            false
            false
            false
            false
            false
            false
            false
            false
            0
            false
            no_coe_file_loaded
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            50
            100
            50
            100
            100
            ALL
            false
            false
            Stand_Alone
            no_Mem_file_loaded
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6slx9
                  spartan6
                  tqg144
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
               
                  2012-11-19+16:22
               
            
         
      
   
   
      
         
            coregen
            ./
            ./tmp/
            ./tmp/_cg/
         
         
            xc6slx9
            spartan6
            tqg144
            -2
         
         
            BusFormatAngleBracketNotRipped
            VHDL
            true
            Other
            false
            false
            false
            Ngc
            false
         
         
            Behavioral
            VHDL
            false
         
      
   

 

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Subversion Repositories timerocd

[/] [timerocd/] [trunk/] [xilinx/] [TimerOCD/] [ipcore_dir/] [coregen.cgc] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	dewhisna
2
3			`xilinx.com`
4			`project`
5			`coregen`
6			`1.0`
7
8
9			`InterpolateMultAdd`
10
11
12			`InterpolateMultAdd`
13			`0`
14			`0`
15			`1`
16			`1`
17			`false`
18			`16`
19			`12`
20			`28`
21			`27`
22			`12`
23			`0`
24			`0`
25			`0`
26
27
28
29
30			`coregen`
31			`./`
32			`./tmp/`
33			`./tmp/_cg/`
34
35
36			`xc6slx9`
37			`spartan6`
38			`tqg144`
39			`-2`
40
41
42			`BusFormatAngleBracketNotRipped`
43			`VHDL`
44			`true`
45			`Other`
46			`false`
47			`false`
48			`false`
49			`Ngc`
50			`false`
51
52
53			`Behavioral`
54			`VHDL`
55			`false`
56
57
58			`2013-07-22+10:41`
59
60
61
62
63
64			`cmpFreqData_memblk`
65
66
67			`cmpFreqData_memblk`
68			`Native`
69			`AXI4_Full`
70			`Memory_Slave`
71			`false`
72			`4`
73			`Dual_Port_ROM`
74			`false`
75			`No_ECC`
76			`false`
77			`false`
78			`false`
79			`Single_Bit_Error_Injection`
80			`false`
81			`9`
82			`Minimum_Area`
83			`8kx2`
84			`false`
85			`16`
86			`128`
87			`16`
88			`WRITE_FIRST`
89			`Always_Enabled`
90			`16`
91			`16`
92			`WRITE_FIRST`
93			`Always_Enabled`
94			`false`
95			`false`
96			`false`
97			`false`
98			`false`
99			`false`
100			`false`
101			`false`
102			`0`
103			`true`
104			`./cmpFreqData_memblk.coe`
105			`true`
106			`0`
107			`false`
108			`false`
109			`CE`
110			`0`
111			`false`
112			`false`
113			`CE`
114			`0`
115			`SYNC`
116			`false`
117			`100`
118			`0`
119			`100`
120			`0`
121			`100`
122			`100`
123			`ALL`
124			`false`
125			`false`
126			`Stand_Alone`
127			`no_Mem_file_loaded`
128
129
130
131
132			`coregen`
133			`./`
134			`./tmp/`
135			`./tmp/_cg/`
136
137
138			`xc6slx9`
139			`spartan6`
140			`tqg144`
141			`-2`
142
143
144			`BusFormatAngleBracketNotRipped`
145			`VHDL`
146			`true`
147			`Other`
148			`false`
149			`false`
150			`false`
151			`Ngc`
152			`false`
153
154
155			`Behavioral`
156			`VHDL`
157			`false`
158
159
160			`2012-11-19+16:22`
161
162
163
164
165
166			`cmpOffData_memblk`
167
168
169			`cmpOffData_memblk`
170			`Native`
171			`AXI4_Full`
172			`Memory_Slave`
173			`false`
174			`4`
175			`Dual_Port_ROM`
176			`false`
177			`No_ECC`
178			`false`
179			`false`
180			`false`
181			`Single_Bit_Error_Injection`
182			`false`
183			`9`
184			`Minimum_Area`
185			`8kx2`
186			`false`
187			`16`
188			`16384`
189			`16`
190			`WRITE_FIRST`
191			`Always_Enabled`
192			`16`
193			`16`
194			`WRITE_FIRST`
195			`Always_Enabled`
196			`false`
197			`false`
198			`false`
199			`false`
200			`false`
201			`false`
202			`false`
203			`false`
204			`0`
205			`true`
206			`./cmpOffData_memblk.coe`
207			`false`
208			`0`
209			`false`
210			`false`
211			`CE`
212			`0`
213			`false`
214			`false`
215			`CE`
216			`0`
217			`SYNC`
218			`false`
219			`100`
220			`0`
221			`100`
222			`0`
223			`100`
224			`100`
225			`ALL`
226			`false`
227			`false`
228			`Stand_Alone`
229			`no_Mem_file_loaded`
230
231
232
233
234			`coregen`
235			`./`
236			`./tmp/`
237			`./tmp/_cg/`
238
239
240			`xc6slx9`
241			`spartan6`
242			`tqg144`
243			`-2`
244
245
246			`BusFormatAngleBracketNotRipped`
247			`VHDL`
248			`true`
249			`Other`
250			`false`
251			`false`
252			`false`
253			`Ngc`
254			`false`
255
256
257			`Behavioral`
258			`VHDL`
259			`false`
260
261
262			`2012-11-19+16:22`
263
264
265
266
267
268			`cmpOnData_memblk`
269
270
271			`cmpOnData_memblk`
272			`Native`
273			`AXI4_Full`
274			`Memory_Slave`
275			`false`
276			`4`
277			`Dual_Port_ROM`
278			`false`
279			`No_ECC`
280			`false`
281			`false`
282			`false`
283			`Single_Bit_Error_Injection`
284			`false`
285			`9`
286			`Minimum_Area`
287			`8kx2`
288			`false`
289			`16`
290			`16384`
291			`16`
292			`WRITE_FIRST`
293			`Always_Enabled`
294			`16`
295			`16`
296			`WRITE_FIRST`
297			`Always_Enabled`
298			`false`
299			`false`
300			`false`
301			`false`
302			`false`
303			`false`
304			`false`
305			`false`
306			`0`
307			`true`
308			`./cmpOnData_memblk.coe`
309			`false`
310			`0`
311			`false`
312			`false`
313			`CE`
314			`0`
315			`false`
316			`false`
317			`CE`
318			`0`
319			`SYNC`
320			`false`
321			`100`
322			`0`
323			`100`
324			`0`
325			`100`
326			`100`
327			`ALL`
328			`false`
329			`false`
330			`Stand_Alone`
331			`no_Mem_file_loaded`
332
333
334
335
336			`coregen`
337			`./`
338			`./tmp/`
339			`./tmp/_cg/`
340
341
342			`xc6slx9`
343			`spartan6`
344			`tqg144`
345			`-2`
346
347
348			`BusFormatAngleBracketNotRipped`
349			`VHDL`
350			`true`
351			`Other`
352			`false`
353			`false`
354			`false`
355			`Ngc`
356			`false`
357
358
359			`Behavioral`
360			`VHDL`
361			`false`
362
363
364			`2012-11-19+16:22`
365
366
367
368
369
370			`timerCT_memblk`
371
372
373			`timerCT_memblk`
374			`Native`
375			`AXI4_Full`
376			`Memory_Slave`
377			`false`
378			`4`
379			`Simple_Dual_Port_RAM`
380			`false`
381			`No_ECC`
382			`false`
383			`false`
384			`false`
385			`Single_Bit_Error_Injection`
386			`false`
387			`9`
388			`Minimum_Area`
389			`8kx2`
390			`true`
391			`16`
392			`64`
393			`16`
394			`READ_FIRST`
395			`Use_ENA_Pin`
396			`16`
397			`16`
398			`READ_FIRST`
399			`Use_ENB_Pin`
400			`false`
401			`false`
402			`false`
403			`false`
404			`false`
405			`false`
406			`false`
407			`false`
408			`0`
409			`false`
410			`no_coe_file_loaded`
411			`false`
412			`0`
413			`false`
414			`false`
415			`CE`
416			`0`
417			`false`
418			`false`
419			`CE`
420			`0`
421			`SYNC`
422			`false`
423			`100`
424			`50`
425			`100`
426			`0`
427			`100`
428			`100`
429			`ALL`
430			`false`
431			`false`
432			`Stand_Alone`
433			`no_Mem_file_loaded`
434
435
436
437
438			`coregen`
439			`./`
440			`./tmp/`
441			`./tmp/_cg/`
442
443
444			`xc6slx9`
445			`spartan6`
446			`tqg144`
447			`-2`
448
449
450			`BusFormatAngleBracketNotRipped`
451			`VHDL`
452			`true`
453			`Other`
454			`false`
455			`false`
456			`false`
457			`Ngc`
458			`false`
459
460
461			`Behavioral`
462			`VHDL`
463			`false`
464
465
466			`2012-11-19+16:22`
467
468
469
470
471
472			`timer_memblk`
473
474
475			`timer_memblk`
476			`Native`
477			`AXI4_Full`
478			`Memory_Slave`
479			`false`
480			`4`
481			`True_Dual_Port_RAM`
482			`false`
483			`No_ECC`
484			`false`
485			`false`
486			`false`
487			`Single_Bit_Error_Injection`
488			`false`
489			`9`
490			`Minimum_Area`
491			`8kx2`
492			`true`
493			`16`
494			`256`
495			`16`
496			`WRITE_FIRST`
497			`Use_ENA_Pin`
498			`16`
499			`16`
500			`WRITE_FIRST`
501			`Use_ENB_Pin`
502			`false`
503			`false`
504			`false`
505			`false`
506			`false`
507			`false`
508			`false`
509			`false`
510			`0`
511			`false`
512			`no_coe_file_loaded`
513			`false`
514			`0`
515			`false`
516			`false`
517			`CE`
518			`0`
519			`false`
520			`false`
521			`CE`
522			`0`
523			`SYNC`
524			`false`
525			`100`
526			`50`
527			`100`
528			`50`
529			`100`
530			`100`
531			`ALL`
532			`false`
533			`false`
534			`Stand_Alone`
535			`no_Mem_file_loaded`
536
537
538
539
540			`coregen`
541			`./`
542			`./tmp/`
543			`./tmp/_cg/`
544
545
546			`xc6slx9`
547			`spartan6`
548			`tqg144`
549			`-2`
550
551
552			`BusFormatAngleBracketNotRipped`
553			`VHDL`
554			`true`
555			`Other`
556			`false`
557			`false`
558			`false`
559			`Ngc`
560			`false`
561
562
563			`Behavioral`
564			`VHDL`
565			`false`
566
567
568			`2012-11-19+16:22`
569
570
571
572
573
574
575
576
577			`coregen`
578			`./`
579			`./tmp/`
580			`./tmp/_cg/`
581
582
583			`xc6slx9`
584			`spartan6`
585			`tqg144`
586			`-2`
587
588
589			`BusFormatAngleBracketNotRipped`
590			`VHDL`
591			`true`
592			`Other`
593			`false`
594			`false`
595			`false`
596			`Ngc`
597			`false`
598
599
600			`Behavioral`
601			`VHDL`
602			`false`
603
604
605
606
607